TW201701491A - Solar cell manufacturing method - Google Patents

Abstract

Method including the steps of (a) providing a semiconductor substrate (1) including a first surface (10) and a second opposite surface (11), the substrate (1) including a first semiconductor area (100) including boron atoms, the first semiconductor area (100) being intended to be in contact with an electrode (E), the method being remarkable in that it includes the steps of (b) forming a dielectric layer (2) at the second surface (11) of the substrate (1), the dielectric layer (2) comprising phosphorus or arsenic atoms, (c) applying a thermal anneal capable of diffusing the phosphorus or arsenic atoms from the dielectric layer (2) all the way to the second surface (11) of the substrate (1) to form a second semiconductor area (110) intended to be in contact with an electrode (E) and to form a thermal oxide layer (3) at the first surface (10) of the substrate (1).

Description

Solar cell manufacturing method

The invention relates to a method of manufacturing a solar cell.

The first known method in the prior art includes the following steps: a0) providing a semiconductor substrate made of a material based on an n-type doped crystalline germanium, the substrate including a first surface and a first a second reverse surface, b0) implanting boron atoms at the first surface of the substrate to form a first semiconductor region, the first semiconductor region is expected to contact an electrode, and c0) is at the second of the substrate Phosphorus or arsenic atoms are implanted at the surface to form a second semiconductor region, which is expected to contact an electrode, d0) thermally anneal the substrate, which is capable of thermally activating the boron atoms and the Phosphorus atom or arsenic atom.

The first surface and the second surface of the substrate may be exposed to an optical radiation for obtaining a double-sided type solar cell.

The thermal activation temperature of the boron atom is higher than the thermal activation temperature of the phosphorus atom or the arsenic atom, and the size is 150 °C. Therefore, the temperature of the thermal annealing is affected by the thermal activation temperature of the boron atoms.

Since the annealing temperatures of the phosphorus atoms are too high compared to their thermal activation temperatures, the execution of step d0) causes the phosphorus atoms to uniformly diffuse into the substrate. Next, the phosphorus atom It will be away from the second surface of the substrate, and the corresponding contact area used as an electrode may become inoperable.

Execution of step d0) causes the arsenic atoms to diffuse outward from the substrate, with the result that their surface concentration is lowered, and the corresponding contact region used as an electrode may become inoperable.

In order to overcome the above disadvantages, the second known method in the prior art includes the following successive steps: a01) providing a semiconductor substrate made of a material based on n-type doped crystalline germanium, the substrate Including a first surface and a second reverse surface, b01) implanting boron atoms at the first surface of the substrate to form a first semiconductor region, the first semiconductor region is expected to contact an electrode, c01 Thermally annealing the substrate to thermally activate the boron atoms, d01) depositing phosphorus atoms or arsenic atoms at the second surface of the substrate to form a second semiconductor region, the second semiconductor region It is expected that an electrode will be contacted, e01) to thermally anneal the substrate, which is capable of thermally activating the phosphorus or arsenic atoms.

Therefore, this second method in the prior art performs the thermal annealing during different steps, and thus avoids diffusing phosphorus atoms in the substrate or allowing arsenic atoms to diffuse outward from the substrate at an inappropriate timing. .

The fabrication of a solar cell is carried out by forming a first dielectric layer and a second dielectric layer on the first surface and the second surface of the substrate to passivate the surfaces. The first dielectric layer and the second dielectric layer are thermal oxide layers.

Now, since the second dielectric layer is formed faster than the first dielectric layer The relationship between the speeds (because the surface concentration of the phosphorus or arsenic atoms is greater than the surface concentration of the boron atoms in the prior art), this second method in the prior art is not entirely satisfactory. This may result in the formation of a second dielectric layer that is too thick, for example, it is not possible to obtain an electrical contact by silk-screening.

The present invention is directed to overcoming all or some of the disadvantages mentioned above, and to achieve the object, the present invention relates to a method of fabricating a solar cell comprising the steps of: a) providing a semiconductor substrate by An n-doped crystalline germanium-based material, the substrate comprising a first surface and a second reverse surface, a1) forming a first semiconductor region, which is expected to contact an electrode, the first semiconductor The fauna is formed by implanting boron atoms in the substrate, notably, the method comprising the steps of: b) forming a dielectric layer at the second surface of the substrate, the dielectric layer comprising a phosphorus atom Or an arsenic atom, and the dielectric layer and the substrate form a structure, c) thermally annealing the structure, capable of: forming a second semiconductor region that is expected to contact an electrode, the second semiconductor region borrowing Forming the phosphorus or arsenic atoms from the dielectric layer to the second surface of the substrate to the substrate, forming a cerium oxide at the first surface of the substrate Basic Thermal oxide layer.

Thus, the method according to the present invention can be avoided by forming the dielectric layer on the second surface of the substrate in step b) prior to forming the thermal oxide layer at step c) A too thick thermal oxide type dielectric layer is formed on the second surface of the substrate.

Further, this method according to the present invention can reduce the cost and shorten the operation time because the second semiconductor region can be formed and the first surface of the substrate can be passivated by performing step c) alone.

The meaning of "crystallization" is a polycrystalline form or a single crystal form of ruthenium, and thus the present invention excludes amorphous ruthenium. The n-type doping of germanium can improve the efficiency of solar cells.

According to an embodiment, step b) comprises a step b1) for forming an additional dielectric layer on the dielectric layer, preferably a system of hydrogenated tantalum nitride, and thermally annealed The structure including the additional dielectric layer will be performed at step c).

Thus, the additional dielectric layer forms a barrier to prevent diffusion of phosphorus or arsenic atoms toward the outer dielectric and to improve passivation of the second surface of the substrate. The advantage of this additional dielectric layer is that it does not include any phosphorus or arsenic atoms.

Further, this material can achieve the following two purposes: to improve the passivation of the second surface of the substrate; and to form a so-called optical anti-reflective layer due to an adapted thickness relationship. The optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thereby optimize the optical radiation absorbed by the substrate.

According to an embodiment, the annealing is performed in an oxidizing environment in step c), and the annealing preferably has an annealing temperature value falling within a range of 850 ° C to 950 ° C and falling within a range of 5 minutes to 1 hour. The value of the annealing duration length.

Therefore, this thermal budget can diffuse phosphorus atoms or arsenic atoms at the second surface of the substrate. The annealing temperature mainly adjusts the surface concentration of the phosphorus atom or the arsenic atom, and the length of the annealing duration mainly adjusts the thermal diffusion length of the atoms.

The oxidizing environment can form a thermal oxide layer at the first surface of the substrate.

Step c) is performed continuously; forming the second semiconductor region and forming the thermal oxide layer are performed together.

The meaning of "thermal budget" is to select the annealing temperature value and select the annealing duration length value.

According to an alternative implementation, step c) comprises the steps of: c1) performing a thermal annealing according to a first thermal budget, the first thermal budget being adapted to diffuse phosphorus or arsenic atoms to form the second semiconductor region, The first thermal budget preferably has an annealing temperature value falling within the range of 850 ° C to 950 ° C and an annealing duration length value falling within the range of 5 minutes to 1 hour, c2) being carried out in an oxidizing environment According to thermal annealing of the second thermal budget, the second thermal budget is adapted to form the thermal oxide layer, and the second thermal budget preferably has an annealing temperature falling within the range of 700 ° C to 800 ° C The value and the length of the annealing duration falling within the range of 5 minutes to 1 hour.

Thus, the formation of the second semiconductor region and the formation of the thermal oxide layer continuity are performed and can be performed in reverse order. It is advantageous to perform step c1) before step c2).

In one aspect, the first thermal budget can diffuse phosphorus or arsenic atoms at the second surface of the substrate. The annealing temperature mainly adjusts the surface concentration of the phosphorus atom or the arsenic atom, and the length of the annealing duration mainly adjusts the thermal diffusion length of the atoms.

In another aspect, the second thermal budget can thermally oxidize the first surface of the substrate, the substrate being made of a material based on crystalline germanium.

According to an embodiment, the dielectric layer formed at step b) is based on bismuth oxynitride SiO _x N _y , which is confirmed to be 0 x < y, a preferred system, is hydrogenated.

Therefore, the bismuth oxynitride SiO _x N _y , 0 x < y, the second surface of the substrate can be passivated, the substrate being made of a material based on crystalline germanium. When x = 0, the niobium oxynitride is tantalum nitride. Hydrogenated bismuth oxynitride is particularly advantageous because of the presence of hydrogen which improves the quality of the passivation. It is thus not necessary to etch the dielectric layer after step c) and then deposit a dedicated passivation layer. In other words, the dielectric layer can be retained after step c) in the method according to the invention.

The advantage is that the bismuth oxynitride SiO _x N _y at step b) and after step c) is confirmed to be 0 x 0.05.

The advantage is that the bismuth oxynitride SiO _x N _y at step b) and after step c) is confirmed to be 0.30 x 0.05.

According to an alternative embodiment, the dielectric layer formed at step b) is based on tantalum carbide.

According to an embodiment, the atomic content of phosphorus or arsenic atoms in the dielectric layer formed at step b) falls within the range of 1% to 10%; and in the dielectric layer after step c) The atomic content of the phosphorus atom or the arsenic atom falls within the range of 1% to 10%, and preferably, falls within the range of 1% to 5%.

Of course, the atomic content of phosphorus or arsenic atoms in the dielectric layer after step c) is less than the atomic content at step b).

Therefore, when the dielectric layer formed at step b) is yttria SiO _x N _y , 0 When x<y is the basis, preferably, the atomic content of the hydrogen atom, phosphorus atom or arsenic atom can achieve the following two purposes: forming a second semiconductor region and thus forming a good quality electrical contact region, that is, the surface atomic concentration of greater than 10 ^{20 at./cm 3,} the preferred system, fall within the scope of 3x10 ²⁰ at./cm ³ to 5x10 ²⁰ at./cm ^3, the good passivation quality of the dielectric layer The too high phosphorus atom or arsenic atom content will affect these passivation characteristics.

According to an embodiment, the thermal annealing performed at step c) is adapted to thermally activate the boron atoms of the first semiconductor region implanted at step a1).

Thus, proprietary thermal annealing may not be required to thermally activate the previously implanted boron atoms. This is especially the case when the boron atoms are implanted in the substrate in small doses (i.e., less than 10 ¹⁵ at./cm ² ) and with energy falling within the range of 5 keV to ¹⁵ keV.

According to an alternative embodiment, step a) comprises a step a2) which thermally annealing the substrate according to a thermal budget, the thermal budget being adapted to thermally activate the boron atoms of the first semiconductor region; step a2 The method is performed before step b), and the thermal annealing performed at step a2) preferably has an annealing temperature value falling within the range of 1,000 ° C to 1,100 ° C and an annealing duration length value of more than 1 minute. .

Therefore, this thermal budget can thermally activate the boron atoms.

The invention further relates to a method of fabricating a solar cell comprising the steps of: a) providing a semiconductor substrate made of a p-type doped crystalline germanium-based material, the substrate comprising a first surface and a second reverse surface, a1) forming a first semiconductor region which is expected to contact an electrode formed by implanting phosphorus atoms or arsenic atoms in the substrate, notably The method includes The following steps: b) forming a dielectric layer at the second surface of the substrate, the dielectric layer includes boron atoms, and the dielectric layer and the substrate form a structure, c) thermally annealing the structure, It is capable of: forming a second semiconductor region which is expected to contact an electrode, the second semiconductor region being diffused from the dielectric layer to the second surface of the substrate to the substrate Formed therein, a thermal oxide layer based on cerium oxide is formed on the first surface of the substrate.

When the substrate is made of a material based on p-type doped crystalline germanium, annealing at a high temperature (i.e., above 950 ° C) destroys the volume quality of the substrate and thereby shortens The life of the charge carrier. Therefore, it is not recommended to perform implantation of boron atoms in this substrate first, followed by thermal activation at a temperature higher than 950 °C.

Therefore, this method according to the present invention can overcome the above because of the relationship of step b) and because of the annealing performed at step c) to diffuse boron atoms from the dielectric layer to the second surface of the substrate. The disadvantages mentioned. The diffusion of boron atoms can be carried out at a temperature falling within the range of 900 ° C to 950 ° C, and thus does not change the volume quality of the substrate. Further, the annealing performed at step c) can synchronously thermally activate the phosphorus atom or the arsenic atom of the first semiconductor region implanted at step a1) because the thermal activation temperature of the phosphorus atom or the arsenic atom is less than the diffusion of the boron atom. temperature.

According to an embodiment, the method comprises a step b1) for forming an additional dielectric layer on the dielectric layer, preferably a system of hydrogenated tantalum nitride, and the steps B1) Preferably, it is performed after step c).

Thus, this additional dielectric layer improves the passivation of the second surface of the substrate. The advantage of this additional dielectric layer is that it does not include any boron atoms.

Preferably, step b1) is performed after step c) such that the dielectric layer can be oxidized when the step c) is annealed in an oxidizing environment. Oxidation of the dielectric layer can improve passivation of the second surface of the substrate.

Further, this material can achieve the following two purposes: to improve the passivation of the second surface of the substrate; and to form a so-called optical anti-reflective layer due to an adapted thickness relationship. The optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thereby optimize the optical radiation absorbed by the substrate.

According to an embodiment, the annealing is performed in an oxidizing environment in step c), and the annealing preferably has an annealing temperature value falling within a range of 900 ° C to 950 ° C and falling within 5 minutes to 1 hour. The length of the annealing duration in the range.

Thus, this thermal budget can: diffuse boron atoms at the second surface of the substrate, thermally activating the phosphorus or arsenic atoms of the first semiconductor region implanted at step a1).

The annealing temperature mainly adjusts the surface concentration of the boron atoms, and the length of the annealing duration mainly adjusts the thermal diffusion length of the atoms.

Further, the oxidizing environment can: form a thermal oxide layer at the first surface of the substrate, and oxidize the dielectric layer when step b1) is performed after step c) to improve passivation.

Step c) is performed continuously; forming the second semiconductor region and forming the hot oxygen The layers are carried out together.

The meaning of "thermal budget" is to select the annealing temperature value and select the annealing duration length value.

According to an embodiment, the dielectric layer formed at step b) is based on bismuth oxynitride SiO _x N _y , which is confirmed to be 0 y < x, a preferred system, is hydrogenated.

Therefore, the bismuth oxynitride SiO _x N _y , 0 y < x, the second surface of the substrate can be passivated, the substrate being made of a material based on crystalline germanium. When y = 0, the bismuth oxynitride is cerium oxide. Hydrogenated bismuth oxynitride is particularly advantageous because of the presence of hydrogen which improves the quality of the passivation.

The advantage is that the bismuth oxynitride SiO _x N _y after step c) is confirmed to be x 0.50, preferred system, 0.50 x 0.66.

The advantage is that the cerium oxynitride SiO _x N _y during step b) is confirmed to be x < 0.50.

Advantages based, in step b) and the silicon oxynitride after step c), SiO _x N _y confirmed 0 y 0.10, preferred system, 0 y 0.05.

According to an alternative embodiment, the dielectric layer formed at step b) is based on tantalum carbide.

According to an embodiment, the atomic content of boron atoms in the dielectric layer formed at step b) falls within the range of 10% to 50%, preferably in the range of 10% to 30%. And the atomic content of boron atoms in the dielectric layer after step c) falls within the range of 1% to 10%, preferably, falls within the range of 3% to 8%.

Therefore, when the dielectric layer formed at step b) is yttria SiO _x N _y , 0 When y<x is the basis, preferably, after hydrogenation, the atomic content of the boron atom can achieve the following two purposes: forming a second semiconductor region and thus forming a good quality electrical contact region, that is, the surface The atomic concentration is greater than 10 ¹⁹ at./cm ³ , preferably, falling within the range of 10 ¹⁹ at./cm ³ to 3 x 10 ²⁰ at./cm ³ to maintain good passivation quality of the dielectric layer, too high The boron atom content affects these passivation characteristics.

According to an embodiment, the first semiconductor region is formed at the first surface of the substrate at step a).

Thus, the fabricated solar layer has a double-sided type of architecture, that is, the first surface and the second surface of the substrate are expected to be exposed to an optical radiation. The first semiconductor region forms an emitter. The second semiconductor region is of the BSF (Back Surface Field) type having a heavy doping of the same doping type as the substrate in order to improve the efficiency of the solar cell.

According to an embodiment, the first semiconductor region is formed at the second surface of the substrate at step a) to form a first well, and the dielectric layers formed at step b) are arranged. The second semiconductor region formed by the atoms diffused at step c) forms a second well portion that is partially separated from the first well.

Therefore, the fabricated solar cell will have a single-sided type architecture with Interdigited Back Contact (IBC). The first surface of the substrate is expected to be exposed to an optical radiation. The first well and the second well are expected to each contact an electrode. An advantage of the first surface of the substrate is a heavily doped semiconductor region having the same doping type as the substrate to improve the efficiency of the solar cell, the semiconductor region being of the FSF (Front Surface Field) type .

The invention also relates to a solar cell that can be obtained by the method according to the invention.

Therefore, the difference between the solar cell and the prior art is that there is a dielectric layer formed at the second surface of the substrate, when the substrate is n-doped (or p-doped), the dielectric layer A boron atom (or a phosphorus atom or an arsenic atom, respectively) that does not always diffuse to the second surface of the substrate is included. The number of non-diffusing boron atoms (or phosphorus or arsenic atoms, respectively) is still sufficient to detect their presence in the dielectric layer, allowing the solar cell to be easily detected by reverse engineering.

The invention further relates to a solar cell comprising: a substrate made of a semiconductor material based on an n-type doped crystalline germanium, the substrate comprising a first surface and a second reverse surface; a semiconductor region and a second semiconductor region respectively extending under the first surface of the substrate and under the second surface of the substrate, the first semiconductor region comprising boron atoms, the second semiconductor region comprising phosphorus atoms or arsenic atoms; a first layer formed of a dielectric material formed at a second surface of the substrate, the dielectric material being based on bismuth oxynitride SiO _x N _y , which is confirmed to be 0 x < y, the dielectric material comprises a phosphorus atom or an arsenic atom and preferably comprises hydrogen; a thermal oxide layer based on cerium oxide is formed at the first surface of the substrate.

The first semiconductor region is expected to contact an electrode. The second semiconductor region is expected to contact an electrode. The first or second surface of the substrate is expected to be exposed to an optical radiation.

The advantage is that the bismuth oxynitride SiO _x N _{y is} confirmed to be 0. x 0.05.

The advantage is that the bismuth oxynitride SiO _x N _{y is} confirmed to be 0.30 x 0.05.

Advantageously, the atomic content of the phosphorus or arsenic atoms in the dielectric layer falls within the range of from 1% to 10%; preferably, it falls within the range of from 1% to 5%.

The invention further relates to a solar cell comprising: a substrate made of a p-type doped crystalline germanium-based semiconductor material, the substrate comprising a first surface and a second reverse surface; a semiconductor region and a second semiconductor region respectively extending under the first surface of the substrate and under the second surface of the substrate, the first semiconductor region comprising phosphorus atoms or arsenic atoms, and the second semiconductor region comprising boron atoms; a first layer formed of a dielectric material formed at a second surface of the substrate, the dielectric material being based on bismuth oxynitride SiO _x N _y , which is confirmed to be 0 y < x, the dielectric material comprises boron atoms and preferably comprises hydrogen; a thermal oxide layer based on cerium oxide, which is formed at the first surface of the substrate.

The first semiconductor region is expected to contact an electrode. The second semiconductor region is expected to contact an electrode. The first or second surface of the substrate is expected to be exposed to an optical radiation.

The advantage is that the bismuth oxynitride SiO _x N _{y is} confirmed to be x 0.50, preferred system, 0.50 x 0.66.

The advantage is that the bismuth oxynitride SiO _x N _{y is} confirmed to be 0. y 0.10, preferred system, 0 y 0.05.

The advantage is that the atomic content of boron atoms in the dielectric layer falls within the range of 1% to 10%; preferably, it falls within the range of 3% to 8%.

In one embodiment, the battery includes a second layer formed of a dielectric material formed on the first layer, and preferably, formed on the thermal oxide layer, the second layer The dielectric material is based on yttrium oxynitride SiO _x N _y , which is confirmed to be 0 Preferably, the dielectric material comprises hydrogen.

Advantageously, the first layer has a thickness that falls within the range of 3 nm to 100 nm.

1‧‧‧Semiconductor substrate

2‧‧‧Dielectric layer

3‧‧‧Thermal oxide layer

4‧‧‧Additional dielectric layer

5‧‧‧Dielectric layer

10‧‧‧ first surface

11‧‧‧ second surface

100‧‧‧First Semiconductor District

110‧‧‧second semiconductor area

120‧‧‧Semiconductor area

E‧‧‧electrode

The foregoing and other features and advantages will now be discussed in detail in the following non-limiting description of various embodiments of the method according to the present invention in conjunction with the accompanying drawings in which: FIG. A simplified cross-sectional view of a solar cell of a first architecture, FIG. 2 is a simplified cross-sectional view of a solar cell of a second architecture taken in accordance with the method of the present invention, and FIGS. 3a through 3e are used to fabricate FIG. A simplified cross-sectional view of the different steps of the method according to the invention of the solar cell shown, and a simplified cross-sectional view of the different steps of the method according to the invention for producing the solar cell shown in Fig. 1 shown in Figs. 4a to 4e .

To simplify the description, in the different embodiments, the same element symbols are used for identical elements or elements for performing the same function. The technical features described below for different embodiments will be discussed separately or in any technically possible combination.

The method shown in Figures 3a to 3e is a method of manufacturing a solar cell comprising the steps of: a) providing a semiconductor substrate 1 made of a material based on n-type doped crystalline germanium. The substrate 1 includes a first surface 10 and a second reverse surface 11, and a1) forms a first semiconductor region 100 which is expected to contact an electrode E. The first semiconductor region 100 is formed by the substrate 1 Formed with boron atoms, steps a) and a1) are shown in Figure 3a, b) a dielectric layer 2 is formed on the second surface 11 of the substrate 1, the dielectric layer 2 comprising phosphorus or arsenic atoms, and dielectric Layer 2 and substrate 1 form a structure 1, 2, step b) is shown in Figure 3b, c) thermal annealing of structures 1, 2, which can: form a second semiconductor region 110 which is expected to contact an electrode E, the second semiconductor region 110 is formed in the substrate 1 by diffusing the phosphorus atoms or arsenic atoms from the dielectric layer 2 to the second surface 11 of the substrate 1 on the first surface of the substrate 1. A thermal oxide layer 3 based on cerium oxide is formed at 10, and step c) is shown in Figure 3c.

In a non-limiting example, the substrate 1 has a thickness of 150 μm. The first semiconductor region 100 is formed at the first surface 10 of the substrate 1 at step a). The advantage of step a1) is ion implantation performed by an ion beam, ion shower, or plasma immersion. Ions may be generated (e.g., BF ₃ or B ₂ H ₆₎ at a precursor gas to the embodiment.

The advantage of the dielectric layer 2 formed at step b) is based on bismuth oxynitride SiO _x N _y , which is confirmed to be zero. x < y, preferably hydrogenated. When x = 0, the niobium oxynitride is tantalum nitride. The advantage of the bismuth oxynitride SiO _x N _y is confirmed to be 0 at step b) and after step c) x 0.05. The advantage of the bismuth oxynitride SiO _x N _y is confirmed at step b) and after step c) is 0.30 x 0.55. The advantage of the phosphorus or arsenic atoms in the dielectric layer 2 formed at step b) is that the atomic content falls within the range of 1% to 10%. The advantage of the phosphorus or arsenic atoms in the dielectric layer 2 after the step c) is that the atomic content falls within the range of 1% to 10%, and preferably, falls within the range of 1% to 5%. Among them. This atomic content can achieve a good quality electronic contact region, that is, the atomic surface concentration is greater than 10 ^{20 at. /} cm ³ , preferably, the front 25 nanometers beyond the substrate 1 will fall at 3 x 10 ^{20 at. /} cm ³ to 5x10 ²⁰ at./cm ³ range. The advantage of the dielectric layer 2 is that the thickness falls within the range of 10 nm to 40 nm. This thickness allows for little optical loss due to reflection of the light radiation while maintaining good passivation quality. When the dielectric layer 2 is made of a material based on hydrogenated tantalum nitride, the advantage of step b) is from the chemical gas phase in a reaction gas comprising decane (SiH ₄ ) and ammonia (NH ₃ ). Deposition (Plasma-Enhanced Chemical Vapor Deposition (PECVD)) is performed. When the dielectric layer 2 is made of a material based on hydrogenated bismuth oxynitride, the advantage of step b) is by PECVD in a reaction gas comprising decane (SiH ₄ ) and nitrous oxide (N ₂ O). To execute. When the dielectric layer 2 includes a phosphorus atom, the advantages of the atoms are incorporated into the hydrogenated tantalum nitride by injecting phosphine (PH ₃ ) and a corresponding reaction gas or are incorporated into the hydrogenation. Niobium oxynitride. When the dielectric layer 2 includes arsenic atoms, the advantages of the atoms are incorporated into the hydrogenated tantalum nitride by injecting arsine (AsH ₃ ) and a corresponding reaction gas or are incorporated into the hydrogenation. Niobium oxynitride.

According to a variant, the dielectric layer 2 formed at step b) is based on tantalum carbide. The advantages of step b) are performed by PECVD in a reaction gas comprising decane (SiH ₄ ) and methane (CH ₄ ). When the dielectric layer 2 includes a phosphorus atom, the advantages of the atoms are incorporated into the tantalum carbide by injecting phosphine (PH ₃ ) and a corresponding reaction gas. When the dielectric layer 2 comprises an arsenic atom, these atoms advantage of this system is due to injection of arsine (AsH ₃₎ and the corresponding reaction gas is incorporated into the silicon carbide.

The advantages of the method include a step b1) for forming an additional dielectric layer 4 on the dielectric layer 2, and the thermal annealing will form the structures 1, 2, 4 including the additional dielectric layer 4 at step c). Come on. The advantage of the additional dielectric layer 4 formed at step b1) is made of hydrogenated tantalum nitride. The advantage of the additional dielectric layer 4 is that the thickness is greater than 30 nm. The thickness of the additional dielectric layer 4 is adjusted to form an optical anti-reflective layer. This optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thus optimize the optical radiation absorbed by the substrate 1.

According to an embodiment, the annealing is carried out in an oxidizing environment in step c). The oxidizing environment may comprise a mixture of N ₂ gas and O ₂ gas, preferably a ratio of N ₂ /O ₂ between 0.2 and 1. This environment is called "dry". According to a variant, the oxidizing environment may comprise a mixture of N ₂ gas and water vapour. This environment is called "wet." The advantage of this oxidizing environment consists of oxygen and a mixture of neutral gases selected from argon, nitrogen, or a mixture of argon and nitrogen. The advantage of this oxidizing environment is that it does not include any dopants, such as phosphine. The advantage of this annealing is that it has an annealing temperature value falling within the range of 850 ° C to 950 ° C and an annealing duration length value falling within the range of 5 minutes to 1 hour.

According to an alternative embodiment, step c) comprises the step of: c1) performing a thermal annealing according to a first thermal budget capable of diffusing phosphorus or arsenic atoms to form a second semiconductor region 110, the first thermal budget Preferably, the annealing temperature value falling within the range of 850 ° C to 950 ° C and the annealing duration length value falling within the range of 5 minutes to 1 hour, c2) are carried out under an oxidizing environment according to the second heat Thermal annealing of the budget.

The advantage of step c2) is performed in a "wet" oxidizing environment such that the second thermal budget has an annealing temperature value falling within the range of 700 ° C to 800 ° C and falling within the range of 5 minutes to 1 hour The value of the annealing duration length. The "wet" oxidizing environment can substantially reduce the annealing temperature value compared to a "dry" oxidizing environment.

According to an embodiment, step a1) is performed such that the boron atoms are implanted in the substrate 1 at a dose which is indeed less than 10 ¹⁵ at./cm ² and with an energy falling within the range of 5 keV to ¹⁵ keV. Next, the thermal annealing performed at step c) is capable of thermally activating the boron atoms of the first semiconductor region 100. The advantage of the ceria-based thermal oxide layer 3 formed at step c) is that it has a thickness falling within the range of 5 nm to 20 nm. This thickness allows for little optical loss due to reflection of the light radiation while maintaining good passivation quality.

According to an alternative embodiment, step a1) is performed such that the boron atoms are at a dose greater than 10 ¹⁵ at./cm ² , preferably at 10 ¹⁵ at./cm ² to 10 ¹⁶ at./ Among the ranges of cm ² , and energy falling in the range of 5 keV to 15 keV is implanted in the substrate 1. These implant parameters provide a good quality electrical contact region, that is, an atomic surface concentration greater than 10 ¹⁹ at./cm ³ , preferably a system falling at 10 ¹⁹ at./cm ³ to 5 x 10 ¹⁹ at. Within the range of /cm ³ . Next, step a) includes a step a2) of thermally annealing the substrate 1 according to a thermal budget, the thermal budget being adapted to thermally activate the boron atoms of the first semiconductor region 100, and step a2) is in step b ) was executed before. The advantage of the thermal annealing performed at step a2) is an annealing temperature value falling within the range of 1,000 ° C to 1,100 ° C and an annealing duration length value of more than 1 minute. The advantages of step a2) are performed in an environment including nitrogen and no oxygen. The advantage of step a2) is followed by a chemical cleaning step on substrate 1. The advantage of the ceria-based thermal oxide layer 3 formed at step c) is that it has a thickness falling within the range of 5 nm to 20 nm. This thickness allows for little optical loss due to reflection of the light radiation while maintaining good passivation quality.

As shown in Figure 3d, the advantages of the method include a step d) for forming a dielectric layer 5 on the thermal oxide layer 3. The dielectric layer 5 formed at step d) is preferably made of a material based on tantalum nitride. The thickness of the dielectric layer 5 formed at step d) is adjusted Formed to form an optical anti-reflective layer. The advantage of the dielectric layer 5 formed at step d) is that it has a thickness that falls within the range of 50 nm to 75 nm. This optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thus optimize the optical radiation absorbed by the substrate 1.

As shown in Figure 3e, the advantages of the method include a step e) for contacting each of the first semiconductor region 100 and the second semiconductor region 110 with an electrode E. Step e) comprises a metallization step, preferably by a wire mesh method.

According to an embodiment shown in FIG. 2, the method differs from the mode shown in FIGS. 3a to 3e in that the first semiconductor region 100 is formed at the second surface 11 of the substrate 1 at step a), preferably The system is formed by a first set of masks to form a first well. The dielectric layer 2 formed at step b) is arranged, preferably, by a second set of masks such that the phosphorus or arsenic atoms diffused at step c) are formed. The second semiconductor region 110 forms a second well portion that is partially separated from the first well. The advantages of the method include the step of forming a semiconductor region 120 at the first surface 10 of the substrate 1. The semiconductor region 120 includes a phosphorus atom or an arsenic atom. The advantages of the semiconductor region 120 are formed by ion implantation of phosphorus atoms or arsenic atoms. These atoms will be thermally activated at step c). The advantages of the method include the step of forming a dielectric layer (not shown in FIG. 2) on the thermal oxide layer 3. The formed dielectric layer is preferably formed by a tantalum nitride-based layer. Made of materials. The thickness of the formed dielectric layer is adjusted to form an optical anti-reflective layer. This optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thus optimize the optical radiation absorbed by the substrate 1.

The invention further relates to a method of fabricating a solar cell, shown in Figures 4a to 4e, the method comprising the steps of: a) providing a semiconductor substrate 1 made of a p-type doped crystalline germanium-based material, the substrate 1 comprising a first surface 10 and a second reverse surface 11, a1) forming a first The semiconductor region 100 is expected to contact an electrode E formed by implanting phosphorus atoms or arsenic atoms in the substrate 1, steps a) and a1) are shown in FIG. 3a, and b) is on the substrate. A dielectric layer 2 is formed on the second surface 11 of the dielectric layer 2, the dielectric layer 2 comprises boron atoms, the dielectric layer 2 and the substrate 1 form a structure 1, 2, the step b) is shown in Figure 3b, and c) the structure 1, 2 performing thermal annealing, which can: form a second semiconductor region 110 which is expected to contact an electrode E, and the second semiconductor region 110 is diffused from the dielectric layer 2 to the substrate 1 by the boron semiconductor atoms The second surface 11 is formed into the substrate 1 to form a thermal oxide layer 3 based on cerium oxide at the first surface 10 of the substrate 1, and step c) is shown in Figure 3c.

In a non-limiting example, the substrate 1 has a thickness of 150 μm. The first semiconductor region 100 is formed at the first surface 10 of the substrate 1 at step a). The advantage of step a1) is ion implantation performed by ion beam, ion shower, or plasma immersion. The advantages of step a1) are performed such that the phosphorus or arsenic atoms are implanted in the substrate 1 at a dose falling within the following range: when the first surface 10 of the substrate 1 is textured to have a pyramid when shaped profile, the dose will fall within the scope of 10 ¹⁵ at./cm ² to 5x10 ¹⁵ at./cm ² when the first surface 10 of the substrate 1 is flat, and may pass during polishing, the dose will fall It is in the range of 0.5 x 10 ¹⁵ at./cm ² to 3 x 10 ¹⁵ at./cm ² .

The advantage of these phosphorus atoms is that at step a1) the energy falling in the range of 5 keV to 15 keV is implanted. The advantage of these arsenic atoms is that at step a1) the energy falling within the range of 15 keV to 30 keV is implanted. Advantage that in step b) a dielectric layer formed at the line 2 to the silicon oxynitride SiO _x N _y basis, which proved to 0 y < x, preferably hydrogenated. When y = 0, the bismuth oxynitride is cerium oxide. The advantage of the cerium oxynitride SiO _x N _y is confirmed to be x after step c) 0.50, preferred system, 0.50 x 0.66. The advantage of the bismuth oxynitride SiO _x N _y is confirmed to be 0 at step b) and after step c) y 0.10, preferred system, 0 y 0.05. The advantage of the boron atoms in the dielectric layer 2 formed at step b) is that the atomic content falls within the range of 10% to 50%, preferably, falls within the range of 10% to 30%. The advantage of the boron atom in the dielectric layer 2 after the step c) is that the atomic content falls within the range of 1% to 10%, preferably, falls within the range of 3% to 8%. The advantage of the dielectric layer 2 formed at step b) is that the nitrogen content is greater than 5%, preferably in the range of from 5% to 15%. The advantage of the dielectric layer 2 is that the thickness falls within the range of 3 nm to 100 nm, preferably, falls within the range of 20 nm to 35 nm. This thickness allows for little optical loss due to reflection of the light radiation while maintaining good passivation quality. Steps a1) and b) can be exchanged. When the dielectric layer 2 is made of a material based on hydrogenated bismuth oxynitride, the advantage of step b) is chemistry in a reaction gas comprising decane (SiH ₄ ) and nitrous oxide (N ₂ O). Vapor deposition (plasma enhanced chemical vapor deposition (PECVD)) is performed. The advantages of these boron atoms are incorporated into the hydrogenated bismuth oxynitride by the injection of diborane (B ₂ H ₆ ) and a reactive gas.

According to a variant, the dielectric layer 2 formed at step b) is based on tantalum carbide. Step b) is performed by PECVD based advantage in the reaction gas comprises Silane (SiH ₄₎ and methane (CH ₄₎ in. The advantages of these boron atoms are incorporated into the tantalum carbide by the injection of borane (B ₂ H ₆ ) and the reaction gases.

The advantage of the method comprises a step b1) for forming an additional dielectric layer 4 on the dielectric layer 2. Step b1) is shown in Figure 3c. The advantage of step b1) is carried out after step c) such that when annealing is carried out in an oxidizing environment in step c), the dielectric layer 2 can be oxidized. Oxidation of the dielectric layer 2 can improve passivation of the second surface 11 of the substrate 1. The advantage of the additional dielectric layer 4 is made of hydrogenated tantalum nitride. The advantage of the additional dielectric layer 4 is that the thickness is greater than 30 nm. The thickness of the additional dielectric layer 4 is adjusted to form an optical anti-reflective layer. This optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thus optimize the optical radiation absorbed by the substrate 1.

According to an embodiment, the annealing is carried out in an oxidizing environment in step c). The oxidizing environment may comprise a mixture of N ₂ gas and O ₂ gas, preferably a ratio of N ₂ /O ₂ between 0.2 and 1. This environment is called "dry". According to a variant, the oxidizing environment may comprise a mixture of N ₂ gas and water vapour. This environment is called "wet."

The advantage of the annealing performed at step c) is that it has an annealing temperature value falling within the range of 900 ° C to 950 ° C and an annealing duration length value falling within the range of 5 minutes to 1 hour, in a dry environment get on.

The advantage of the ceria-based thermal oxide layer 3 formed at step c) is a non-zero thickness of less than 30 nm. This thickness allows for little optical loss due to reflection of the light radiation while maintaining good passivation quality.

As shown in Figure 4d, the advantages of the method include a step d) for forming a dielectric layer 5 on the thermal oxide layer 3. The dielectric layer 5 formed at step d) is preferably made of a material based on tantalum nitride. The thickness of the dielectric layer 5 formed at step d) is adjusted to form an optical anti-reflective layer. The advantage of the dielectric layer 5 formed at step d) is A thickness falling within the range of 50 nm to 75 nm. This optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thus optimize the optical radiation absorbed by the substrate 1.

As shown in FIG. 4e, the advantages of the method include a step e) for contacting each of the first semiconductor region 100 and the second semiconductor region 110 with an electrode E. Step e) comprises a metallization step, preferably by a wire mesh method.

According to an embodiment shown in FIG. 2, the method differs from the mode shown in FIGS. 4a to 4e in that the first semiconductor region 100 is formed at the second surface 11 of the substrate 1 at step a), preferably. The system is formed by a first set of masks to form a first well. The dielectric layers 2 formed at step b) are arranged, preferably, by a second set of masks such that the second semiconductor region formed by the boron atoms diffused at step c) 110 will form a second well portion that is partially separated from the first well.

The advantages of the method include the step of forming a semiconductor region 120 at the first surface 10 of the substrate 1. The semiconductor region 120 includes a phosphorus atom or an arsenic atom.

The advantages of the method include the step of forming a dielectric layer (not shown in FIG. 2) on the thermal oxide layer 3. The formed dielectric layer is preferably formed by a tantalum nitride-based layer. Made of materials. The thickness of the formed dielectric layer is adjusted to form an optical anti-reflective layer. This optical anti-reflective layer can reduce the optical loss caused by the reflection of the optical radiation and thus optimize the optical radiation absorbed by the substrate 1.

1‧‧‧Semiconductor substrate

2‧‧‧Dielectric layer

3‧‧‧Thermal oxide layer

4‧‧‧Additional dielectric layer

5‧‧‧Dielectric layer

10‧‧‧ first surface

11‧‧‧ second surface

100‧‧‧First Semiconductor District

110‧‧‧second semiconductor area

E‧‧‧electrode

Claims (32)

A method of fabricating a solar cell, comprising the steps of: a) providing a semiconductor substrate (1) made of a material based on an n-type doped crystalline germanium, the substrate (1) comprising a first a surface (10) and a reverse second surface (11), a1) forming a first semiconductor region (100) intended to contact an electrode (E), the first semiconductor region (100) being Forming a boron atom in the substrate (1), wherein the method comprises the following steps: b) forming a dielectric layer (2) at the second surface (11) of the substrate (1), the dielectric The layer (2) comprises a phosphorus atom or an arsenic atom, and the dielectric layer (2) and the substrate (1) form a structure (1, 2), c) thermally annealing the structure (1, 2), Capable of: forming a second semiconductor region (110) that is expected to contact an electrode (E) from the dielectric layer (2) by the phosphorus or arsenic atoms Spreading to the second surface (11) of the substrate (1) and forming into the substrate (1), forming a cerium oxide at the first surface (10) of the substrate (1) Basic thermal oxide layer (3). The method of claim 1, wherein the step b) comprises a step b1) for forming an additional dielectric layer (4) on the dielectric layer (2), preferably a system Made of hydrogenated tantalum nitride; and thermal annealing is performed at step c) on the structure (1, 2, 4) comprising the additional dielectric layer (4). The method according to claim 1 or 2, wherein the annealing is performed in an oxidizing atmosphere in the step c), and the annealing preferably has an annealing temperature value falling within a range of 850 ° C to 950 ° C and Annealing duration length values falling within the range of 5 minutes to 1 hour. The method of claim 1 or 2, wherein the step c) comprises the step of: c1) performing a thermal annealing according to the first thermal budget, the first thermal budget being adapted to diffuse the phosphorus or arsenic atoms Forming the second semiconductor region (110), the first thermal budget preferably having an annealing temperature value falling within a range of 850 ° C to 950 ° C and an annealing duration falling within a range of 5 minutes to 1 hour a length of time value, c2) performing a thermal annealing according to a second thermal budget in an oxidizing environment, the second thermal budget being adapted to form the thermal oxide layer (3), the second thermal budget preferably having The annealing temperature value falling within the range of 700 ° C to 800 ° C and the annealing duration length value falling within the range of 5 minutes to 1 hour. The method according to any one of claims 1 to 4, wherein the dielectric layer (2) formed at the step b) is based on bismuth oxynitride SiO _x N _y , which is confirmed to be 0 x < y, a preferred system, is hydrogenated. The method according to claim 5, wherein the bismuth oxynitride SiO _x N _y at step b) and after step c) is confirmed to be 0 x 0.05. The method of claim 5 or 6, wherein the bismuth oxynitride SiO _x N _y at step b) and after step c) is confirmed to be 0.30 x 0.05. The method of any one of claims 1 to 4, wherein the dielectric layer (2) formed at step b) is based on tantalum carbide. The method according to any one of claims 5 to 7, wherein the atomic content of the phosphorus atom or the arsenic atom in the dielectric layer (2) formed at the step b) falls within the range of 1% to 10%. And; the atomic content of the phosphorus atom or the arsenic atom in the dielectric layer (2) after the step c) falls within the range of 1% to 10%, and preferably, falls at 1% Up to 5% range. The method according to any one of claims 1 to 9, wherein the thermal annealing performed at step c) is capable of thermally activating the boron atoms of the first semiconductor region (100) implanted at step a1). The method of any one of claims 1 to 9, wherein the step a) comprises a step a2) of thermally annealing the substrate (1) according to a thermal budget, the thermal budget being adapted for use Thermally activating the boron atoms of the first semiconductor region (100); step a2) is performed prior to step b), and thermal annealing performed at step a2) preferably has a temperature of from 1,000 ° C to 1,100 ° C Annealing temperature values in the range and annealing duration length values greater than 1 minute. A method of fabricating a solar cell, comprising the steps of: a) providing a semiconductor substrate (1) made of a p-type doped crystalline germanium-based material, the substrate (1) comprising a first a surface (10) and a reverse second surface (11), a1) forming a first semiconductor region (100) intended to contact an electrode (E), the first semiconductor region (100) being Forming a phosphorus atom or an arsenic atom in the substrate (1), wherein the method comprises the following steps: b) forming a dielectric layer (2) at the second surface (11) of the substrate (1), The dielectric layer (2) includes boron atoms, and the dielectric layer (2) and the substrate (1) form a structure (1, 2), and c) the structure (1, 2) is thermally annealed. Capable of: forming a second semiconductor region (110) that is expected to contact an electrode (E) that diffuses the boron atoms from the dielectric layer (2) to Forming the second surface (11) of the substrate (1) into the substrate (1), forming a cerium oxide-based heat at the first surface (10) of the substrate (1) Oxide layer (3). The method of claim 12, wherein the method comprises a step b1) for forming an additional dielectric layer (4) on the dielectric layer (2), preferably a system Hydrogenated tantalum nitride is produced; and, step b1) is preferably carried out after step c). The method of claim 12 or 13, wherein the annealing is performed in an oxidizing environment in step c); and the annealing preferably has an annealing temperature value falling within a range of 900 ° C to 950 ° C And an annealing duration length value falling within the range of 5 minutes to 1 hour. The method according to any one of claims 12 to 14, wherein the dielectric layer (2) formed at step b) is based on bismuth oxynitride SiO _x N _y , which is confirmed to be 0 y < x, a preferred system, is hydrogenated. The method according to claim 15 wherein the bismuth oxynitride SiO _x N _y after step c) is confirmed to be x 0.50, preferred system, 0.50 x 0.66. The method of claim 15 or 16, wherein the bismuth oxynitride SiO _x N _y at step b) and after step c) is confirmed to be 0 y<0.10, preferred system, 0 y<0.05. The method of any one of claims 12 to 14, wherein the dielectric layer (2) formed at step b) is based on tantalum carbide. The method according to any one of claims 15 to 17, wherein the atomic content of the boron atom in the dielectric layer (2) formed at the step b) falls within a range of 10% to 50%, Preferably, it falls within the range of 10% to 30%; and the atomic content of boron atoms in the dielectric layer (2) after step c) falls within the range of 1% to 10%, Preferably, it falls within the range of 3% to 8%. The method of any one of claims 1 to 19, wherein the first semiconductor The body region (100) is formed at the first surface (10) of the substrate (1) at step a). The method according to any one of claims 1 to 20, wherein the first semiconductor region (100) is formed at the second surface (11) of the substrate (1) at step a), Forming a first well; and the dielectric layer (2) formed at step b) is arranged such that the second semiconductor region (110) formed at step c) forms a first and the first The second well separated by the well. A solar cell obtainable by the method of any one of claims 1 to 21. A solar cell comprising: a substrate (1) made of a semiconductor material based on an n-type doped crystalline germanium, the substrate (1) comprising a first surface (10) and a second a reverse surface (11); a first semiconductor region and a second semiconductor region (100, 110) extending under the first surface (10) of the substrate (1) and under the second surface (11) of the substrate, respectively The first semiconductor region (100) includes boron atoms, the second semiconductor region (110) includes a phosphorus atom or an arsenic atom; and a dielectric material formed at the second surface (11) of the substrate (1) Forming the first layer (2), the dielectric material is based on bismuth oxynitride SiO _x N _y , which is confirmed to be 0 x<y, the dielectric material comprises a phosphorus atom or an arsenic atom and preferably comprises hydrogen; a thermal oxide layer (3) based on cerium oxide, which is formed on the substrate (1) At a surface (10). The patentable scope of application of the solar cell 23, wherein the silicon oxynitride SiO _x N _y confirmed 0 x 0.05. The solar cell according to claim 23 or 24, wherein the bismuth oxynitride SiO _x N _{y is} confirmed to be 0.30 x 0.05. The solar cell according to any one of claims 23 to 25, wherein an atomic content of a phosphorus atom or an arsenic atom in the dielectric layer falls within a range of from 1% to 10%; preferably, It falls within the range of 1% to 5%. A solar cell comprising: a substrate (1) made of a semiconductor material based on a p-type doped crystalline germanium, the substrate (1) comprising a first surface (10) and a reverse a second surface (11); - a first semiconductor region and a second semiconductor region (100, 110) extending under the first surface (10) of the substrate (1) and a second surface (11) of the substrate Bottom, the first semiconductor region (100) comprises a phosphorus atom or an arsenic atom, the second semiconductor region (110) comprises a boron atom; and a dielectric formed at the second surface (11) of the substrate (1) The first layer (2) formed by the material, the dielectric material is based on yttrium oxynitride SiO _x N _y , which is confirmed to be 0 y<x, the dielectric material comprises a boron atom and preferably comprises hydrogen; a cerium oxide-based thermal oxide layer (3) formed on the first surface of the substrate (1) ( 10). A solar cell according to claim 27, wherein the bismuth oxynitride SiO _x N _{y is} confirmed to be x 0.50, preferred system, 0.50 x 0.66. The solar cell according to claim 27 or 28, wherein the bismuth oxynitride SiO _x N _{y is} confirmed to be 0 y 0.10, preferred system, 0 y 0.05. The solar cell according to any one of claims 27 to 29, wherein an atomic content of boron atoms in the dielectric layer falls within a range of from 1% to 10%; preferably, it falls within 3 % to 8% range. The solar cell according to any one of claims 23 to 30, wherein the solar cell comprises a second layer (4) formed of a dielectric material formed on the first layer (2), the system and preferably, is formed on the thermal oxide layer (3), the second dielectric material-based layer (4) to silicon oxynitride SiO _x N _y basis, which proved to 0 Preferably, the dielectric material comprises hydrogen. The solar cell according to any one of claims 23 to 31, wherein the first layer (2) has a thickness falling within a range of 3 nm to 100 nm.