TW201936018A - Printed circuit board - Google Patents

Abstract

A printed circuit board includes: first substrate having first pad provided on one surface thereof; second substrate having second pad provided on one surface thereof disposed to be separated from the first substrate such that the first pad and the second pad face opposite to each other; third substrate interposed between the first substrate and the second substrate; and fourth substrate including insulating layer and a plurality of circuits inserted into the third substrate. The plurality of circuits insulated from one another by the insulating layer are formed in parallel in one direction connecting the first substrate and the second substrate in such a way that both ends of the plurality of circuits are oriented, respectively, toward the first substrate and the second substrate. Both ends of two or more adjacent circuits selected among the plurality of circuits are joined, respectively, with the first pad and the second pad.

Description

A printed circuit board

The invention relates to a printed circuit board.

Advances in digital technology and semiconductor technology, and the sharp rise in the use of various electronic devices have resulted in a wider range of applications for sophisticated and complex electronic devices. With the increasing integration of various components in electronic devices, printed circuit boards require larger areas to interconnect individual components (eg, active devices, passive devices). At the same time, the size of the battery becomes larger, and therefore the printed circuit board needs to be more efficiently placed and installed in the limited space of the electronic device.

The related technology is described in Korean Patent Publication No. 10-1324595 (registered date: October 28, 2013).

The present invention aims to provide a printed circuit board having a plurality of layers which can be efficiently interconnected in a vertical direction.

An aspect of the present invention provides a printed circuit board. The printed circuit board includes a first substrate, a first pad provided on one surface of the first substrate, and a second substrate provided with a second connection on one surface of the second substrate. Pad, and the second substrate is disposed to be separated from the first substrate such that the first pad and the second pad face each other; a third substrate is interposed between the first substrate and the second substrate; and Four substrates are inserted into the third substrate. The fourth substrate includes an insulating layer and a plurality of circuits, and the plurality of circuits are insulated from each other by the insulating layer and are formed in one direction in parallel so that the two ends of the plurality of circuits face the first substrate and the second substrate, respectively. Connect the first substrate and the second substrate in a directional manner. Two ends of two or more adjacent circuits selected from a plurality of circuits are respectively engaged with the first pad and the second pad.

The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, devices, and / or systems described herein. However, it will be apparent to those skilled in the art that various modifications, retouching, and equivalents of the methods, devices, and / or systems described herein will be apparent. The order of operations described in this article is only an example, and is not limited to the order of operations mentioned in this article, but as will be apparent to those having ordinary knowledge in the technology, except for operations that must occur in a particular order Other than that, it can be changed. In addition, in order to improve clarity and clarity, descriptions of functions and structures that are well known to those having ordinary knowledge in the art may be omitted.

Features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided so that this disclosure will be thorough and complete, and will convey the full scope of the invention to those skilled in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those with ordinary knowledge in the technology to which this invention belongs. Any term defined in a commonly used dictionary should be interpreted as having the same meaning as in the context of the related technology, and should not be interpreted as having an idealized or overly formal meaning unless it is clearly defined otherwise.

Regardless of the drawing number, the same or corresponding elements will be given the same reference numbers, and the same or corresponding elements will not be described again. Throughout the description of the present invention, when specific related conventional technologies are set out to be irrelevant to the viewpoint of the present invention, the detailed description will be omitted. Terms such as "first" and "second" can be used in explaining various elements, but the above elements should not be limited to the above terms. The above terms are only used to distinguish individual components. In the drawings, some elements may be exaggerated, omitted, or shown briefly, and the dimensions of the elements do not necessarily reflect the actual dimensions of the elements.

Hereinafter, specific embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 illustrates a printed circuit board according to an embodiment of the present invention. 2 and 3 illustrate a third substrate of a printed circuit board according to an embodiment of the present invention. 4 to 6 illustrate a fourth substrate of a printed circuit board according to an embodiment of the present invention. FIG. 7 illustrates a process of inserting a fourth substrate of a printed circuit board into a third substrate of the printed circuit board according to an embodiment of the present invention.

1, a printed circuit board according to an embodiment of the present invention includes a first substrate, a second substrate, a third substrate, and a fourth substrate. The first substrate and the second substrate are arranged above and below each other and spaced apart, the third substrate is sandwiched between the first substrate and the second substrate, and the fourth substrate is inserted into the third substrate. In the following, the configuration and coupling relationship of these substrates will be explained.

Each of the first substrate 100 and the second substrate 200 may be a main board installed in an electronic device such as a mobile phone. The first substrate 100 and the second substrate 200 may be spaced apart from each other above and below to form a multilayer stacked sandwich structure. Specifically, the first substrate 100 and the second substrate 200 are arranged to be spaced apart from each other such that one surface 110 of the first substrate 100 and one surface 210 of the second substrate 200 face each other.

The first substrate 100 and the second substrate 200 may each be formed in a plate shape, each may be a multilayer substrate composed of a plurality of insulating material layers and a plurality of circuit layers, and each may include eight circuit layers or 10 circuit layers. Multilayer substrate.

The insulating material layer of the first substrate 100 and the insulating material layer of the second substrate 200 are made of, for example, epoxy resin, polyimide resin, bismaleimide triazine (BT) resin or liquid crystal polymer ( Liquid Crystal Polymer (LCP) and other insulating materials. The circuit layer is made of a conductive material such as a metal (eg, copper) and is designed to have a specific pattern. The circuit layer is formed on one or both surfaces of the insulating material layer, and the circuit layers on different layers can be electrically interconnected by a connecting conductor penetrating the insulating material layer.

A first electronic component E1 is mounted on one surface 110 of the first substrate 100. Here, the first electronic component E1 may include, but is not limited to, an active device, a passive device, or an integrated circuit. In addition, a third electronic component E3 may be mounted on the other surface 120 of the first substrate 100.

A first pad 130 is provided on one surface 110 of the first substrate 100. The first pad 130 can be electrically connected to the first electronic component E1 and the circuit layer.

The first pad 130 may be a part of a circuit layer located on an outermost layer on one surface side of the first substrate 100. Specifically, the first pad 130 is formed on the outermost insulating material layer of the first substrate 100, may be a part of the circuit layer covered by the solder resist 330, and may be exposed through the opening 331 of the solder resist 330.

A plurality of first pads 130 may be formed and may be arranged at a boundary of one surface 110 of the first substrate 100.

A second electronic component E2 is mounted on one surface 210 of the second substrate 200. Here, the second element D3 may include, but is not limited to, an active device, a passive device, or an integrated circuit.

In addition, a second pad 230 is provided on one surface 210 of the second substrate 200. The second pad 230 can be electrically connected to the second electronic device E2 and the circuit layer.

The second pad 230 may be a part of a circuit layer located on an outermost layer on one surface side of the second substrate 200. Specifically, the second pad 230 is formed on the outermost insulating material layer of the second substrate 200, may be a part of a circuit layer covered with the solder resist 330, and may be exposed through the opening 331 of the solder resist 330.

A plurality of second pads 230 may be formed and may be arranged at a boundary of one surface 210 of the second substrate 200.

One surface 110 of the first substrate 100 and one surface 210 of the second substrate 200 face each other, and the first pad 130 and the second pad 230 face each other. Here, the position of the first pad 130 corresponds to the position of the second pad 230. Specifically, a line connecting the first pad 130 to the second pad 230 (and vice versa) may be perpendicular to the first substrate 100 and the second substrate 200. The first pads 130 and the second pads 230 may each be formed in a plurality, and the plurality of first pads 130 and the plurality of second pads 230 may be respectively formed to correspond to each other.

The third substrate 300 is interposed between the first substrate 100 and the second substrate 200. That is, the third substrate 300 is coupled to one surface 110 of the first substrate 100 and one surface 210 of the second substrate 200. The space between the first substrate 100 and the second substrate 200 can be obtained by the third substrate 300. maintain.

The first electronic component E1 and the second electronic component E2 are housed in a space provided by the third substrate 300 between the first substrate 100 and the second substrate 200. That is, the first electronic component E1 mounted on the first substrate 100 and the second electronic component E2 mounted on the second substrate 200 are accommodated in a space surrounded by the third substrate 300, and the tops of these electronic components are The surfaces face each other.

The third substrate 300 may be located at a boundary between the first substrate 100 and the second substrate 200. The width of the third substrate 300 may be 1 millimeter (mm) to 2 millimeters.

Referring to FIG. 2, the third substrate 300 may include a plurality of separate sheet substrates, and the plurality of separate sheet substrates may be arranged along a boundary between the first substrate 100 and the second substrate 200. The electronic components are placed in a space surrounded by a plurality of separate sheet substrates.

Referring to FIG. 3, the third substrate 300 includes a base substrate, a cavity C, and a solder resist 330, and a fourth substrate 400 is housed in the cavity C. Meanwhile, the third substrate 300 may further include a surface treatment layer 340.

The base substrate includes an insulating material 310 and metal layers 320 laminated on both surfaces of the insulating material 310. The base substrate may be a copper clad laminate (CCL). That is, the insulating material 310 may be a prepreg (PPPG) having a resin such as epoxy resin immersed in a reinforcing substrate, and the metal layer 320 may be a copper (Cu) foil. The metal layer 320 provides rigidity to the third substrate 300. Meanwhile, when the third substrate 300 is sandwiched between the first substrate 100 and the second substrate 200, one surface of the base substrate faces the first substrate 100, and the other surface of the base substrate faces the second substrate 200. Specifically, the metal layers 320 formed on one surface and the other surface of the base substrate face the first substrate 100 and the second substrate 200, respectively.

The base substrate is formed with a cavity C, and the cavity C penetrates the base substrate in a thickness direction. That is, the cavity C penetrates the base substrate from one surface of the base substrate facing the first substrate 100 to the other surface of the base substrate facing the second substrate 200. The cavity C can be machined by a laser drill, a CNC drill, or the like. The cavity C houses the fourth substrate 400. That is, the third substrate 300 is used to support the fourth substrate 400. Therefore, although the third substrate 300 has the metal layer 320 included in the copper-clad laminate, the metal layer 320 is not necessarily formed as a pattern of the separate circuit 420, and the circuit 420 of the fourth substrate 400 and the third substrate 300 The metal layers 320 are not electrically connected to each other, but are separated from each other and insulated from each other.

The fourth substrate 400 is inserted into the cavity C of the third substrate 300 and includes an insulating layer 410 and a plurality of circuits 420.

The insulating layer 410 is a plate-shaped layer made of an insulating material, such as, but not limited to, an epoxy resin, a polyimide resin, or a bismaleimide triazine (BT) resin.

Referring to FIG. 4, a plurality of circuits 420 are formed on a surface of the insulating layer 410, are formed in “one direction” in parallel, and are insulated from each other by the insulating layer 410. The circuit 420 is configured to electrically interconnect the first substrate 100 and the second substrate 200. Therefore, the “one direction” in which the plurality of circuits 420 are formed in parallel is a direction connecting the first substrate 100 and the second substrate 200 and may include any direction sufficient to connect the first substrate 100 and the second substrate 200. In a case where the first substrate 100 and the second substrate 200 are arranged in a vertical direction (ie, the z-axis), the plurality of circuits 420 are also each formed to extend in the vertical direction (ie, the z-axis). That is, the ends of each of the plurality of circuits 420 are respectively oriented toward the first substrate 100 and the second substrate 200. Nevertheless, the plurality of circuits 420 need not necessarily be parallel to the z-axis and may be diagonally opposite to the z-axis.

At the same time, both end portions of the plurality of circuits 420 are exposed through a side surface of the fourth substrate 400. In order to make both ends of the plurality of circuits 420 face the first substrate 100 and the second substrate 200, after the fourth substrate 400 is manufactured, the fourth substrate 400 is rotated 90 degrees (that is, rotated about the x-axis or the y-axis) and It is then inserted into the third substrate 300.

Both ends of the plurality of circuits 420 are also exposed through the third substrate 300 and are bonded to the first pads 130 of the first substrate 100 and the second pads 230 of the second substrate 200. Specifically, for two or more circuits 420 selected from a plurality of circuits 420, two ends of the two or more selected circuits 420 are respectively connected to the first pad 130 and the second pad 230. Bonded, and thus a single first pad 130 (or second pad 230) is bonded with two or more circuits 420.

Since the multiple circuits 420 have the same shape, even when the fourth substrate 400 is inserted into the third substrate 300, the fourth substrate 400 is misaligned (relative to the designed insertion placement position) or the first connection when the fourth substrate 400 is inserted. The pad 130 (or the second pad 230) is misaligned (relative to the designed pad placement position), and the first pad 130 (or the second pad 230) will still eventually reach any two of the multiple circuits 420 Or more.

To enhance the possibility of alignment, the side cross-sectional area of each of the first pad 130 and the second pad 230 may be larger than the side cross-sectional area of the circuit 420 (a rectangular area in FIG. 3 (a) ). Here, the circuits 420 may be as close to each other as possible. For example, the width of the circuits 420 (that is, the width of one rectangle in (a) of FIG. 3) may be larger than the gap between the circuits 420 formed on the surface of the insulating layer 410.

The width of the circuit 420 may be between 1 micrometer (um) and 1,000 micrometers. However, depending on the intended use of the circuit 420, the plurality of circuits 420 may have different widths from each other. The use of the circuit 420 may include transmitting an effective electrical signal, transmitting a ground signal, and the like, and the circuit 420 intended for transmitting an effective electrical signal may have a relatively small width.

As shown in FIGS. 4 to 6, the insulating layer 410 may be composed of a plurality of insulating layers 410 laminated one by one, and a plurality of circuits 420 may be formed on a surface of each insulating layer 410. Therefore, the plurality of circuits 420 are also laminated with the insulating layer 410 in the vertical direction (ie, the z-axis). In this case, the fourth substrate 400 is configured to have an insulating layer 410 and a circuit layer (which is a collection of a plurality of circuits 420 formed on a coplanar surface of the insulating layer 410) staggeredly laminated. However, the circuit 420 may not be formed on the surface of the outermost insulating layer 410.

As in FIG. 1, in the final printed circuit board in which the fourth substrate 400 is inserted into the third substrate 300, the lamination direction of the plurality of insulating layers 410 of the fourth substrate 400 is the same as that of the first substrate 100 (and the second substrate). 200) The lamination directions of the insulating material layers may be perpendicular to each other. This is because the fourth substrate 400 is rotated 90 degrees before being inserted into the third substrate 300. For example, if the insulating material layers of the first substrate 100 (and the second substrate 200) are laminated in the z-axis direction, the insulating layer 410 of the fourth substrate 400 is laminated in the x-axis or y-axis direction.

Referring to FIG. 4, the insulating layer 410 includes a first insulating layer 411 and a plurality of second insulating layers 412 sequentially laminated on any surface of the first insulating layer 411. In addition, a plurality of circuits 420 are formed on both surfaces of the first insulating layer 411 and on a surface of the plurality of second insulating layers 412. Since the third insulating layer 410 is laminated on the outermost layer, the circuit 420 may not be exposed.

Referring to (a) in FIG. 4, a double-sided copper-clad laminate is prepared, and a circuit 420 is formed on both surfaces of the first insulating layer 411 using copper foil. Referring to (b) in FIG. 4, a single-sided copper-clad laminate is laminated on both surfaces of the double-sided copper-clad laminate, and the insulating material 310 of the single-sided copper-clad laminate is referred to as a second insulating layer 412 to It is distinguished from the first insulating layer 411.

Nonetheless, the first insulating layer 411 and the second insulating layer 412 may be made of the same material, and the boundary line (ie, the interface) between the first insulating layer 411 and the second insulating layer 412 may be made in the final manufactured first. The four substrates 400 disappear.

Referring to (c) in FIG. 4, the circuit 420 is again formed using a copper foil of a single-sided copper-clad laminate. By repeatedly performing steps (b) and (c), a plurality of second insulating layers 412 are formed on the first insulating layer 411, and a circuit 420 is formed in each of the second insulating layers 412. Once the third insulating layer 410 is laminated on the outermost layer, a fourth substrate 400 as shown in (d) of FIG. 4 can be produced. The third insulating layer 410 may also be made of the same material as the first insulating layer 411 and the second insulating layer 412, but the term "third" is only used to distinguish the insulating layers. Of course, the third insulating layer 410 may be made of a material different from that of the first insulating layer 411 and / or the second insulating layer 412.

As shown in (d) of FIG. 4, both end portions of the plurality of circuits 420 are exposed through the side surface of the fourth substrate 400, and referring to (e) of FIG. 4, the fourth substrate 400 is inserted into the third substrate 400. The substrate 300 is rotated 90 degrees (that is, around the x-axis or the y-axis), and both ends of the plurality of circuits 420 face the first substrate 100 and the second substrate 400 in the fourth substrate 400 inserted into the third substrate 300. The substrates 200 are respectively oriented.

Meanwhile, as shown in FIG. 5, the circuits 420 formed in the different second insulating layers 412 may not overlap each other in the vertical direction. That is, the circuits 420 formed in any one of the second insulating layers 412 may be formed at corresponding spaces between the circuits 420 formed in each of the adjacent second insulating layers 412. In this case, the possibility of alignment can be increased.

As shown in FIG. 6, the insulation layer 410 may include a plurality of first insulation layers 411 and a plurality of second insulation layers 412 sandwiched between the plurality of first insulation layers 411, respectively, and the circuit 420 may be formed in a plurality of On either surface of the first insulating layer 411. However, the circuit 420 may be formed on only one surface of the outermost first insulating layer 411. Alternatively, a third insulating layer 410 (not shown) may be formed on the outermost first insulating layer 411.

Referring to (b) in FIG. 6, a circuit may be first formed on any surface of the first insulating layer 411 by using a double-sided copper-clad laminate. Nevertheless, as shown in (a) and (c) of FIG. 6, a circuit 420 is formed on one surface of each of the outermost first insulating layers 411 using a single-sided copper-clad laminate. While repeating step (b) of FIG. 6 up to 100 times to arrange the plurality of first insulating layers 411 one by one, the second insulating layer 412 is sandwiched between the plurality of first insulating layers 411, respectively. Then, the first insulating layer 411 and the second insulating layer are integrally laminated together (shown in (d) and (e) of FIG. 6).

Nonetheless, the first insulating layer 411 and the second insulating layer 412 may be made of the same material, and the boundary line (ie, the interface) between the first insulating layer 411 and the second insulating layer 412 may be made in the final manufactured first. The four substrates 400 disappear.

As shown in (e) of FIG. 6, both ends of the plurality of circuits 420 are exposed through the side surface of the fourth substrate 400, and referring to (f) of FIG. 6, the fourth substrate 400 is inserted into the third The substrate 300 is rotated 90 degrees (that is, around the x-axis or the y-axis), and both ends of the plurality of circuits 420 face the first substrate 100 and the second substrate 400 in the fourth substrate 400 inserted into the third substrate 300 The substrates 200 are respectively oriented.

FIG. 7 illustrates a process of inserting the fourth substrate 400 into the third substrate 300.

Referring to (a) in FIG. 7, as above, a double-sided copper-clad laminate is prepared as a base substrate, and as shown in (b) of FIG. 7, the cavity C is machined. Here, since the cavity C completely penetrates the base substrate in the thickness direction, an adhesive tape for temporarily securing the fourth substrate is bonded to the lower surface of the base substrate after the cavity C is machined. Referring to (c) in FIG. 7, the fourth substrate 400 is inserted into the cavity C of the third substrate 300, and the fourth substrate 400 is rotated 90 degrees before the fourth substrate 400 is inserted as described above. Therefore, both ends of the plurality of circuits 420 of the fourth substrate are respectively oriented toward both surfaces of the base substrate of the third substrate 300 (or copper foil on either surface of the double-sided copper-clad laminate).

Referring to (d) in FIG. 7, a solder resist 330 is formed on a base substrate. That is, the solder resist 330 is provided on the outermost layer of the third substrate 300. Specifically, in a case where the cavity C is larger than the fourth substrate 400, a region other than the fourth substrate 400 in the cavity C is filled with the solder resist 330 to fasten the fourth substrate 400. Since it may be difficult to form the cavity C to the exact size of the fourth substrate 400, the cavity C is made larger than the fourth substrate 400, and then after the fourth substrate 400 is inserted, the cavity C is filled with a resistor. The solder 330 is used to fix the fourth substrate 400 in place. At the same time, the solder resist 330 is formed inside the cavity C and on the upper surface of the base substrate due to the adhesive tape attached after the cavity C is machined, and as shown in FIG. 7 (e), the solder resist 330 Also formed on the lower surface of the base substrate, the solder resist 330 covers each surface of the fourth substrate 400. In this way, the fourth substrate 400 can be more firmly fixed in the third substrate 300.

Referring to (f) in FIG. 7, an opening 331 is formed in the solder resist 330. The opening 331 exposes an end portion of the circuit 420 exposed through the side surface of the fourth substrate 400 (ie, the side surface before being rotated 90 degrees). That is, the end of the circuit 420 is exposed through the bottom of the opening 331 of the solder resist 330. The exposed ends of the circuit 420 are bonded to the first pads 130 of the first substrate 100 and the second pads 230 of the second substrate 200 by solder S. In this case, solder S may be formed in the opening 331 (see FIG. 1) of the solder resist 330 between the pad and the end of the circuit 420. That is, the solder resist 330 enables the solder S to be stably located between the pad and the circuit 420 and enhances the bonding reliability between the pad and the circuit 420.

Meanwhile, in a case where the solder resist 330 is photosensitive, the openings 331 may be formed by a photolithography process, and a plurality of the openings 331 may be formed and spaced apart from each other.

Referring to (g) in FIG. 7, a surface treatment layer 340 may be formed at an end portion of the circuit 420 exposed through the opening 331 of the solder resist 330. The surface treatment layer 340 may be made of a metal such as gold (Au) or nickel (Ni) or may be provided with a double layer composed of gold (Au) and nickel (Ni). The surface treatment layer 340 can prevent the ends of the circuit 420 from being corroded.

Once the surface treatment layer 340 is formed, the solder S is accommodated on the surface treatment layer 340, and the surface treatment layer 340 and the first pad 130 or the second pad 230 can be joined by the solder S.

FIG. 8 illustrates a third substrate 300 of a printed circuit board according to an embodiment of the present invention. 9 to 13 illustrate a method of manufacturing the third substrate 300 illustrated in FIG. 8, and FIGS. 14 to 18 illustrate another method of manufacturing the third substrate 300 illustrated in FIG. 8.

Referring to FIG. 8, the third substrate 300 may have a ring shape. Here, the ring shape means a shape in which the internal space is not filled. Corresponding to the shape of the third substrate 300, the first pads 130 and the second pads 230 may be located at the boundary of one surface 110 of the first substrate 100 and the boundary of one surface 210 of the second substrate 200, respectively. However, in the case where the third substrate 300 has a ring shape, the first electronic component E1 and the second electronic component E2 may be accommodated in an unfilled internal space. That is, the first electronic component E1 mounted on one surface 110 of the first substrate 100 and the second electronic component E2 mounted on one surface 210 of the second substrate 200 are accommodated in the internal space of the third substrate 300 and Surrounded by the third substrate 300.

Meanwhile, the fourth substrate 400 is formed of a separate piece substrate, and a cavity C corresponding to each piece of substrate is formed in the third substrate 300, and the fourth substrate 400 in the form of a separate piece substrate can be inserted In each cavity C. Alternatively, the fourth substrate 400 may have a ring shape corresponding to the third substrate 300. The former is shown in FIG. 9 and the latter is shown in FIG. 10.

Referring to FIGS. 9 to 13, a substrate made of a copper-clad laminate is prepared, and a space A is provided by removing some parts inside the base substrate. A plurality of cavities C are formed in a ring formed by the remaining base substrate. The plurality of cavities C can be arranged in various ways and can be freely arranged along the ring shape of the base substrate. Furthermore, there can be any number of cavities C. There is a base substrate that does not become the cavity C between the cavities C.

While the fourth substrate 400 is inserted into the cavity C, a separate sheet substrate is inserted into each cavity C. After the fourth substrate 400 is inserted into the cavity C, a solder resist 330 is formed in a space inside the cavity C and on the upper surface of the base substrate and on the lower surface of the base substrate. Once the opening 331 is formed in the solder resist 330, the circuit 420 of the fourth substrate 400 is exposed through the opening 331. In addition, a surface treatment layer (340 in FIG. 7; not shown in FIGS. 8 to 18) may be formed on the lower surface of the opening 331.

14 to 18, a base substrate composed of a copper-clad laminate is prepared, and a space A is provided by removing some parts inside the base substrate. A ring-shaped cavity C is formed in a ring formed by the remaining base substrate. The ring shape of the cavity C corresponds to the ring shape of the base substrate. Here, the adhesive tape may be attached to the lower surface of the base substrate so that the annular inner portion of the base substrate does not separate. As described above, the adhesive tape may be used to temporarily fasten the fourth substrate 400.

A fourth substrate 400 having a ring shape may be inserted into the cavity C. The ring shape of the fourth substrate 400 can be made by machining a ring shape in the fourth substrate 400 manufactured by FIGS. 4 to 6. After the fourth substrate 400 is inserted into the cavity C, a solder resist 330 is formed in the space in the cavity C and on the upper surface of the base substrate and on the lower surface of the base substrate. Once the opening 331 is formed in the solder resist 330, the circuit 420 of the fourth substrate 400 is exposed through the opening 331. In addition, a surface treatment layer (340 in FIG. 7; not shown in FIGS. 8 to 18) may be formed on the lower surface of the opening 331.

In the present invention, although the multilayer stacked sandwich structure composed of the first substrate 100 and the second substrate 200 is maintained by the third substrate 300 sandwiched between the first substrate 100 and the second substrate 200, the first The electrical connection between a substrate 100 and the second substrate 200 is achieved by a fourth substrate 400 inserted into the third substrate 300.

Specifically, both ends of the plurality of circuits 420 formed in the fourth substrate 400 are exposed through two surfaces of the fourth substrate 400 that are respectively oriented toward the first substrate 100 and the second substrate 200 and also pass through the third surface. The substrate 300 is exposed, and thus two ends of two or more adjacent circuits 420 selected from the plurality of circuits 420 and the first pad 130 of the first substrate 100 and the second of the second substrate 200 are selected. The pads 230 are respectively joined. The plurality of circuits 420 enhance the possibility of alignment between the fourth substrate 400 and the first pad 130 (or the second pad 230).

The pad and the circuit 420 may be bonded by the solder S. In this case, while the solder resist 330 formed in the third substrate 300 fastens the fourth substrate 400, the bonding reliability is enhanced by accommodating the solder S in the opening 331 of the solder resist 330.

Although the present invention includes specific examples, it will be apparent to those having ordinary knowledge in the art that various forms may be made in these examples without departing from the spirit and scope of the scope of the patent application and its equivalent range. And changes in details. The examples described herein are to be regarded as illustrative only and not limiting. The description of features or aspects in each instance should be considered as applicable to similar features or aspects in other instances. If the techniques are performed in a different order and / or if the components in the system, architecture, device or circuit are combined in different ways and / or replaced or supplemented by other components or their equivalents, Achieve the right results. Therefore, the scope of the present invention is not defined by the detailed description, but is defined by the scope of the patent application and its equivalent scope, and all changes within the scope of the scope of the patent application and its equivalent scope should be considered to be included in the invention in.

100‧‧‧first substrate

110, 210‧‧‧ one surface

120‧‧‧ another surface

130‧‧‧The first pad

200‧‧‧ second substrate

230‧‧‧Second pad

300‧‧‧ Third substrate

310‧‧‧Insulation material

320‧‧‧ metal layer

330‧‧‧solder resist

331‧‧‧ opening

340‧‧‧Surface treatment layer

400‧‧‧ Fourth substrate

410‧‧‧Insulation layer / Third insulation layer

411‧‧‧first insulating layer

412‧‧‧Second insulation layer

420‧‧‧circuit

A‧‧‧space

C‧‧‧ Cavity

E1‧‧‧The first electronic component

E2‧‧‧Second electronic component

E3‧‧‧Third Electronic Component

FIG. 1 illustrates a printed circuit board according to an embodiment of the present invention. 2 and 3 illustrate a third substrate of a printed circuit board according to an embodiment of the present invention. 4 to 6 illustrate a fourth substrate of a printed circuit board according to an embodiment of the present invention. 7 illustrates a process of inserting a fourth substrate of a printed circuit board into a third substrate of the printed circuit board according to an embodiment of the present invention. FIG. 8 illustrates a third substrate of a printed circuit board according to an embodiment of the present invention. 9 to 13 illustrate a method of manufacturing the third substrate shown in FIG. 8. 14 to 18 illustrate another method of manufacturing the third substrate shown in FIG. 8.

Claims (17)

A printed circuit board includes: a first substrate provided with a first pad on one surface of the first substrate; a second substrate provided with a second pad on one surface of the second substrate; and A second substrate is disposed to be separated from the first substrate so that the first pad and the second pad face each other; a third substrate is sandwiched between the first substrate and the first substrate Between two substrates; and a fourth substrate inserted into the third substrate, wherein the fourth substrate includes an insulating layer and a plurality of circuits, wherein the plurality of circuits are insulated from each other by the insulating layer, and It is formed in parallel to one direction connecting the first substrate and the second substrate, and is further formed so that both ends of the plurality of circuits are oriented toward the first substrate and the second substrate, respectively. And two end portions of two or more adjacent circuits selected from the plurality of circuits are respectively engaged with the first pad and the second pad. The printed circuit board according to item 1 of the patent application scope, wherein the third substrate includes a solder resist on an outermost layer of the third substrate, wherein the solder resist covers a surface of the fourth substrate, and wherein The solder resist is formed with an opening to expose the two end portions of the two or more adjacent circuits selected from the plurality of circuits. The printed circuit board according to item 2 of the scope of patent application, wherein the two ends of the two or more adjacent circuits selected from the plurality of circuits are formed in the openings. Solder which is bonded to the first pad and the second pad. The printed circuit board according to item 2 of the scope of patent application, wherein the two end portions of the two or more adjacent circuits selected from the plurality of circuits exposed through the opening are exposed. A surface treatment layer is formed thereon. The printed circuit board according to item 2 of the patent application scope, wherein the openings are formed in a plurality and spaced apart from each other. The printed circuit board according to item 1 of the scope of patent application, wherein the insulating layer of the fourth substrate includes a plurality of first insulating layers and a second insulating layer sandwiched between the plurality of insulating layers, And wherein the plurality of circuits are formed on two surfaces of each of the plurality of the first insulating layers. The printed circuit board according to item 1 of the scope of patent application, wherein the insulating layer of the fourth substrate includes a first insulating layer and a plurality of layers sequentially laminated on both surfaces of the first insulating layer. A second insulating layer, and wherein the plurality of circuits are formed on the two surfaces of the first insulating layer and on the surfaces of the plurality of second insulating layers. The printed circuit board according to claim 6 or claim 7, wherein the first substrate and the second substrate are each a multilayer substrate in which a plurality of insulating material layers are laminated, and wherein The laminating direction of the insulating material layer of the first substrate and the insulating material layer of the second substrate is perpendicular to the laminating direction of the first insulating layer and the second insulating layer of the fourth substrate. . The printed circuit board according to item 1 of the scope of patent application, wherein the third substrate comprises: an insulating material; and a metal layer laminated on any surface of the insulating material, wherein the insulating material and the A cavity is formed in the metal layer to penetrate the insulating material and the metal layer, and the fourth substrate is inserted into the cavity. The printed circuit board according to item 9 of the scope of patent application, wherein the metal layer of the third substrate and the circuit of the fourth substrate are electrically insulated from each other. The printed circuit board according to item 9 of the scope of patent application, wherein a space other than the fourth substrate in the cavity is filled with a solder resist. The printed circuit board according to item 1 of the scope of patent application, wherein the first pad is located at a boundary on the one surface of the first substrate, and the second pad is located on the second substrate At the boundary on the one surface, the third substrate has a ring shape corresponding to the first pad and the second pad, and a space is provided in the third substrate. The printed circuit board according to item 12 of the application, wherein a first electronic component is mounted on the one surface of the first substrate, and a second electronic component is mounted on the one surface of the second substrate. Component, and wherein the first electronic component and the second electronic component are accommodated in the space. The printed circuit board according to item 13 of the scope of patent application, wherein a third electronic component is mounted on the other surface of the first substrate. The printed circuit board according to item 12 of the scope of patent application, wherein the fourth substrate has a ring shape corresponding to the third substrate. The printed circuit board according to item 9 of the scope of patent application, wherein the fourth substrate is composed of a plurality of sheet substrates separated from each other, and wherein the cavity is formed with a plurality of and separated from the cavity. The opened multiple sheet substrates correspond. The printed circuit board according to item 1 of the scope of patent application, wherein the third substrate is composed of a plurality of separated sheet substrates, and wherein the plurality of separated sheet substrates are in the first A boundary between a substrate and the second substrate is arranged along the periphery.