TW201937330A - Low dropout regulator and system thereof - Google Patents

Abstract

A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output of the low dropout regulator and a reference signal to produce a comparison result; a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result; an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.

Description

Low dropout voltage regulator and system

The present invention relates to the technical field of circuits, and in particular, to a dropout voltage regulator and a system thereof.

Low-dropout regulators are used in integrated circuits as a way to regulate the output voltage. Low-dropout regulators are often designed to produce stable output voltages even when the output voltage is close to the supply voltage.

The invention provides a low-dropout voltage regulator and a system including the low-dropout voltage regulator, which can quickly adjust the output of the low-dropout voltage regulator in real time according to changes in the output of the low-dropout voltage regulator.

An output-generating low-dropout voltage regulator provided by an embodiment of the present invention may include: a comparison circuit configured to compare a signal representing a output of the low-dropout voltage regulator with a reference signal to generate a comparison result; a loop controller, coupled To the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result; and the output circuit, including two or more switch circuits, configured to adjust based on the output circuit control signal The number of switching circuits that are turned on among the two or more switching circuits.

A system provided by an embodiment of the present invention may include: a load circuit including a plurality of sub-circuits; a first low-dropout voltage regulator coupled to a first end of the load circuit and configured to convert the first low-dropout voltage A first output of a voltage regulator is provided to the first end of the load circuit; and a second low-dropout voltage regulator, coupled to a second end of the load circuit, is configured to connect the second low-dropout voltage A second output of the voltage regulator is provided to the second end of the load circuit; wherein the first low dropout voltage regulator is configured to send an electric voltage indicating the first output to the second low dropout voltage regulator. A first indication of a flat change; wherein the first low-dropout voltage regulator is the low-dropout voltage regulator according to the embodiments of the present invention.

As described above, the low-dropout voltage regulator and system provided by the embodiments of the present invention can compare a signal representing a output of the low-dropout voltage regulator and a reference signal through a comparison circuit to generate a comparison result, and based on the The comparison result generates an output circuit control signal to adjust the number of switched circuits in the output circuit of the low-dropout voltage regulator. Therefore, the low-dropout voltage regulator and system of the embodiment of the present invention can quickly The change adjusts the output of the low-dropout voltage regulator immediately. Furthermore, when the low-dropout voltage regulator is connected to the load circuit, the embodiment of the present invention can quickly adapt to the change of the load circuit impedance to adjust the output of the low-dropout voltage regulator.

Integrated Low Dropout (ILDO) voltage regulators can be an important part of many integrated circuit solutions. Ideally, an ILDO regulator can provide a controlled output voltage level that is close to the power supply voltage level while maintaining low ripple and noise. The ILDO regulator can adjust its output according to the change of the impedance of the load circuit coupled to its output, so that a constant or near constant power, voltage or current is provided at the output. However, typical ILDO regulators need to notify the load condition in advance, indicating that the load impedance will change at a specific point in time to provide proper output regulation. When the load circuit needs to quickly adjust the current, voltage, or power provided by the ILDO regulator, an ILDO regulator with a notification system in advance may not provide adequate control. In addition, if the advance notification signal is lost or delayed, the ILDO regulator may not be able to provide the correct output voltage, current, or power level, and the load circuit may receive insufficient voltage, current, or power level, or be too high. A typical ILDO regulator is usually synchronized to one clock cycle, which may introduce unnecessary delays when changing the output voltage or current provided because the ILDO regulator adjusts its output voltage, current or power level before You may have to wait for a clock edge. The present invention describes an ILDO regulator with a non-synchronous control system, which can quickly adjust the output of the low-dropout regulator according to changes in the output of the low-dropout regulator (for example, changes in the impedance of the load circuit).

Before discussing the control system of the present invention, the existence of parasitics in circuits related to the ILDO regulator will be discussed. FIG. 1 illustrates a circuit board 100 including a package component 110 and a package external component 140. The package component 110 may include an integrated low dropout (ILDO) voltage regulator 120 coupled to the load circuit 130. The ILDO regulator 120 may provide its output to the load circuit 130. The package external component 140 may have a parasitic inductance, a parasitic capacitance and / or a parasitic resistance and an external power management integrated circuit (PMIC). For example, an out-of-package inductor may have parasitic capacitance between the winding turns of the inductor. In another example, an out-of-package capacitor may have parasitic resistance at various frequencies. In addition, the coupling between the packaged component 110 and the package and non-packaged components can have parasitic inductance, parasitic capacitance, and / or parasitic resistance through similar mechanisms. Any or all of the parasitic effects described herein may vary over time. In addition, the impedance of the load circuit 130 may change with time. For example, if the load circuit 130 is coupled to another circuit, the reflected impedance from the coupling may change over time, thereby changing the impedance of the load circuit 130 as seen by the ILDO regulator 120. In another example, the impedance 130 of the load circuit may change due to time-varying parasitic effects within the load circuit 130. In some embodiments, the ILDO regulator 120 may be designed to provide changes in power, voltage, or current output and load impedance to the load circuit 130 in a manner that mitigates parasitic effects. It should be understood that the outer package component 140 shown in FIG. 1 is merely an example, and in some embodiments, the outer package component may not be used. In some embodiments, with the exception of the ILDO regulator 120 and the load circuit 130, no on-chip packaged components are used.

The load circuit 130 may be any circuit that receives power, current, or voltage from the ILDO regulator 120. The impedance of the load circuit 130 may change over time due to a number of factors, such as changes in the size of the load or changes in parasitics. Therefore, as will be described in further detail below, in some embodiments, the ILDO regulator 120 can adapt to impedance changes of the load circuit and parasitic effects of the package component 110 and the package external component 140.

FIG. 2A illustrates an embodiment of the ILDO regulator 200. The ILDO regulator 200 may include a control circuit 260 and a switching circuit 250. The control circuit 260 may receive the feedback signal VFB and the reference signal VREF1 at the comparator 210. VFB may be a signal indicating a voltage level at the output of the ILDO regulator 200 (ie, VFB may reflect a change in the impedance of the load circuit). For example, in some embodiments, VFB may be the output voltage of the ILDO regulator 200. In other embodiments, VFB may be a proportional representation of the output voltage of the ILDO regulator 200. In other embodiments, the feedback signal provided to the comparator 210 may represent the current or power provided to the load circuit. VREF1 can be a reference voltage, which can be preset in the memory of the system, set by the user of the system, or established by any suitable method. In other embodiments, the reference signal may be a reference current or power. The comparator 210 may compare the feedback signal and the reference signal and output a COMP signal indicating a state change between the two signals. For example, if VFB is initially lower than VREF1 and then becomes higher than VREF1, the comparator 210 may generate a first COMP signal indicating a change in VFB state. Alternatively, if VFB is initially higher than VREF1 and then becomes lower than VREF1, the comparator 210 may generate a second COMP signal indicating a change in the state of the VFB that is different from the first COMP signal. For example, the first COMP signal may be a pulse having a first shape, a first duration and / or a first amplitude, and the second COMP signal may be a pulse having a second shape, a second duration and / or a second amplitude . In some embodiments, the first COMP signal and the second COMP signal may be different and may change in different states of VFB relative to VREF1 (eg, VFB drops below VREF1 or VFB rises above VREF1). Although voltage comparison is used as an example here, it should be understood that the comparison object in the specific implementation may be current or power. A change in the level of VFB relative to VREF1 (for example, VFB drops below VREF1 or VFB rises above VREF1) can be used to determine the change in the level of the output voltage provided by the ILDO regulator 200 to the load circuit. Therefore, the ILDO regulator 200 can adjust its output voltage to compensate for the level change of VFB relative to VREF1.

The output COMP of the comparator 210 may be sent to the pulse generator 220. The output COMP can cause the pulse generator 220 to generate a pulse that can be sent to the loop controller 230. The pulse generator 220 may be adapted to generate a signal indicative of a change in state detected by the comparator 210. In some embodiments, if the output COMP of the comparator 210 indicates that VFB has changed state to be higher than VREF1, the pulse generator 220 may generate a first type of pulse. If the output COMP of the comparator 210 indicates that VFB has changed state to low At VREF1, the pulse generator 220 can generate a second type of pulse. In some embodiments, the pulse generator 220 may generate the same pulse for any state change detected by the comparator 210. In such an embodiment, the comparator 210 can be connected to both the loop controller 230 and the pulse generator 220 so that when the loop controller 230 receives a pulse from the pulse generator 220, it can receive the COMP signal generated by the comparator 210 To indicate a change in the level of VFB relative to VREF1 (ie, VFB becomes higher than VREF1, or VFB becomes lower than VREF1). It should be understood that in some embodiments, the pulse generator 220 may not be used, and the output of the comparator 210 may be passed to the loop controller 230. In such an embodiment, as will be described in further detail below, the level of the COMP signal may indicate the level of VFB relative to VREF1, and the loop controller 230 may use the COMP signal according to a change in the state of the COMP signal Level to determine the number of switches enabled or disabled in the switching circuit 250.

The loop controller 230 may receive the signal PULSE from the pulse generator 220 and / or the signal COMP from the comparator 210 and determine the number of switches enabled or disabled in the switching circuit 250. In some embodiments where the loop controller 230 only receives the signal PULSE from the pulse generator 220, the signal PULSE may correspond to the state of the COMP output by the comparator 210. When COMP is at the first level, PULSE may correspond to the first pulse shape, the first amplitude and / or the first duration, and when COMP is at the second level, PULSE may correspond to the second pulse shape, the second amplitude and / Or second duration. In some embodiments where the loop controller receives both signals PULSE and COMP, PULSE may be the same pulse shape regardless of the level of COMP, and the loop controller 230 may be based on the level of COMP when the signal PULSE is received The number of enable switches in the switch circuit 250 is adjusted. In some embodiments where the loop controller 230 receives COMP instead of PULSE, when the signal COMP changes level, the loop controller 230 may adjust the number of enabled switches in the switching circuit 250. The number of enable switches in the switching circuit 250 may correspond to the level of the output voltage VOUT of the ILDO regulator 200. For example, if the loop controller 230 receives an indication that the feedback voltage VFB is lower than VREF1, the loop controller 230 may generate a signal to increase the number of switches enabled in the switching circuit 250 to increase the output of the ILDO regulator 200 Voltage. In such an example, if 5 switches are currently enabled in the switching circuit 250 and the loop controller 230 receives and indicates that VFB is low relative to VREF1, the loop controller 230 may generate a signal to enable the switching circuit 250 Sixth switch. Alternatively, the loop controller 230 may receive an indication about the magnitude of the difference between VFB and VREF1, and may enable a proportional number of switches in the switching circuit 250. In another example, if the loop controller 230 receives an indication that the feedback voltage VFB is relatively high with respect to VREF1, the loop controller 230 may generate a signal to disable additional switches in the switching circuit 250 in order to reduce the ILDO voltage regulator 200. The output voltage. In Figure 2A, N switches are described in switch circuit 250, where N is any positive integer greater than one. The loop controller 230 may be any controller suitable for determining the number of switches in the switching circuit 250 and generating signals to enable these switches, such as a field programmable gate array (FPGA), a microprocessor, or a hardware logic circuit.

The signal from the loop controller 230 may pass through the optional buffer circuit 240 before reaching the switching circuit 250. The buffer circuit 240 may include N buffer amplifiers, each buffer amplifier being connected from the loop controller 230 to a corresponding switch of the switching circuit 250. Therefore, each buffer amplifier of the buffer circuit 240 may provide a separate signal path between the loop controller 230 and each switch of the switching circuit 250. The buffer circuit 240 can adjust the impedance level seen by the output of the loop controller 230 and the input of the switch circuit 250 to drive the switch of the switch circuit 250.

The switching circuit 250 may include N switches controlled by the loop controller 230 for providing a conductive path between the high reference voltage VIN and the output VOUT of the ILDO regulator 200. The high reference voltage VIN can be provided by any known voltage source, such as a power supply or a battery. As shown in Figure 1, the output VOUT of the ILDO regulator 200 can be connected to a load circuit.

FIG. 2B shows an embodiment of the buffer circuit 240 and the switching circuit 250. In this example, N is equal to 3, but N can use any positive integer greater than or equal to 2. The loop controller 230 provides three output signals, one for each switch in the switching circuit 250. The output signal from the loop controller 230 may pass through a buffer amplifier in the buffer circuit 240 before being connected to a control terminal (eg, a gate) of a switch of the switching circuit 250. The switches in the switching circuit 250 may be connected in parallel, so that more switches are turned on to generate a higher output voltage or current at VOUT, and more switches are turned off to generate a lower output at VOUT. Output voltage, or current. It should be understood that the configuration of the buffer amplifier and switch connections shown is merely an example, and any suitable implementation that allows the use of the loop controller 230 to control the switches within the switch circuit 250 may be implemented in the present invention.

In some embodiments, it may be necessary to provide multiple reference voltages so that the loop controller can adjust the output voltages related to the multiple reference voltages. Such an embodiment may allow the output voltage to remain within a range or multiple ranges determined by multiple reference voltage levels. FIG. 3 illustrates an ILDO regulator 300 including another embodiment of a first branch 330 and a second branch 340. The second branch 340 of the ILDO regulator 300 may include a second comparator 310 and a second pulse generator 320. The second comparator 310 can receive the feedback voltage VFB and the second reference voltage VREF2 as input signals. VREF2 and VREF1 are the same or different reference voltages. The comparator 310 can compare VFB and VREF2, and indicate a state change between the two signals through a signal COMP2. For example, if VFB is initially lower than VREF2 and then becomes higher than VREF2, the comparator 310 may generate a signal COMP2 indicating a state change. Alternatively, if VFB is initially higher than VREF2 and then becomes lower than VREF2, the comparator 310 may generate a signal COMP2 indicating a change in state (COMB2 and VFB generated by VFB changing from below VREF2 to above VREF2 changing from above COMP2 generated below VREF2 may have different durations, amplitudes, etc.). The output COMP2 of the comparator 310 can reach the pulse generator 320 or the loop controller 230.

The state change detected and output by the comparator 310 may cause the pulse generator 320 to generate a pulse PULSE2, which may be sent to the loop controller 230. The pulse generator 320 may be any circuit suitable for generating a signal indicating a change in state detected by the comparator 310. In some embodiments, if the comparator 310 detects that the VFB has changed state to be higher than VREF2, the pulse generator 320 may generate a first type of pulse, and if the comparator 310 detects that the VFB has changed state to be lower than VREF2, then The pulse generator 320 may generate a second type of pulse. In some embodiments, the pulse generator 320 may periodically generate a pulse or signal PULSE2 unless the comparator 310 detects a change in the state of VFB relative to VREF2. In some embodiments, the pulse generator 320 may generate the same pulse for any change in the state detected by the comparator 310. It should be understood that in some embodiments, the pulse generator 320 may not be used, and the output COMP2 of the comparator 310 may be passed to the loop controller 230. In some embodiments, the pulse generator 320 may be used, and the output COMP2 of the comparator 310 may also be passed to the loop controller 230. In such an embodiment, if two state changes are detected, the loop controller 230 may use the outputs of the comparators 210 and 310 in combination with the outputs of the pulse generators 220 and 320 to determine the priority of the controller. For example, if VFB starts to fall below VREF1 and VREF2, but then rises quickly to exceed VREF1 and VREF2, in this example, VREF2> VREF1, the loop controller 230 may determine that it should handle the event generated by the second branch 340, namely the first The events on the second comparator 310 and the second pulse generator 320, because based on the relationship between the two reference voltages, processing the events on the second branch 340 will inherently satisfy the events on the first branch 330.

Although two branches 330 and 340 are depicted in FIG. 3, each branch serves as a signal chain for receiving a signal indicating an output voltage or a reference voltage, and is used to generate an event detection signal for transmission to the loop controller 230. It can be understood that the present invention You can use any number of branches. The signal indicating the output voltage may be a voltage or current signal with or without a scaling ratio with the output voltage. For example, three branches with three reference voltages may be used, or four branches with four reference voltages may be used. In addition, if a suitable comparator is used, multiple reference voltages can be used for a single branch. It should be understood that in some embodiments, a single comparator may be used with two reference voltages VREF1 and VREF2 without using two comparators. The output of the comparator may be a tristate signal indicating the level of VFB compared to two reference voltages, or the comparator may have two outputs, each output indicating that VFB is compared to one of the two references Level.

The ILDO regulator 300 with two branches can be used to monitor the output voltage VOUT and keep it within a predetermined limit. For example, VREF1 can be set as the lower limit voltage, and VREF2 can be set as the upper limit voltage. If it is specified that VOUT, which should be between VREF1 and VREF2 during system operation, is increased due to various parasitic effects or load effects, causing VFB to exceed the upper limit voltage VREF2, the comparator 310 will trigger an event and send an indication of the state change to the loop controller 230 and / or pulse generator 320. If the comparator 310 sends a signal to the pulse generator 320, the pulse generator 320 will then generate and send to the loop controller 230 a pulse corresponding to a change in the state of the comparator. The loop controller 230 will then reduce the number of switches that are turned on in the switching circuit 250 to reduce the output voltage VOUT. The number of deactivated switches can be a fixed amount (for example, the loop controller disables an additional switch for each event) or it can be a proportional amount (for example, the loop controller is disabled compared to VOUT for reference The difference in voltage (ie, the amount of VOUT greater than the reference voltage) is proportional to multiple switches). If VOUT drops due to various parasitic effects or load effects, causing VFB to drop below the lower limit voltage VREF1, the comparator 210 will trigger an event and send a signal indicating a state change to the loop controller 230 and / or the pulse generator 220. If the comparator 210 sends a signal to the pulse generator 220, the pulse generator 220 will then generate a pulse corresponding to the state change of the comparator 210 and send it to the loop controller 230. The loop controller 230 will then increase the number of conducting switches in the switching circuit 250 to increase the output voltage VOUT. The number of switches that are turned on can be a fixed amount (for example, the loop controller enables an additional switch for each event), or it can be a proportional amount (for example, the loop controller is disabled compared to reference with VOUT The difference in voltage (ie, VOUT is smaller than the reference voltage) is proportional to multiple switches).

In some embodiments, it may be necessary to control the output voltage relative to a time reference. If the output voltage is held at a fixed level for longer than the reference time, the output voltage level may need to be adjusted to provide precise control of the output voltage level. For example, if the desired output voltage level is 0.70V and the output voltage level remains at 0.69V for longer than a predetermined amount of time, it may be desirable to increase the output voltage level even if the resulting level is higher than 0.70V, so The average output voltage over a period of time is close to 0.70V.

FIG. 4 illustrates a single branch ILDO regulator 400 including a timer check circuit 410. The timer checking circuit 410 may include a time comparison circuit and a running timer. In some embodiments, the running timer may be separate from the timer checking circuit 410, and the timer checking circuit 410 may receive a timing signal from the running timer. When the comparator 210 detects an event based on the relative value of the feedback voltage VFB and the reference voltage VREF1 (ie, the relative value of the feedback voltage VFB and the reference voltage VREF1 changes, for example, VFB changes from below VREF1 to above VREF1, or VFB When changing from above VREF1 to below VREF1), the comparator 210 may send an instruction to the timer check circuit 410, the pulse generator 220, and the loop controller 230 (where at least one of the pulse generator 220 and the loop controller 230 is selected) The signal of the event. The timer check circuit 410 may compare the value of the running timer and the threshold time T1 when an event from the comparator 210 is received. If the value of the running timer is greater than the threshold time T1, it means that the output voltage VOUT remains at a single undesired If the level is too long, the timer check circuit 410 may trigger the loop controller 230 to adjust the number of on-state switches in the switch circuit 250 accordingly (for example, when the comparator 210 detects that the feedback voltage VFB is lower than the reference voltage VREF1 Low becomes higher than the reference voltage VREF1, and the value of the running timer is greater than the threshold time T1, the timer checking circuit 410 may trigger the loop controller 230 to reduce the number of conductive switches in the switching circuit 250 accordingly; instead, when comparing The controller 210 detects that the feedback voltage VFB is changed from higher than the reference voltage VREF1 to lower than the reference voltage VREF1 and the value of the running timer is greater than the threshold time T1. Then, the timer checking circuit 410 may trigger the loop controller 230 to increase the switching circuit accordingly. The number of on-switches in 250;). In this embodiment, whenever the switching circuit 250 adjusts the number of switches that are internally turned on according to the comparison result between the value of the running timer and the threshold time T1, or whenever the timer checking circuit 410 compares the value of the running timer with the threshold After time T1, the running timer in the timer checking circuit 410 may be reset, or the running timer in the timer checking circuit 410 may be reset when the comparison result of the comparator changes. The run timer can be any suitable timing circuit, such as an oscillator, a clock input, or a counter. The threshold time may be a preset time to adjust the action of the loop controller 230. In addition, the timer check circuit 410 may also or alternatively receive the feedback voltage VFB from the comparator 210 or directly from the input of the ILDO regulator 400. Therefore, if the timer check circuit 410 detects that the time when VFB is at a constant undesired level exceeds the threshold T1, the timer check circuit 410 may trigger the loop controller 230 to adjust the number of on-switches in the switch circuit 250 accordingly. Even if the comparator does not cause an event (for example, if the timer check circuit 410 detects that VFB is at a constant too low voltage level for more than T1, it can trigger the loop controller 230 to increase the conduction of the switch circuit 250 accordingly. The number of switches; on the contrary, if the timer checking circuit 410 detects that VFB is at a constant excessively high voltage level for more than T1, the loop controller 230 may be triggered to reduce the number of conductive switches in the switching circuit 250 accordingly; ). The time-based control allows finer control of the output voltage VOUT of the allowed system. The specific method is: first change the output voltage VOUT by using a voltage level based on a comparison relationship, and then readjust it over time based on timer control A voltage level of the output voltage VOUT. Therefore, in the embodiment of the present invention, the timer checking circuit may be used to prevent the output voltage VOUT from being maintained at a single undesired level for longer than a certain period of time. For example, it is acceptable for the output voltage to be slightly higher or lower than the desired output voltage for a short period of time, but it is not desirable to maintain the output voltage at a voltage level higher or lower than the desired level.

Figure 5 depicts a two-branch ILDO regulator 500, where each branch has a timer check circuit. Among them, the working principle of the first branch including the comparator 210, the timer checking circuit 410, the pulse generating circuit 220, and the loop controller 230 is the same as that in FIG. 4, and details are not described herein. This embodiment only discusses the working principle of the second branch including the comparator 310, the timer checking circuit 510, the pulse generating circuit 320, and the loop controller 230. Specifically, when the comparator 310 is based on the feedback voltage VFB and the reference voltage VREF2, The relative value detects an event (that is, the relative value of the feedback voltage VFB and the reference voltage VREF2 changes, for example, when VFB changes from below VREF2 to above VREF2, or VFB changes from above VREF2 to below VREF2) The generator may send a signal indicating an event to the timer check circuit 510 and the pulse generator 320 and the loop controller 230 (wherein at least one of the pulse generator 320 and the loop controller 230 may be selected for transmission). The timer check circuit 510 may compare the value of the running timer when the event from the comparator 310 is received with the threshold time T2. If the value of the running timer is greater than the threshold time T2, it means that the output voltage VOUT remains at a single undesired If the time of the level is too long, the timer checking circuit 510 may trigger the loop controller 230 to adjust the number of the on-switches in the switching circuit 250 accordingly (for example, when the comparator 310 detects that the feedback voltage VFB is lower than the reference voltage When VREF2 is low and becomes higher than the reference voltage VREF2, and the value of the running timer is greater than the threshold time T2, the timer check circuit 510 may trigger the loop controller 230 to correspondingly reduce the number of conductive switches in the switching circuit 250; instead, when The comparator 310 detects that the feedback voltage VFB is changed from higher than the reference voltage VREF2 to lower than the reference voltage VREF2 and the value of the running timer is greater than the threshold time T2. Then the timer check circuit 510 may trigger the loop controller 230 to increase the switch accordingly. The number of conductive switches in the circuit 250;). In this embodiment, whenever the switching circuit 250 adjusts the number of switches that are internally turned on according to the comparison result between the value of the running timer and the threshold time T2, or whenever the timer checking circuit 510 compares the value of the running timer with the threshold After the time T2, the running timer in the timer checking circuit 510 can be reset. The run timer can be any suitable timing mechanism, such as an oscillator, a clock input, or a counter. As described above, the threshold time may be a preset time to adjust an action taken by the loop controller 230. In addition, the timer checking circuit 510 may also or alternatively receive the feedback voltage VFB from the comparator 310 or directly receive the feedback voltage VFB from the input of the ILDO regulator 500. Therefore, if the timer check circuit 510 detects that the time that VFB is at a constant undesired level exceeds the threshold T2, the timer check circuit 510 can trigger the loop controller 230 to adjust the number of conductive switches in the switch circuit 250 accordingly. Even if the comparator does not cause an event (for example, if the timer check circuit 510 detects that VFB is at a constant too low voltage level for more than T2, it can trigger the loop controller 230 to increase the conduction in the switching circuit 250 accordingly. The number of switches; on the contrary, if the timer check circuit 510 detects that VFB is at a constant excessively high voltage level for more than T2, the loop controller 230 may be triggered to reduce the number of conductive switches in the switch circuit 250 accordingly; ) However, in the plurality of timer checking circuits, the interval of the plurality of timer checking circuits may be set to adjust the action taken by the loop controller 230. For example, if T1 is less than T2, in a case where the running timer reaches T1 and VOUT is at an undesired level, the loop controller 230 may set the number of switches that are turned on to the first configuration. If the running timer reaches a time between T1 and T2 and VOUT is at an undesired level, the loop controller 230 may set the number of switches that are turned on to the second configuration. Although two separate timer check circuits 410 and 510 are described in FIG. 5. It should be understood that two timer check circuits may be implemented as a single timer check circuit with multiple inputs and thresholds. In addition, it should be understood that although two branches are depicted in FIG. 5. Any number of branches and timer check circuits can be used to provide finer control over the output voltage VOUT.

Furthermore, in another embodiment, an ILDO regulator 500 with two branches can be used to monitor the output voltage VOUT and keep it within a predetermined limit. For example, VREF1 can be set as the lower limit voltage, and VREF2 can be set as the upper limit voltage. If it is specified that VOUT, which should be between VREF1 and VREF2 during system operation, increases due to various parasitic effects or load effects, so that VFB is lower than the lower limit voltage VREF1, the comparator 210 will trigger an event and send an indication of the state change to a timer The inspection circuit 410 and the loop controller 230 and the pulse generator 220 (wherein at least one of the pulse generator 220 and the loop controller 230 is selected). The timer check circuit 410 may compare the value of the running timer when the event from the comparator 210 is received with the threshold time T1. If the value of the running timer is greater than the threshold time T1, it means that the output voltage VOUT remains below VREF1 If the time of a certain undesired level is too long, the timer checking circuit 410 may trigger the loop controller 230 to increase the number of conducting switches in the switching circuit 250 accordingly. In this embodiment, whenever the switching circuit 250 adjusts the number of switches that are internally turned on according to the comparison result between the value of the running timer and the threshold time T1, or whenever the timer checking circuit 410 compares the value of the running timer with the threshold After the time T1, the running timer in the timer checking circuit 410 may be reset. If it is specified that VOUT, which should be between VREF1 and VREF2, increases due to various parasitic effects or load effects during system operation, so that VFB exceeds the upper limit voltage VREF2, the comparator 310 will trigger an event and send an indication of the state change to a timer check The circuit 510 and the loop controller 230 and the pulse generator 320 (where at least one of the pulse generator 320 and the loop controller 230 is selected). The timer check circuit 510 may compare the value of the running timer when the event from the comparator 310 is received with the threshold time T2. If the value of the running timer is greater than the threshold time T2, it means that the output voltage VOUT remains greater than VREF2 The time of a certain undesired level is too long, the timer checking circuit 510 can trigger the loop controller 230 to reduce the number of conducting switches in the switching circuit 250 accordingly. In this embodiment, whenever the switching circuit 250 adjusts the number of switches that are internally turned on according to the comparison result between the value of the running timer and the threshold time T2, or whenever the timer checking circuit 510 compares the value of the running timer with the threshold After the time T2, the running timer in the timer checking circuit 510 may be reset. In specific implementation, the threshold times T1 and T2 may be the same or different.

In some embodiments, the load circuit at the output of the ILDO regulator may include a mesh circuit. In this case, supplying the output of the ILDO regulator to one end of the mesh circuit may cause uneven power, voltage, or current distribution across the load circuit. Described here is a system with multiple ILDO regulators for providing power, voltage, or current at multiple points in a load circuit, where the ILDO regulators can communicate to maintain system stability or otherwise Improve control of the system.

FIG. 6 illustrates a system 600 including a first ILDO regulator 620 and a second ILDO regulator 630 coupled across a load circuit 610. In an embodiment where the load circuit 610 is equivalent to a resistor grid, if a single ILDO regulator is used and connected to one side of the load circuit 610, the grid may cause the voltage from the ILDO regulator to be on the load circuit 610 Non-uniform dissipation, resulting in inefficient operation and high power consumption. Therefore, the system 600 uses a first ILDO regulator 620 on the first side of the load circuit 610 and a second ILDO regulator 630 on the second side of the load circuit 610. By providing equal voltages on the separate sides of the load circuit 610, voltage dissipation across the grid can be reduced, and more uniform power consumption can be achieved. However, if the first ILDO regulator 620 and the second ILDO regulator 630 independently provide voltage to the grid, if the output voltages are not adjusted in a synchronous manner, the output voltages may be suppressed from each other.

FIG. 7 illustrates a system 700 having a first ILDO 620 and a second ILDO 630 coupled across a load circuit 610. The load circuit 610 includes N sub-circuits (irrespective of the number of switches in the ILDO switching circuit) arranged in the mesh network, where N is a positive integer greater than or equal to 1. Each of the sub-circuits 710, 720, and 730 may function as a sub-circuit within the load circuit 610 coupled to the first ILDO 620 and the second ILDO 630, but if the first ILDO regulator 620 and the second ILDO regulator 630 operate independently, The resistance value between each sub-circuit 710, 720, and 730 may cause uneven power consumption across these sub-circuits. Therefore, the first ILDO regulator 620 and the second ILDO regulator 630 can exchange control signals through a communication channel. For example, in a unidirectional embodiment, the loop controller of the first ILDO regulator 620 may receive signals from a comparator, a pulse generator, and / or a timer check circuit of the second ILDO regulator 630. Therefore, if the second ILDO regulator 630 detects that an event on the second side of the load circuit 610 does not occur on the first side of the load circuit 610, it may notify the first ILDO regulator 620 and the first ILDO stabilizes The loop controller of the voltage regulator 620 can change the number of switches that are turned on to regulate the output voltage of the first ILDO regulator 620 and prevent the damping effect from occurring through the uneven voltage applied to the load circuit 610. In another bi-directional embodiment, both ILDOs 620 and 630 can check circuits based on their timers, pulse generators and / or comparators communicate event information to each other to maintain a synchronized voltage output to load circuit 610. Although two ILDOs are depicted in Figures 6 and 7, it should be recognized that any number of ILDOs can be applied to the load circuit and synchronized.

For this reason, the data structure disclosed in the present invention and the mentioned code may be stored in whole or in part in a computer-readable storage medium, a hardware module, or a hardware device. The computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic or optical storage devices (eg, hard drives, magnetic tapes, optical drives, digital optical drives), or other current A medium capable of storing code and / or information known or to be developed in the future. The hardware modules or hardware devices disclosed in the present invention include, but are not limited to, Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), dedicated Or shared processors, and other hardware modules or devices that are currently known or will be developed in the future.

Although the embodiments of the present invention are described by a part of the embodiments, the present invention is not limited to the specific forms described herein. To be precise, the scope of the present invention is limited only by the scope of corresponding patent applications. In addition, although a feature may be described in only one specific embodiment, those skilled in the art may know that with reference to the present invention, multiple features in the described embodiments may be combined. In the context of patenting, the term "comprising" does not exclude the presence of other elements or steps.

Further, although a single feature may be included in different patent application scopes, these features may be advantageously combined as far as possible, and the inclusion in different patent application scopes does not indicate that the combination between features is not feasible and / or Adverse. In addition, the features included in the scope of one type of patent application are not meant to be limited to this category. On the contrary, it means that according to the actual situation, these features can also be applied to other types of patent scope.

The use of ordinal numbers such as "first", "second", and "third" used to modify elements in the scope of the patent application does not imply any priority, order of priority, order between elements, or implementation The chronological order of the methods, and is only used as an identifier to distinguish between different elements with the same name (with different ordinal numbers).

Certain terms are used in the description and the scope of patent applications to refer to specific elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The scope of this specification and the patent application does not use the difference in names as a way to distinguish components, but rather uses the difference in functions of components as a criterion for distinguishing components. The terms "including" and "including" mentioned throughout the specification and the scope of patent application are open-ended terms and should therefore be interpreted as "including but not limited to". "Substantially" means that within the acceptable error range, those skilled in the art can solve the technical problem within a certain error range, and basically achieve the technical effect. In addition, the term "coupled" includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. Device. The following is a preferred way of implementing the present invention, and the purpose is to explain the spirit of the present invention and not to limit the scope of protection of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

Although the present invention is disclosed as above with the preferred embodiment, it is not intended to limit the scope of the present invention. Those skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined by the scope of patent application. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

100‧‧‧Circuit Board

140‧‧‧package outer parts

110‧‧‧package parts

120, 300, 400, 620, 630‧‧‧ILDO voltage regulator

130, 610‧‧‧ load circuit

200‧‧‧DAC system

260‧‧‧Control circuit

210, 310‧‧‧ Comparator

220, 320‧‧‧pulse generator

230‧‧‧loop controller

240‧‧‧ buffer circuit

250‧‧‧ Switch Circuit

330‧‧‧ first branch

340‧‧‧first branch

410, 510‧‧‧Timer check circuit

700‧‧‧ system

710, 720, 730‧‧‧ Sub-circuits

FIG. 1 illustrates a circuit board 100 including a package component 110 and a package external component 140. FIG. 2A illustrates an embodiment of the ILDO regulator 200. FIG. 2B shows an embodiment of the buffer circuit 240 and the switching circuit 250. FIG. 3 illustrates an ILDO regulator 300 including another embodiment of a first branch 330 and a second branch 340. FIG. 4 illustrates a single branch ILDO regulator 400 including a timer check circuit 410. Figure 5 illustrates a dual-branch ILDO regulator 500. FIG. 6 illustrates a system 600 including a first ILDO regulator 620 and a second ILDO regulator 630 coupled across a load circuit 610. FIG. 7 illustrates a system 700 having a first ILDO 620 and a second ILDO 630 coupled across a load circuit 610.

Claims (18)

An output low-dropout voltage regulator includes: a comparison circuit configured to compare a signal representing a output of the low-dropout voltage regulator with a reference signal to generate a comparison result; a loop controller coupled to the comparison circuit, Configured to generate an output circuit control signal based at least in part on the comparison result; and an output circuit including two or more switching circuits configured to adjust the two or more based on the output circuit control signal The number of switching circuits that are turned on among the plurality of switching circuits. The low dropout voltage regulator according to claim 1, wherein the comparison circuit is coupled to the loop controller through a pulse generator configured to generate a pulse according to a change in the comparison result, Wherein the loop controller is configured to generate the output circuit control signal based on the pulse. The low dropout voltage regulator according to claim 2, wherein the pulse generator is configured to generate a first type of pulse when the output is greater than the reference signal, and when the output is less than the reference signal A second type of pulse is generated. The low dropout voltage regulator according to claim 1, wherein the loop controller is configured to generate at least one of the two or more switching circuits when the output is smaller than the reference signal. An output circuit control signal of a switching circuit; or the loop controller is configured to generate output circuit control that disables at least one of the two or more switching circuits when the output is greater than the reference signal signal. The low-dropout voltage regulator according to claim 1, further comprising: a timer check circuit configured to, when the comparison result of the comparison circuit changes, change the execution time of the timer when the comparison result changes and The first reference time is compared to generate a time check signal. The low dropout voltage regulator according to claim 5, wherein the loop controller is further configured to generate the output circuit control signal based on the time check signal, wherein when the time check signal indicates the execution time When the first reference time is exceeded, the output circuit control signal is generated. The low-dropout voltage regulator according to claim 5 or 6, wherein: the execution time is reset after the output circuit adjusts the number of turned-on switching circuits; or the execution time is in the timer check circuit The execution time is reset after comparing the first reference time; or the execution time is reset when a comparison result of the comparator changes. The low-dropout voltage regulator according to claim 1, wherein the comparison circuit is a first comparison circuit, the reference signal is a first reference signal, and the comparison result generated by the comparison circuit is a first comparison result. The low-dropout regulator further includes: a second comparison circuit configured to compare a signal representing an output of the low-dropout regulator and a second reference signal to generate a second comparison result, wherein the loop control And an amplifier further coupled to the second comparison circuit and configured to generate the output circuit control signal based at least in part on the first comparison result and the second comparison result. The low dropout voltage regulator according to claim 8 further comprises: a second pulse generator coupled between the second comparison circuit and the pulse generator, the second pulse generator being configured to A second pulse is generated according to a change in the second comparison result. The low-dropout voltage regulator according to claim 8 further comprises: a first timer checking circuit configured to change the first comparison result when the comparison result of the first comparison circuit changes. A first execution time of a running timer is compared with a first reference time to generate a first time check signal; and a second timer check circuit is configured to, when a comparison result of the second comparison circuit changes, When the second comparison result changes, the second execution time of the second running timer is compared with the second reference time to generate a second time check signal. The low dropout voltage regulator according to claim 8, wherein the loop controller is further configured to generate the output circuit control signal based on the first time check signal and / or the second time check signal; Wherein when the first time check signal indicates that the first execution time exceeds the first reference time, an output circuit control signal is generated based on the first comparison result; wherein when the second time check signal indicates the When the second execution time exceeds the second reference time, an output circuit control signal is generated based on the second comparison result. The low-dropout voltage regulator according to claim 10 or 11, wherein the first execution time and the second execution time are reset after the output circuit adjusts the number of switching circuits that are turned on. The low dropout voltage regulator according to claim 10 or 11, wherein the first execution time is reset after the first timer checking circuit compares the first execution time with a first reference time; The second execution time is reset after the second timer checking circuit compares the second execution time with a second reference time. The low dropout voltage regulator according to patent application range 8, wherein the loop controller is configured to generate the two or more switching circuits when the output signal is smaller than the first reference signal. An output circuit control signal of at least one of the switching circuits, and output circuit control that disables at least one of the two or more switching circuits when the output signal is greater than the second reference signal signal. A system includes: a load circuit, the load circuit including a plurality of sub-circuits; a first low-dropout voltage regulator coupled to a first end of the load circuit, configured to connect a first of the first low-dropout voltage regulator An output is provided to the first end of the load circuit; and a second low-dropout voltage regulator coupled to the second end of the load circuit is configured to provide a second low-dropout voltage regulator. An output is provided to the second end of the load circuit; wherein the first low dropout voltage regulator is configured to send a first indication to the second low dropout voltage regulator indicating a level change of the first output. Wherein, the first low-dropout voltage regulator is the low-dropout voltage regulator according to any one of claims 1-18. The system of claim 15, wherein the second low dropout voltage regulator is configured to provide the second output based on the first indication. The system according to claim 15, wherein the second low-dropout voltage regulator is configured to send a second indication to the first low-dropout voltage regulator indicating a level change of the second output voltage, The second low-dropout voltage regulator is the low-dropout voltage regulator according to any one of claims 1-17. The system of claim 17, wherein the first low dropout voltage regulator is configured to provide the first output based on the second indication.