TW201939708A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201939708A
TW201939708A TW107127259A TW107127259A TW201939708A TW 201939708 A TW201939708 A TW 201939708A TW 107127259 A TW107127259 A TW 107127259A TW 107127259 A TW107127259 A TW 107127259A TW 201939708 A TW201939708 A TW 201939708A
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substrate
mounting substrate
semiconductor device
layer
wiring
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佐野雄一
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種能夠抑制於封裝內部產生之電磁波雜訊洩漏之半導體裝置。 本實施形態之半導體裝置具備基板。半導體晶片搭載於基板之上。第1及第2接地配線設置於基板之內部。密封樹脂層係以將半導體晶片密封之方式設置於基板上。導電性之屏蔽層設置於密封樹脂層之上表面、密封樹脂層之側面、及基板之側面，且於基板之側面連接於第1及第2接地配線。第1及第2接地配線係藉由於與屏蔽層之接觸面附近展開而相互連接。

Description

半導體裝置
本實施形態係關於一種半導體裝置。
存在於半導體封裝之上表面或側面設置有屏蔽層之情形。該屏蔽層係為了抑制於半導體封裝內部產生之電磁波雜訊向外部漏出而經由設置於安裝基板之接地配線接地。然而，期望進一步減少電磁波雜訊之洩漏。
實施形態提供一種能夠抑制於封裝內部產生之電磁波雜訊洩漏之半導體裝置。
本實施形態之半導體裝置具備基板。半導體晶片搭載於基板之上。第1及第2接地配線設置於基板之內部。密封樹脂層係以將半導體晶片密封之方式設置於基板上。導電性之屏蔽層設置於密封樹脂層之上表面、密封樹脂層之側面、及基板之側面，且於基板之側面連接於第1及第2接地配線。第1及第2接地配線係藉由於與屏蔽層之接觸面附近展開而相互連接。
[相關申請案] 本申請案享有以日本專利申請案2018-48308號(申請日：2018年3月15日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
以下，參照圖式對本發明之實施形態進行說明。本實施形態並非限定本發明者。於以下之實施形態中，安裝基板之上下方向表示將供設置半導體晶片之面設為上之情形時之相對方向，有時與按照重力加速度所得之上下方向不同。
以下之實施形態中，對應用於BGA(Ball Grid Array，球狀柵格陣列)之半導體裝置(半導體封裝)之一例進行說明，但對於LGA(Land Grid Array，焊盤網格陣列)亦能同樣地應用。 (第1實施形態)
圖1係表示第1實施形態之半導體裝置10之構成之一例的剖視圖。半導體裝置10具備安裝基板2、外部連接端子3、半導體晶片1a〜1h、11、接合線4a、4b、5a、5b、12、密封樹脂層6、及屏蔽層8。
安裝基板2具有嵌埋於絕緣材料內之多層配線層。安裝基板2亦被簡稱為基板。絕緣材料例如包含絕緣層9a、9b。絕緣層9a、9b例如使用玻璃環氧樹脂等絕緣材料。多層配線層例如包含配線層2a、2b、2c。配線層2a、2b、2c例如使用金、銀、銅、鋁、鎳、鈀、鎢等導電性金屬。又，於安裝基板2之上表面，設置有與配線層2a、2b、2c電性連接之焊墊電極Pa、Pb。焊墊電極Pa、Pb係經由接合線4a、4b、5a、5b而電性連接於半導體晶片1a〜1h。於安裝基板2之背面，例如設置有焊料凸塊3。焊料凸塊3與未圖示之其他半導體裝置電性連接。
配線層2c係設置於配線層2a與配線層2b之間。配線層2c之一端於安裝基板2之側面露出，且具有在安裝基板2之厚度方向(Z方向)上被切斷所成之切斷面。配線層2c之切斷面係利用切割刀片切斷所成之面。配線層2c被設置為接地配線，電性連接於大地。
又，為了將配線層2a、2b、2c中之任一者於配線層間電性連接，安裝基板2具有貫通安裝基板2之導通孔15。導通孔15具有：導體層13，其形成於貫通安裝基板2之貫通孔之內表面；及填孔材14，其填充於導體層13內側之中空部。
半導體晶片1a〜1h、11係設置於安裝基板2之上表面上。半導體晶片11係藉由例如DAF(Die Attachment Film，晶片貼膜)(未圖示)等而接著於安裝基板2之上表面上。半導體晶片11經由接合線12與焊墊電極12a電性連接。半導體晶片11例如為NAND(Not-AND，反及)型EEPROM(Electrically Erasable Programmable Read Only Memory，電子可抹除可程式化唯讀記憶體)之控制器。半導體晶片11由樹脂層16被覆。
半導體晶片1a〜1h係設置於半導體晶片11之上方，且積層於樹脂層16上。半導體晶片1a〜1h係藉由DAF而接著於樹脂層16上或其他半導體晶片1a〜1g上。半導體晶片1a〜1h例如為NAND型EEPROM晶片。
半導體晶片1a〜1e藉由接合線4a、5a與焊墊電極Pa電性連接。又，半導體晶片1f〜1h藉由接合線4b、5b與焊墊電極Pb電性連接。
密封樹脂層6係以被覆半導體晶片1a〜1h、11及接合線4a、4b、5a、5b、12之方式，設置於安裝基板2之上表面上。
屏蔽層8係以被覆密封樹脂層6之上表面、密封樹脂層6之側面、及安裝基板2之側面之方式設置。屏蔽層8亦設置於安裝基板2之側面，且連接於配線層2c。
設置屏蔽層8之理由如下所述。自半導體晶片1a〜1h、11及安裝基板2之配線層會放射電磁波。該電磁波有對半導體裝置10外部之機器造成不良影響之虞。由此，設置覆蓋密封樹脂層6及安裝基板2之側面之屏蔽層8。屏蔽層8將來自半導體裝置10內部之電磁波阻斷。藉此，抑制來自半導體晶片1a〜1h、11及安裝基板2之配線層的電磁波向外部洩漏。
為了有效地發揮此種電磁波屏蔽功能，屏蔽層8較佳為由電阻率較低之金屬層形成。例如，屏蔽層8係使用銅、銀、鎳、不鏽鋼(SUS)等導電性金屬或其等中之任意複數種材料之積層膜。
外部連接端子3係設置於安裝基板2之下表面，且與安裝基板2之配線層2b電性連接。外部連接端子3例如為焊料球。再者，作為接地配線之配線層2c經由外部連接端子3而與半導體裝置10外部之大地電性連接。
藉由此種構成，半導體裝置10能夠將電磁波向大地傳輸，從而抑制電磁波向半導體裝置10之封裝外部洩漏。
圖2(A)及圖2(B)係圖1所示之安裝基板2之側面中之配線層2c之剖視圖。圖2(A)係圖1之安裝基板2之側面附近之圓C的放大剖視圖。圖2(B)係沿著圖2(A)之B-B線之剖視圖。即，圖2(B)表示已將屏蔽層8去除時之安裝基板2之側面，且係自圖1之X方向觀察到之剖視圖。再者，於圖2(B)中，以實線Ls表示已將屏蔽層8去除時露出於安裝基板2之側面之配線層2c，以虛線Lb表示安裝基板2內部之配線層2c。所謂安裝基板2之內部係指圖2(A)之由絕緣層9a及9b夾著之區域。
如圖2(A)所示，將露出於安裝基板2之側面F2之配線層2c之側面設為F2c。配線層2c之側面F2c相較於安裝基板2內部之配線層2c而言變寬。因此，如圖2(B)所示，配線層2c之側面F2c之面積(由Ls包圍之區域之面積)大於安裝基板2內部之配線層2c之面積(由Lb包圍之區域之面積之和)。其原因在於，於安裝基板2被切割刀片切斷時，配線層2c與切割刀片接觸而延伸。
又，如圖2(B)所示，複數個配線層2c於安裝基板2之側面F2係排列於同一配線層內。即，複數個配線層2c於安裝基板2內沿Y方向排列。進而，換言之，複數個配線層2c係於安裝基板2之側面F2沿相對於安裝基板2之上表面Ft大致平行之方向排列。配複數個配線層2c係接地配線，能夠電性連接於大地。再者，於圖2(B)中示出2個配線層2c，但亦可排列3個以上之配線層2c。又，配線層2c由於為接地配線，故而即便相互短路亦不存在問題。
如圖2(B)之虛線Lb所示，複數個配線層2c於安裝基板2之內部相互分離。然而，如實線Ls所示，複數個配線層2c於與安裝基板2之側面F2大致同一面之側面F2c沿Y方向擴展而相互連接。即，相鄰之複數個配線層2c彼此在安裝基板2之側面與屏蔽層8之間之接觸面附近相互短路且連接。於該情形時，在安裝基板2內之與安裝基板2之側面F2大致平行之剖面中，複數個配線層2c與屏蔽層8之接觸面積(由實線Ls包圍之區域之面積)變得大於複數個配線層2c之剖面面積之和(由虛線Lb包圍之區域之面積之和)。
藉此，配線層2c與屏蔽層8之接觸面積變大，而能夠提高兩者之連接狀態。即，能使屏蔽層8與配線層(接地配線)2c之接觸電阻降低。其結果，半導體裝置10可使大部分電磁波向大地釋放，從而減少電磁波向半導體裝置10外部之洩漏。又，藉由使相鄰之複數個配線層2c於安裝基板2之側面F2擴展並連接，可使配線層2c本身具有電磁屏蔽效果。其結果，半導體裝置10能夠進一步減少電磁波之洩漏。
隨著半導體封裝之微細化，安裝基板2亦被微細化。因此，相鄰之複數個配線層2c之間隔D2c變窄，而存在如下情形：於利用切割刀片將安裝基板2切斷時，相鄰之複數個配線層2c自然地連接。如此，為了藉由切割使複數個配線層2c自行對準地連接，較佳為相鄰之配線層2c彼此之間隔D2c係安裝基板2之側面F2中之配線層2c之擴展寬度EXT2c之2倍以下。藉此，於切割後，複數個配線層2c於安裝基板2之側面F2擴展而可自行對準地連接。 (第2實施形態)
圖3(A)及圖3(B)係表示第2實施形態之半導體裝置10之構成例之剖視圖。圖3(A)係圖1之安裝基板2之側面附近之圓C的放大剖視圖。圖3(B)係沿著圖3(A)之B-B線之剖視圖。即，圖3(B)表示已將屏蔽層8去除時之安裝基板2之側面，且係自圖1之X方向觀察到之剖視圖。再者，於圖3(B)中，以實線Ls表示已將屏蔽層8去除時露出於安裝基板2之側面之配線層2c，以虛線Lb表示安裝基板2內部之配線層2c。
第2實施形態與第1實施形態之不同點在於：複數個配線層2c沿縱向(Z方向)排列。第2實施形態之半導體裝置10之其他構成可與第1實施形態之半導體裝置10之對應構成相同。
與第1實施形態同樣地，配線層2c之側面F2c相較於安裝基板2內部之配線層2c而言變寬。因此，配線層2c之側面F2c之面積(由Ls包圍之區域之面積)大於安裝基板2內部之配線層2c之面積(由Lb包圍之區域之面積之和)。
又，如圖3(B)所示，複數個配線層2c係於安裝基板2之側面F2作為不同之配線層沿縱向排列。即，複數個配線層2c係於安裝基板2內沿Z方向排列。進而，換言之，複數個配線層2c係於安裝基板2之側面F2沿相對於安裝基板2之上表面Ft大致垂直之方向排列。複數個配線層2c係接地配線，能夠電性連接於大地。
如圖3(B)之虛線Lb所示，複數個配線層2c於安裝基板2內相互分離。然而，如實線Ls所示，複數個配線層2c在與安裝基板2之側面F2大致同一面之側面F2c亦沿Z方向擴展而相互連接。即，相鄰之複數個配線層2c彼此在安裝基板2之側面與屏蔽層8之間之接觸面附近相互短路且連接。於該情形時，在安裝基板2內之與安裝基板2之側面F2大致平行之剖面中，複數個配線層2c與屏蔽層8之接觸面積(由實線Ls包圍之區域之面積)變得大於複數個配線層2c之剖面面積之和(由虛線Lb包圍之區域之面積之和)。
藉此，配線層2c與屏蔽層8之接觸面積變大，而能夠提高兩者之連接狀態。即，能使屏蔽層8與配線層(接地配線)2c之接觸電阻降低。其結果，半導體裝置10可使大部分電磁波向大地釋放，從而減少電磁波向半導體裝置10外部之洩漏。又，藉由使相鄰之複數個配線層2c於安裝基板2之側面F2擴展並連接，可使配線層2c本身具有電磁屏蔽效果。其結果，半導體裝置10能夠進一步減少電磁波之洩漏。
為了藉由切割使複數個配線層2c自行對準地連接，較佳為於Z方向上相鄰之配線層2c彼此之間隔D2c係安裝基板2之側面F2中之配線層2c之擴展寬度EXT2c之2倍以下。藉此，於切割後，複數個配線層2c於安裝基板2之側面F2擴展而可自行對準地連接。 (變化例)
圖4係表示按照變化例而得之半導體裝置10之構成例之剖視圖。本變化例係第1實施形態與第2實施形態之組合。本變化例中，複數個配線層2c係於安裝基板2之側面F2分別沿相對於安裝基板2之上表面Ft大致平行之方向及大致垂直之方向排列。即，複數個配線層2c於安裝基板2之側面F2設置於同一配線層及不同之配線層。而且，複數個配線層2c於大致平行方向及大致垂直方向上相互連接。
如此，亦可使於側面F2內(沿Z方向及Y方向)排列之複數個配線層2c相互連接。藉此，配線層2c與屏蔽層8之接觸面積變大，而能夠提高兩者之連接狀態。其結果，半導體裝置10可使大部分電磁波向大地釋放，從而減少電磁波向半導體裝置10外部之洩漏。又，藉由使相鄰之複數個配線層2c於安裝基板2之側面F2擴展並連接，可使配線層2c本身具有電磁屏蔽效果。
再者，於圖4中示出4條配線，但亦可將5條以上之配線二維配置於側面F2內。藉此，亦能以配線層2c之金屬覆蓋安裝基板2之側面F2整體。其結果，半導體裝置10能夠進一步減少電磁波之洩漏。
已對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出，並非意圖限定發明之範圍。該等實施形態能以其他各種形態實施，且能夠於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，同樣地包含於申請專利範圍所記載之發明及其均等之範圍內。
1a〜1h‧‧‧半導體晶片
2‧‧‧安裝基板
2a‧‧‧配線層
2b‧‧‧配線層
2c‧‧‧配線層
3‧‧‧外部連接端子
4a‧‧‧接合線
4b‧‧‧接合線
5a‧‧‧接合線
5b‧‧‧接合線
6‧‧‧密封樹脂層
8‧‧‧屏蔽層
9a‧‧‧絕緣層
9b‧‧‧絕緣層
10‧‧‧半導體裝置
11‧‧‧半導體晶片
12‧‧‧接合線
12a‧‧‧焊墊電極
13‧‧‧導體層
14‧‧‧填孔材
15‧‧‧導通孔
16‧‧‧樹脂層
C‧‧‧圓
D2c‧‧‧相鄰之配線層2c彼此之間隔
F2‧‧‧安裝基板2之側面
F2c‧‧‧配線層2c之側面
Ft‧‧‧安裝基板2之上表面
Lb‧‧‧虛線
Ls‧‧‧實線
Pa‧‧‧焊墊電極
Pb‧‧‧焊墊電極
X‧‧‧方向
Y‧‧‧方向
Z‧‧‧方向
圖1係表示第1實施形態之半導體裝置之構成之一例的剖視圖。 圖2(A)、(B)係圖1所示之安裝基板之側面中之配線層之剖視圖。 圖3(A)、(B)係表示第2實施形態之半導體裝置之構成例之剖視圖。 圖4係表示按照變化例而得之半導體裝置之構成例之剖視圖。

Claims (6)

  1. 一種半導體裝置，其具備： 基板； 半導體晶片，其搭載於上述基板之上； 第1及第2接地配線，其等設置於上述基板之內部； 密封樹脂層，其以將上述半導體晶片密封之方式設置於上述基板上；及 導電性之屏蔽層，其設置於上述密封樹脂層之上表面、上述密封樹脂層之側面、及上述基板之側面，且於上述基板之側面連接於上述第1及第2接地配線；且 上述第1及第2接地配線係藉由於與上述屏蔽層之接觸面附近展開而相互連接。
  2. 如請求項1之半導體裝置，其中上述第1及第2接地配線彼此於上述基板之側面與上述屏蔽層之間相互連接。
  3. 如請求項1或2之半導體裝置，其中上述第1及第2接地配線與上述屏蔽層之接觸面積於上述基板內之與上述基板之側面大致平行之剖面中，大於上述第1及第2接地配線之剖面面積之和。
  4. 如請求項1或2之半導體裝置，其中上述第1及第2接地配線間之間隔係上述基板之側面中之上述第1及第2接地配線之擴展寬度之2倍以下。
  5. 如請求項1或2之半導體裝置，其中上述第1及第2接地配線於上述基板之側面沿相對於上述基板之上表面大致平行之方向排列，且相互連接。
  6. 如請求項1或2之半導體裝置，其中上述第1及第2接地配線於上述基板之側面沿相對於上述基板之上表面大致垂直之方向排列，且相互連接。
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