TW202103013A - An interrupt process system and method for pcie with the heterogeneous equipment - Google Patents

Abstract

An Interrupt process system and method for PCIE with the heterogeneous equipment comprises of a PCIE adapter card, a storage unit and a process unit. The PCIE adapter card includes a control unit, an identify information and a communication connector. The storage unit includes a service program, a driver and a buffer structure. The process unit perform the driver and service program. The driver builds a channel according to the identify information. The channel map to the communication connector by the driver. The channel transmission the ISR. If the driver detects the ISR in the buffer structure, the service program performs the ISR.

Description

Interrupt processing system and method applied to PCIE to heterogeneous equipment

A control processing system and method for terminal equipment, particularly related to the interrupt processing system and method applied to PCIE to heterogeneous equipment.

For traditionally used various low-speed communication interfaces (for example: Digital I/O, Analog I/O or RS-232, etc.), although it can be transferred to other high-speed communication interfaces (for example: Universal Serial Bus (Universal Serial Bus, USB) or Peripheral Component Interconnect Express (PCIE)). However, the interrupt processing mechanism (Interrupt Service Routine, ISR) limited by the traditional communication interface will also affect the transmission efficiency in the high-speed transmission interface.

Because traditional communication uses a polling mechanism, the controller will inquire each terminal device connected one by one whether there is an interrupt request. When a terminal device issues an interrupt request, the controller will process the interrupt request before inquiring whether the terminal device has issued an interrupt request. Since the controller can only handle the current interrupt request, the interrupt request of other devices will be retained and cannot be received, which will cause congestion in the transmission of the terminal device.

In addition to the difference in hardware architecture, the software also needs to be coordinated accordingly. The operation system is an indispensable role for the computer. The operating system not only provides an interface for user operations, but also controls the processing of computer-related hardware resources. In order to allow the operating system to more fully support various hardware resources, each type of hardware has a corresponding driver to serve as an intermediary communication between hardware and software.

Because the driver directly affects the operating system and hardware, each driver must pass the operating system certification. Take Microsoft's Windows operating system (Windows OS) as an example. When the hardware supplier manufactures a new interface card or revises the driver, Suppliers need to provide drivers again to Microsoft. After Microsoft confirms that the new version of the driver is correct, it can be provided to end customers. But every time you verify the driver, you need to pay a verification fee to Microsoft, and the verification process takes a long time. Therefore, for the supplier, the driver needs to be verified for each revision, and the verification procedure is a lot of development costs.

The present invention provides an interrupt processing system applied to PCIE to heterogeneous equipment, which is used to reduce the waiting time of processing equipment interrupts and to reduce the verification cost of the driver program for inspection.

The interrupt processing system applied to PCIE to heterogeneous equipment of the present invention includes a PCIE adapter card, a storage unit and a processing unit. The PCIE adapter card has a control unit, identification information, and at least one communication interface. The control unit is electrically connected to the communication interfaces; the storage unit has a service program, a driver program, and a plurality of cache structures, and each cache structure is used to store interrupts. Requirements: The processing unit is electrically connected to the PCIE adapter card and the storage unit. The processing unit executes the driver and service program. The driver establishes multiple transmission channels based on the identification information, and the driver assigns the corresponding communication interfaces to the different transmission channels. , The transmission channel is used to transmit interrupt request or access request; if the driver detects any transmission channel transmission interrupt request, the driver will store the interrupt request in the cache structure. If there is an interrupt request in the cache structure, the service program will handle the interrupt request .

The present invention also provides an interrupt processing method applied to PCIE to heterogeneous devices, including: running a driver and a service program in an operating system; initializing a PCIE adapter card so that the service program drives multiple sets of communication interfaces of the PCIE adapter card to the operating system It is mapped to multiple transmission channels; the driver polls and monitors the transmission channel, and receives the interrupt request or access request issued by the transmission channel; when the driver detects that the interrupt request is sent, the driver saves the interrupt request to Cache structure; if there is an interrupt request in the cache structure, the interrupt request will be handled by the service program.

The interrupt processing system and method for heterogeneous equipment applied to PCIE of the present invention is applied to the relevant control of various heterogeneous equipment by a high-speed transmission interface. Since the driver program and the service program of the present invention process their respective procedures, the service program does not need to wait for the completion of the interrupt request before executing the next interrupt request. In this way, the driver can always detect interrupt requests, and the service program can handle interrupt requests full-time. When the developer’s When the content is changed, the developer does not need to re-verify the driver. Therefore, the present invention not only improves the interrupt processing efficiency of the terminal device, but also reduces the verification cost of sending the driver for verification every time the version is revised.

With regard to the features and implementation of the present invention, the best embodiments are described in detail as follows in conjunction with the drawings.

100‧‧‧Interrupt handling system

110‧‧‧Processing unit

120‧‧‧Storage Unit

121‧‧‧Operating System

122‧‧‧Service Program

123‧‧‧Driver

124‧‧‧Cache structure

130‧‧‧PCIE riser card

131‧‧‧Control Unit

132‧‧‧Memory Unit

133‧‧‧PCIE pin

135‧‧‧Communication interface

136‧‧‧Identification information

140‧‧‧Terminal equipment

310‧‧‧Transmission Channel

320‧‧‧Interrupt request

330‧‧‧Completion notice

411‧‧‧First Device

412‧‧‧Second device

413‧‧‧Third equipment

414‧‧‧Fourth equipment

421‧‧‧The first channel

422‧‧‧Second channel

423‧‧‧Third channel

424‧‧‧Fourth channel

431‧‧‧First cache

432‧‧‧Second Cache

433‧‧‧Third cache

434‧‧‧Fourth cache

Figure 1 is a schematic diagram of the system architecture of the present invention.

Figure 2 is a schematic diagram of the operation flow of the present invention.

FIG. 3A is a schematic diagram of the operation structure of the present invention.

FIG. 3B is a schematic diagram of the operation structure of the present invention.

FIG. 3C is a schematic diagram of the operation structure of the present invention.

FIG. 3D is a schematic diagram of another operational architecture of the present invention.

Figure 3E is a schematic diagram of the queue of multiple interrupt requests in the cache structure of the present invention.

Please refer to Figure 1, which is a schematic diagram of the system architecture of the present invention. The interrupt processing system 100 of the present invention can be applied to a personal computer, a notebook computer, or an embedded computer with PCIE pins 133. The PCIE interrupt processing system 100 for heterogeneous devices of the present invention includes a processing unit 110, a storage unit 120, and a PCIE adapter card 130. The processing unit 110 is electrically connected to the storage unit 120 and the PCIE riser card 130. The heterogeneous equipment referred to in the present invention refers to PCIE pin-based communication interface equipment compared to other types of communication interface equipment. . For example, taking the PCIE adapter card 130 to the RS-232 printer as an example, the RS-232 printer is a heterogeneous device. The storage unit 120 stores an operation system 121 (operation system), a service program 122 (service program), a driver program 123 (driver), and a cache structure 124. The processing unit 110 is used to run an operating system, a service program 122, a driver program 123, and an application program (application), and divides a plurality of cache structures 124 in the storage unit 120.

The PCIE riser card 130 can not only be installed in the PCIE slot of the main board, but also can be installed in the M.2 slot of the compatible PCIE riser card 130. In the present invention, the PCIE slot is taken as an example, and it is not limited to this. The PCIE riser card 130 includes a control unit 131, a memory unit 132, PCIE pins 133 and at least one communication interface 135. Control sheet The element 131 is electrically connected to the memory unit 132, the PCIE pin 133, and the communication interfaces 135. The storage unit 132 stores identification information 136. The PCIE pin 133 is used to connect to the corresponding slot of the motherboard, so that the control unit 131 can be coupled to the processing unit 110. The identification information 136 is used to record each communication interface 135 and the type of the PCIE riser card 130, and the identification information 136 also records the memory space configuration of each communication interface 135. The type of communication interface 135 is analog input/output, digital input/output, serial port, parallel port, or universal serial bus (Universal Serial Bus, USB). Each communication interface 135 can be connected to a terminal device 140 of a corresponding type of interface. For example, the serial communication interface 135 can be connected to a terminal device 140 such as a barcode scanner or a printer.

The control unit 131 is electrically connected to the terminal device 140 through the communication interface 135, and the control unit 131 is also electrically connected to the processing unit 110. When the PCIE riser card 130 is inserted into the slot, the control unit 131 will send the identification information 136 to the processing unit 110. The processing unit 110 determines the type and quantity of the communication interface 135 mounted on the PCIE riser card 130 according to the identification information 136. Then, the processing unit 110 establishes a transmission channel 310 (channel) of each communication interface 135 according to the identification information 136. Each group of transmission channels 310 corresponds to the communication interface 135. The transmission channel 310 is used to define the type of the connected terminal device 140.

For example, if the PCIE riser card 130 has two communication interfaces 135, the transmission channel 310 of the first group may be the RS-232 communication interface 135, and the transmission channel 310 of the second group may correspond to the serial communication interface 135. The service program 122 can configure the corresponding transmission channel 310 in the operating system according to the identification information 136, and at the same time assign the memory address and section space of each transmission channel 310, and enable the data of the transmission channel 310 to be mapped. And are stored in the cache structure 124. The cache structure 124 can be implemented in a queue or a stack.

Generally speaking, the terminal device 140 may send an interrupt request 320 (Interrupt Service Routine, ISR) or access request to the processing unit 110. The interrupt request 320 is used to send a signal required by the terminal device 140 to the control unit 131 so that the processing unit 110 can allocate related hardware resources to the terminal device 140. The access request is a data transmission request from the terminal device 140 to the processing unit 110. Because the interrupt requirement 320 of the conventional technology will affect the processing unit The processing schedule of 110 prevents the interrupt request 320 of other terminal devices 140 from being processed immediately. As a result, the processing efficiency of the computer is low. The types of access requests are event, command, or data. The three types of access requests respectively indicate the priority order of execution. The highest priority access request is the event, and the lowest priority access request is the data.

In order to further explain the operation of the present invention, please refer to Fig. 2, which is a schematic diagram of the operation process of the present invention. The PCIE interrupt processing method for heterogeneous devices of the present invention includes: Step S210: Start the computer and run the driver and service program in the operating system; Step S220: Initialize the PCIE adapter card, and enable the service program to drive multiple sets of PCIE adapter cards The communication interface is mapped into multiple transmission channels in the operating system; Step S230: The driver polls and monitors the transmission channels, and receives the interrupt request or access request issued by the transmission channel; Step S240: Detect the current buffer structure Step S241: If there is an interrupt request in the cache structure, the service program handles the interrupt request; Step S242: If there is no interrupt request in the cache structure, the service program moves to the next cache structure and detects whether there is an interrupt request ; Step S250: When the driver detects the access request issued by the transmission channel, call the service program to execute the access request.

First, start the computer and run the driver 123 and the service program 122 of the PCIE riser card 130 in the operating system 121. At the same time, the operating system 121 also initializes the installed PCIE riser card 130, and the operating system 121 sets the type and corresponding number of the transmission channel 310 according to the identification information 136 of the PCIE riser card 130.

At the same time, the communication interface 135 can be selectively connected to the physical terminal device 140 or not connected to the terminal device 140. The service program 122 is mapped into multiple transmission channels 310 in the operating system 121 according to the type and quantity of the transmission channels 310. The service program 122 allocates a corresponding memory address and section to each transmission channel 310. And the service program 122 divides the buffer structure 124 corresponding to the number of transmission channels 310 in the storage unit 120, so that the buffer structure 124 can store the request or data transmitted by the transmission channel 310.

After the terminal device 140 is connected to the communication interface 135, the terminal device 140 can An interrupt request 320 or an access request is sent to the processing unit 110. The driver 123 of the present invention detects whether the terminal device 140 sends an interrupt request 320. If the terminal device 140 issues an interrupt request 320, the driver 123 will store the interrupt request 320 in the corresponding cache structure 124. Subsequently, the driver 123 moves to the next terminal device 140 and detects whether an interrupt request 320 is issued. After the driver 123 completes the detection of all the communication interfaces 135, the driver 123 will send a completion notification 330 to the service program 122 to notify the service program 122 to start detection.

When the service program 122 receives the completion notification 330, the service program 122 will sequentially detect whether there is an interrupt request 320 in the cache structure 124. The service program 122 sequentially detects the cache structure 124 according to the sequence of the transmission channel 310. While the service program 122 detects the cache structure 124, the driver program 123 will detect the interrupt request 320 of each terminal device 140 in the next round. For the access request, when the driver detects the access request sent by the transmission channel 123, the service program 122 is called to execute the access request.

In order to clearly illustrate the process of detecting and processing the interrupt request 320 of the service program 122 and the driver 123 of the present invention, four polling detection and processing of the terminal device 140 are used as an illustration, but it is not limited to this number. Please cooperate with FIG. 3A to FIG. 3E, which are schematic diagrams of the detection sequence and time processing of the interrupt request 320 of the present invention. In the illustrative example of this embodiment, the PCIE riser card 130 is connected to the first device 411, the second device 412, the third device 413, and the fourth device 414, respectively. The first device 411 corresponds to the first channel 421, the second device 412 corresponds to the second channel 422, the third device 413 corresponds to the third channel 423, and the fourth device 414 corresponds to the fourth channel 424. The first channel 421, the second channel 422, the third channel 423, and the fourth channel 424 respectively map the first buffer 431, the second buffer 432, the third buffer 433, and the fourth buffer 434, as shown in FIG. 3A.

First, the driver 123 will poll by the first device 411, the second device 412, the third device 413 to the fourth device 414 and monitor whether an interrupt request 320 is issued. Here, the driver 123 monitors each terminal device 140 at the first time, the second time, the third time, and the fourth time respectively, and it is assumed that the first device 411, the third device 413, and the fourth device 414 issue interrupts in sequence Requirements 320. Therefore, the driver 123 stores each interrupt request 320 into the corresponding cache structure 124, as shown in FIG. 3B. When the driver 123 completes the polling of the first device 411, the second device 412, the third device 413 to the fourth device 414, the driver 123 will The detection of the interrupt request 320 of this round will be ended, and a completion notification 330 will be sent to the service program 122 at the same time. The driver 123 will start the detection of each interrupt request 320 in the next round.

Then, the service program 122 starts to detect whether there is an interrupt request 320 for the first cache 431, the second cache 432, the third cache 433, and the fourth cache 434 one by one, as shown in FIG. 3C. In Figure 3C, the service program 122 dumps the interrupt request 320 into each cache structure 124. The driver 123 then processes the cache structure 124 and the interrupt request 320 in sequence. In the process of processing the interrupt request 320, the service program 122 can suspend the detection of the interrupt request 320 and wait for the driver 123 to complete all the interrupt requests 320. The service program 122 can also detect the interrupt request 320 in the next round. If the service program 122 performs the next round of interrupt detection, the driver 123 can store the outstanding interrupt request 320 in each cache structure 124 in a queue, as shown in FIG. 3D.

In Figure 3D, the third device 413 issues a new interrupt request 320 in the next round. Assuming that the driver 123 is still processing the interrupt request 320 of the fourth cache 434, the service program 122 will still forward the new interrupt request 320 to the third cache 433. Assuming that after multiple rounds and the cache structure 124 fails to complete the interrupt request 320, the interrupt request 320 will be stored in the cache structure 124 in a queue, as shown in FIG. 3E. Due to the parallel processing of the service program 122 and the driver program 123, the polling of heterogeneous devices by the PCIE transfer card will not be blocked by the single terminal device 140.

The interrupt processing system and method for heterogeneous equipment applied to PCIE of the present invention is applied to the relevant control of various heterogeneous equipment by a high-speed transmission interface. Since the driver 123 and the service program 122 of the present invention process their respective processes, the service program 122 does not need to wait for the completion of the interrupt request 320 before executing the next interrupt request 320. In this way, the driver 123 can always detect the interrupt request 320, and the service program 122 can handle the interrupt request 320 full-time. When the developer changes the content of the service program 122, the developer does not need to re-verify the driver program 123. Therefore, the present invention not only improves the interrupt processing efficiency of the terminal device 140, but also reduces the verification cost of sending the driver 123 for verification every time the version is revised.

Although the present invention is disclosed in the foregoing preferred embodiments as above, it is not intended to limit the present invention. Anyone familiar with similar art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of patent protection for inventions is subject to the Those defined in the scope of the patent application shall prevail.

100‧‧‧Interrupt handling system

110‧‧‧Processing unit

120‧‧‧Storage Unit

121‧‧‧Operating System

122‧‧‧Service Program

123‧‧‧Driver

124‧‧‧Cache structure

130‧‧‧PCIE riser card

131‧‧‧Control Unit

132‧‧‧Memory Unit

133‧‧‧PCIE pin

135‧‧‧Communication interface

136‧‧‧Identification information

140‧‧‧Terminal equipment

Claims (10)

An interrupt processing system applied to PCIE to heterogeneous equipment, which provides a variety of interface combinations and reduces the waiting time of each interface interrupt. The interrupt processing system applied to PCIE to heterogeneous equipment includes: a PCIE adapter card, It has a control unit, an identification information and at least one communication interface, and the control unit is electrically connected to the communication interfaces; a storage unit has a service program, a driver program and a plurality of cache structures, each The cache structure is used to store an interrupt request; a processing unit, which is electrically connected to the PCIE adapter card and the storage unit, the processing unit executes the driver and the service program, and the driver establishes according to the identification information Multiple transmission channels, and the driver assigns different transmission channels to the corresponding communication interface, and the transmission channel is used to transmit the interrupt request or an access request; wherein, if the driver detects any of the transmission The channel transmits the interrupt request, and the driver stores the interrupt request in the cache structure. If the interrupt request exists in the cache structure, the service program handles the interrupt request. The interrupt processing system applied to PCIE to heterogeneous devices as described in claim 1, wherein the type of the communication interface is a serial port (Communication port), an analog input/output port (Analog I/O port), or a digital input/output port ( Digital I/O port). As described in claim 1, the PCIE interrupt processing system for heterogeneous devices is applied, wherein the cache structure is implemented by a queue, a stack, or an array. The PCIE interrupt processing system for heterogeneous devices as described in claim 1, wherein the types of the access request are event, command, or data. The interrupt processing system applied to PCIE to heterogeneous devices as described in claim 1, wherein the driver and the service program operate at the same time, and the driver stores the interrupt request in the cache structure and then the service program handles it The interrupt request. The interrupt processing system applied to PCIE for heterogeneous devices as described in claim 1, wherein the driver program polls all the transmission channels and then the service program processes the interrupt requests. An interrupt processing method applied to PCIE to heterogeneous equipment, which provides a variety of different types of interface combinations and reduces the interrupt waiting time of various interfaces. The interrupt processing method applied to PCIE to heterogeneous equipment includes: Run a driver program and a service program in an operating system; initialize a PCIE adapter card so that the service program drives the PCIE adapter card's multiple communication interfaces to be mapped to multiple transmission channels in the operating system; The driver polls and monitors the transmission channels, and receives an interrupt request or an access request sent by the transmission channel; when the driver detects that the interrupt request is sent, the driver saves the interrupt request to A cache structure; and if the interrupt request exists in the cache structure, the service program handles the interrupt request. The interrupt processing method applied to PCIE to heterogeneous devices as described in claim 7, wherein the step of initializing the PCIE riser card further includes: the operating system sets the transmission channels according to an identification information of the PCIE riser card The corresponding quantity. The PCIE interrupt handling method for heterogeneous devices as described in claim 7, wherein the driver monitoring the transmission channels further includes: when the driver detects the access request issued by the transmission channels, calling the service The program executes the access request. As described in claim 7, the PCIE interrupt handling method for heterogeneous devices is applied, wherein the types of the access request are event, command, or data.

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