TW202201955A - Signal transmission device capable of transmitting multiple data streams - Google Patents

Abstract

A signal transmission device is provided. The connection port includes a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. The first positive differential pin of the plurality of positive differential pins transmits the positive signal component of the first differential signal. The second positive differential pin of the plurality of positive differential pins transmits the positive signal component of the second differential signal. The first negative differential pin of the plurality of negative differential pins transmits the negative signal component of the first differential signal. The second negative differential pin of the plurality of negative differential pins transmits the negative signal component of the second differential signal. The first positive differential pin and the first negative differential pin are located on one side of the first ground pin of the plurality of ground pins, the second positive differential pin and the second negative differential pin are located on the other side of the first ground pin.

Description

Signal transmission device capable of transmitting complex data streams

The present invention relates to a signal transmission device capable of transmitting complex data streams.

With the higher and higher requirements for the quality of video playback images, the resolution from the original 4K to 8K is upgraded from the player that is the signal source (Signal Source) to the monitor that is the signal sink (Signal Sink), etc. The amount of data transfer required also increases. Moreover, due to the rise of home theaters, it is often necessary to use longer transmission lines to connect the signal generating source and the signal receiving end to meet the needs of various living room arrangements.

In the current signal transmission device specification, considering the definition of the pin position, the ground shielding (Ground Shielding) that attaches importance to differential signals is not the best planning method, which makes the signal quality when transmitting high-speed signals vulnerable. The effects of crosstalk and delay make it difficult to transmit over longer distances.

In some embodiments, a signal transmission device includes a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. The first positive differential pin of the plurality of positive differential pins is used to transmit the positive signal component of the first differential signal, and the second positive differential pin of the plurality of positive differential pins is used to transmit the second differential signal The positive signal component of the signal; the first negative differential pin of the plurality of negative differential pins is used to transmit the negative signal component of the first differential signal, and the second negative differential pin of the plurality of negative differential pins is used to transmit the negative signal component of the first differential signal. to transmit the negative signal component of the second differential signal; wherein, the first positive differential pin and the first negative differential pin are located on one side of the first ground pin among the plurality of ground pins, and the second positive differential pin The pin and the second negative differential pin are located on the other side of the first ground pin.

Please refer to FIG. 1 , which is a schematic diagram of an embodiment of a signal transmission device according to the present application. The signal transmission device includes a plurality of positive differential pins (Pin), a plurality of negative differential pins, a plurality of control signal pins, a plurality of power signal pins and a plurality of ground pins. Among them, the number of positive differential pins, the number of negative differential pins, the number of ground pins, the number of power signal pins and the number of control signal pins can be based on different product requirements (such as the required current, signal transmission rate) for customized design, FIG. 1 is only an example of one embodiment of the signal transmission device, and this case is not limited to this.

FIG. 1 illustrates a plurality of positive differential pins 111, 121, 131, 141, a plurality of negative differential pins 112, 122, 132, 142 and the corresponding differential pins 111, 112, 121, 122, 131, 132, Plural ground pins (GND) 21-25 of 141 and 142. The positive differential pins 111, 121, 131, 141 and the negative differential pins 112, 122, 132, and 142 respectively transmit the positive signal component and the negative signal component of the differential signal. 121 (respectively referred to as the first positive differential pin 111 and the second positive differential pin 121 for the convenience of description), the negative differential pins 112 and 122 (respectively referred to as the first negative differential pin 112 and the second positive differential pin 121) The two negative differential pins 122 ) and the corresponding ground pins 21 (hereinafter referred to as the first ground pins 21 ) are described as an example.

The first positive differential pin 111 and the first negative differential pin 112 transmit the first differential signal, wherein the first positive differential pin 111 transmits the positive signal component of the first differential signal, and the first negative differential signal The pin 112 transmits the negative signal component of the first differential signal; the second positive differential pin 121 and the second negative differential pin 122 transmit another differential signal different from the first differential signal (hereinafter referred to as the The second differential signal), the second positive differential pin 121 transmits the positive signal component of the second differential signal, and the second negative differential pin 122 transmits the negative signal component of the second differential signal. In terms of configuration, the first positive differential pin 111 and the first negative differential pin 112 are located on one side of the first ground pin 21 (that is, the two differential pins 111 and 112 transmitting the same differential signal are located on one side of the first ground pin 21 ). On the same side of the first ground pin 21 ), the second positive differential pin 121 and the second negative differential pin 122 are located on the other side of the first ground pin 21 (ie, two differential pins that transmit the same differential signal) The moving pins 121 and 122 are located on the same side of the first ground pin 21 ), that is, the two differential pins 111 and 122 that transmit different differential signals are located on different sides of the first ground pin 21 .

Furthermore, FIG. 1 illustrates four power signal pins 31-34 and a plurality of control signal pins. The power signal pins 31-34 can transmit power signals conforming to specific communication specifications, and the control signal pins can transmit control signals conforming to specific communication specifications. The operating power signal and control signal conform to specific communication specifications. Based on this, different from the conventional signal transmission device, the signal transmission device of the present application can avoid crosstalk between different differential signals when transmitting the first differential signal and the second differential signal, and achieve better results. Therefore, the transmission quality of the signal transmission device is improved, and the signal can be transmitted to the electronic device more efficiently.

In some embodiments, as shown in FIG. 1 , the signal transmission device can transmit at least four pairs of differential signals, the third positive differential pin 131 and the third negative differential pin 132 can transmit the third differential signal, the first differential signal The three positive differential pins 131 transmit the positive signal component of the third differential signal, the third negative differential pin 132 transmits the negative signal component of the third differential signal, the fourth positive differential pin 141 and the fourth negative differential The dynamic pin 142 can transmit the fourth differential signal, the fourth positive differential pin 141 transmits the positive signal component of the fourth differential signal, and the fourth negative differential pin 142 transmits the negative signal component of the fourth differential signal. In order to prevent the aforementioned four pairs of differential signals from interfering with each other, as shown in FIG. 1 , the plurality of ground pins of the signal transmission device are a first ground pin 21 , a second ground pin 22 and a third ground pin 23 , the fourth ground pin 24 and the fifth ground pin 25 . The second positive differential pin 121 and the second negative differential pin 122 are located between the first ground pin 21 and the fourth ground pin 24 , namely the second positive differential pin 121 and the second negative differential pin The pin 122 is located on one side of the fourth ground pin 24, the third positive differential pin 131 and the third negative differential pin 132 are located on the other side of the fourth ground pin 24; the third positive differential pin 131 and the third negative differential pin 132 is located between the fourth ground pin 24 and the fifth ground pin 25, that is, the third positive differential pin 131 and the third negative differential pin 132 are located on the fifth ground pin On one side of 25 , the fourth positive differential pin 141 and the fourth negative differential pin 142 are located on the other side of the fifth ground pin 25 . Based on this, the second positive differential pin 121 and the third negative differential pin 132 are shielded by the fourth ground pin 24 , and the space between the third positive differential pin 131 and the fourth negative differential pin 142 is shielded by the fourth ground pin 24 . Shielded by the fifth ground pin 25, the first differential signal, the second differential signal, the third differential signal and the fourth differential signal do not interfere with each other.

In some embodiments, the plurality of positive differential pins 111 , 121 , 131 , 141 and the plurality of negative differential pins 112 , 122 , 132 , and 142 are along the same linear direction D1 (eg, the length direction of the signal transmission device) Arrangement, the signal transmission device can be more easily compatible with the existing communication transmission specifications.

In some embodiments, please refer to FIG. 2 , which is a schematic diagram of another embodiment of the signal transmission device of FIG. 1 . The signal transmission device may also include eight pairs of differential pins, each of which transmits the same differential signal. The differential pins are shielded by two ground pins. The signal transmission device further includes positive differential pins 171, 181, 191, 101 (hereinafter referred to as the seventh positive differential pin 171, the eighth positive differential pin 181, the ninth positive differential pin 191 and the first Ten positive differential pins 101), negative differential pins 172, 182, 192, 102 (hereinafter referred to as the seventh negative differential pin 172, the eighth negative differential pin 182, the ninth negative differential pin pin 192 and the tenth negative differential pin 102) and the corresponding ground pins 26, 27, 28, 29. The positive differential pins 171 , 181 , 191 , and 101 and the negative differential pins 172 , 182 , 192 and 102 are also arranged along the same linear direction D1 . The seventh positive differential pin 171 and the seventh negative differential pin 172 can transmit the seventh differential signal, the seventh positive differential pin 171 transmits the positive signal component of the seventh differential signal, and the seventh negative differential connection The pin 172 transmits the negative signal component of the seventh differential signal. The eighth positive differential pin 181 and the eighth negative differential pin 182 can transmit the eighth differential signal, the eighth positive differential pin 181 transmits the positive signal component of the eighth differential signal, and the eighth negative differential pin The pin 182 transmits the negative signal component of the eighth differential signal. The ninth positive differential pin 191 and the ninth negative differential pin 192 can transmit the ninth differential signal, the ninth positive differential pin 191 transmits the positive signal component of the ninth differential signal, and the ninth negative differential connection The pin 192 transmits the negative signal component of the ninth differential signal. The tenth positive differential pin 101 and the tenth negative differential pin 102 can transmit the tenth differential signal, the tenth positive differential pin 101 transmits the positive signal component of the tenth differential signal, and the tenth negative differential connection The pin 102 transmits the negative signal component of the tenth differential signal.

In order to prevent the aforementioned eight differential signals from interfering with each other, as shown in FIG. 2 , the fourth positive differential pin 141 and the fourth negative differential pin 142 are located at the fifth grounding pin 25 and the sixth grounding pin. Between the pins 26, namely the fourth positive differential pin 141 and the fourth negative differential pin 142 are located on one side of the sixth ground pin 26, the seventh positive differential pin 171 and the seventh negative differential pin 172 is located on the other side of the sixth ground pin 26; the seventh positive differential pin 171 and the seventh negative differential pin 172 are located between the sixth ground pin 26 and the seventh ground pin 27, namely the seventh The positive differential pin 171 and the seventh negative differential pin 172 are located on one side of the seventh ground pin 27 , and the eighth positive differential pin 181 and the eighth negative differential pin 182 are located on the seventh ground pin 27 The other side; the eighth positive differential pin 181 and the eighth negative differential pin 182 are located between the seventh ground pin 27 and the eighth ground pin 28, namely the eighth positive differential pin 181 and the eighth ground pin 28. The eight negative differential pins 182 are located on one side of the eighth ground pin 28, the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on the other side of the eighth ground pin 28; The differential pin 191 and the ninth negative differential pin 192 are located between the eighth ground pin 28 and the ninth ground pin 29, that is, the ninth positive differential pin 191 and the ninth negative differential pin 192 are located between the eighth ground pin 28 and the ninth ground pin 29. On one side of the ninth ground pin 29 , the tenth positive differential pin 101 and the tenth negative differential pin 102 are located on the other side of the ninth ground pin 29 . Based on this, the fourth positive differential pin 141 and the seventh negative differential pin 172 are shielded by the sixth ground pin 26 , and between the seventh positive differential pin 171 and the eighth negative differential pin 182 Shielded by the seventh ground pin 27, the eighth positive differential pin 181 and the ninth negative differential pin 192 are shielded by the eighth ground pin 28, the ninth positive differential pin 191 and the tenth negative differential The ninth grounding pin 29 is shielded between the moving pins 102, the first differential signal, the second differential signal, the third differential signal, the fourth differential signal, the seventh differential signal, and the eighth differential signal , The ninth differential signal and the tenth differential signal do not interfere with each other. Based on this, the signal transmission device can transmit at least eight pairs of differential signals, and the eight pairs of differential pins are arranged along the same linear direction D1, and the signal transmission device can be more easily compatible with the existing communication transmission specifications.

In some embodiments, as shown in FIG. 1 and FIG. 2 , one side of the third ground pin 23 among the plurality of ground pins (ie, the side away from the first negative differential pin 112 ) is not provided with The positive differential pin and the negative differential pin can be provided with power signal pins 31 and 32, and the other side of the third ground pin 23 is the first positive differential pin 111 and the first negative differential pin The pins 112 , namely the first positive differential pin 111 and the first negative differential pin 112 are located between the first ground pin 21 and the third ground pin 23 , the first positive differential pin 111 and the first The negative differential pin 112 is shielded by the two ground pins 21 and 23 , and the ground pins 21 and 23 can jointly provide the grounding of the first differential signal. Based on this, the setting of the third grounding pin 23 separates the first positive differential pin 111 and the first negative differential pin 112 from the plurality of power signal pins 31 and 32, so as to prevent the first positive differential pin 111 and the first negative differential pin 112 are interfered by the power signal when transmitting the first differential signal, which causes the transmission quality of the first differential signal to decrease.

In some embodiments, as shown in FIG. 2 , the second ground pin 22 is located at the most edge position of the signal transmission device, that is, one side of the second ground pin 22 in the linear direction D1 is not set with positive difference The other side of the second grounding pin 22 in the linear direction D1 is the tenth positive differential pin 101 and the tenth negative differential pin 102 . That is, the tenth positive differential pin 101 and the tenth negative differential pin 102 are located between the ninth ground pin 29 and the second ground pin 22, and the tenth positive differential pin 101 and the tenth negative differential pin are located between the ninth ground pin 29 and the second ground pin 22. The pin 102 is shielded by the two ground pins 29 and 22 , that is, the ground pins 29 and 22 can jointly provide the tenth differential signal grounding. Based on this, the tenth positive differential pin 101 and the tenth negative differential pin 102 can be further prevented from being interfered by the noise outside the signal transmission device when the tenth differential signal is transmitted, which will lead to the transmission quality of the tenth differential signal. falling situation.

In some embodiments, as shown in FIG. 2 , the plurality of differential pins of the signal transmission device also include two positive differential pins 151 , 161 and two negative differential pins 152 , 162 (hereinafter, the positive differential pins will be The moving pins 151 and 161 are respectively referred to as the first positive and differential high-speed pins 151 and the second positive and differential high-speed pins 161, and the negative differential pins 152 and 162 are respectively referred to as the first negative differential high-speed pins. 152 and the second negative differential high-speed pin 162 ), and the plurality of ground pins of the signal transmission device also include a tenth ground pin 20 . The first positive differential high-speed pin 151 is used to transmit the positive signal component of the fifth differential signal, the first negative differential high-speed pin 152 is used to transmit the negative signal component of the fifth differential signal; The pin 161 is used for transmitting the positive signal component of the sixth differential signal, and the second negative differential high-speed pin 162 is used for transmitting the negative signal component of the sixth differential signal. In terms of configuration, the first positive differential high-speed pin 151 and the first negative differential high-speed pin 152 are located on one side of the tenth ground pin 20 , the second positive differential high-speed pin 161 and the second negative differential high-speed pin 161 The pin 162 is located on the other side of the tenth ground pin 20 . The positive differential high-speed pins 151 and 161 , the tenth ground pin 20 and the negative differential high-speed pins 152 and 162 are arranged along the same linear direction D1 .

In some embodiments, the plurality of positive differential pins and the plurality of negative differential pins of the signal transmission device are used to transmit high-speed signals. For example, the differential pins 111 and 112 transmit the first differential signal and the differential pin 121 . , 122 transmits the second differential signal, differential pins 131, 132 transmits the third differential signal, differential pins 141, 142 transmits the fourth differential signal, differential pins 171, 172 transmits the first differential signal Seven differential signals, eighth differential signal transmitted by differential pins 181, 182, ninth differential signal transmitted by differential pins 191, 192, tenth differential signal transmitted by differential pins 101, 102, The fifth differential signal transmitted by the differential high-speed pins 151 and 152 and the sixth differential signal transmitted by the differential high-speed pins 161 and 162 are both high-speed signals. Moreover, as shown in FIG. 1 and FIG. 2 , the signal transmission device may further include a positive differential low-speed pin 51 and a negative differential low-speed pin 52 for transmitting low-speed data signals, and the positive differential low-speed pin 51 and the negative differential low-speed pin 51 The low-speed pins 52 and the differential high-speed pins 151 , 152 , 161 , and 162 are arranged along the same linear direction D1 . The positive differential low-speed pin 51 and the negative differential low-speed pin 52 transmit the low-speed differential signal of low-speed data, the positive differential low-speed pin 51 transmits the positive signal component of the low-speed differential signal, and the negative differential low-speed pin 52 transmits the low-speed differential signal. Negative signal component of the low speed differential signal. Based on this, the signal transmission device can simultaneously support the transmission of high-speed signals and low-speed data signals.

In some embodiments, the signal transmission device shown in FIGS. 1 to 2 can support the Universal Serial Bus (USB) 2.0 specification, and the positive differential low-speed pins 51 and the negative differential low-speed pins 52 are suitable for According to the USB2.0 specification, the low-speed differential signals transmitted by the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are USB2.0 USB signals. The positive differential low-speed pin 51 can transmit USB-DP signals, and the negative differential low-speed pin 51 The differential low-speed pins 52 can transmit USB-DM signals. Furthermore, the signal transmission device shown in FIG. 2 can also support various specifications using differential transmission methods. In the signal transmission device, there are a plurality of positive differential pins for transmitting high-speed Any two of pins 111, 112, 121, 122, 131, 132, 141, 142, 171, 172, 181, 182, 191, 192, 101, 102 and differential high-speed pins 151, 152, 161, 162) For differential pins, it can transmit high-speed data transmission and reception signals that conform to USB 2.0 or PCIe 1.0 and later versions, or other high-speed data transmission and reception methods using differential transmission.

In some embodiments, the signal transmission device shown in FIG. 1 to FIG. 2 can also support PCIe interface specifications, wherein the positive differential low-speed pin 51 , the negative differential low-speed pin 52 , and the first positive differential high-speed pin 151. The first negative differential high-speed pin 152, the second positive differential high-speed pin 161 and the second negative differential high-speed pin 162 are also suitable for PCIe interface transmission, and the positive differential low-speed pin 51, the negative The differential low-speed pin 52 can transmit a clock signal (which may include a positive clock component and a negative clock component) conforming to the PCIe interface specification.

In some embodiments, the signal transmission device can support High Definition Multimedia Interface (HDMI), as shown in FIG. 1 and FIG. 2 , the plurality of control signal pins may be a plurality of SCL pins, a plurality of SDA pins The pin and the hot plug detection (Hot Plug Detection) pin 411 or a combination formed from the aforementioned items. The plurality of SCL pins are the SCL/PCIE_WAKE_N pins 414 and REALONE_SCL pins 419 for transmitting SCL (Serial Clock) signals; the plurality of SDA pins are the SDA/PCIE_PERST_N pins 412 for transmitting SDA (Serial Data) signals and REALONE_SDA pin 420. The SCL pin and the SDA pin can be used for the communication between the signal generating source (such as Digital Video Disc, or DVD) device and the signal receiving end (such as television, or TV) device. The source device reads through the SCL pin and the SDA pin. Select the resolution supported by the playback device, so that the source device displays an image screen that matches the resolution of the playback device. In addition, four pairs of positive differential pins 111, 121, 131, 141, 171, 181, 191, and 101 and negative differential pins 112, 122, 132, 142, 172, 182, 192, and 102 are differentially connected. The pins can transmit a total of three pairs of Transition Minimized Differential Signaling (TMDS) and a pair of clock signals suitable for HDMI specifications to support the transmission of HDMI signals.

In some embodiments, the plurality of control signal pins of the signal transmission device can be iRealOne_LINK pin 415, CLK (AUDIO-SYNC clock) pin 413, a plurality of pins suitable for serial peripheral interface (SPI) or selected from the aforementioned items The formed combination is used to transmit voice and video related control signals between electronic devices, wherein the plurality of pins suitable for SPI include SPI_DI pin 416, SPI_CS pin 417, SPI_WP_PWM pin 421, SPI_DO pin 423, SPI_HOLD_PWM Pin 422 and SPI_CLK pin 418.

In some embodiments, one of the plurality of control signal pins of the signal transmission device may be the system main power enable pin 410 , and the system main power enable pin 410 is used to transmit whether the external device provides power or not. A control signal (or an enabling signal), for example, a signal transmission device can be connected between a notebook computer and a tablet computer, the tablet computer can be regarded as an external device for the notebook computer, and the tablet computer has the ability to supply power to the notebook computer For the power supply function of the computer, the system main power enable pin 410 can transmit a control signal for enabling or disabling the aforementioned power supply function. In terms of configuration, the system main power enable pin 410 is located at the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the first The two positive differential high-speed pins 161 and the second negative differential high-speed pins 162 are used to isolate the transmission of low-speed data signals and high-speed signals. In some embodiments, the aforementioned plurality of control signal pins are arranged along the same linear direction D1.

In some embodiments, the power signal pins 31-34 can be a plurality of low-voltage power pins and a plurality of high-voltage power pins, wherein, the power signal pins 31 and 32 are low-voltage power pins, namely HV-POWER power pins, The power signal pins 31 and 32 supply low-voltage power signals related to HV, and the voltage can be 12 volts (V). The power signal pins 33 and 34 are high-voltage power pins, namely UHV-POWER Pins 33 and 34 supply high-voltage power signals related to UHV, and the voltage can be 350V. In some embodiments, the number of the plurality of low-voltage power pins and the number of the plurality of high-voltage power pins can be adjusted according to the actual on-current of the signal transmission device and the differential signal transmission rate.

In some embodiments, as shown in FIG. 1 and FIG. 2 , the plurality of ground pins of the signal transmission device can provide power signal grounding, that is, the high voltage ground pins 61 and 62 of the plurality of ground pins can be provided as high voltage The power signal pins 33 and 34 of the power pins are used for grounding. The aforementioned power signal pins 33 and 34 and the high voltage ground pins 61 and 62 are arranged along the same straight line direction D1. Furthermore, the signal transmission device further includes an insulating layer I, and the insulating layer I is located between the power signal pins 33, 34 and the high voltage ground pins 61, 62 of the plurality of ground pins for the power supply signal pins 33, 34 to be grounded. That is to say, the power signal pins 33 and 34 which are UHV-POWER pins are located on one side of the insulating layer I, and the high-voltage grounding pins 61 and 62 are located on the other side of the insulating layer I. Therefore, disposing the insulating layer I between the power signal pins 33, 34 and the high-voltage ground pins 61, 62 can prevent arcing or damage to the signal transmission device due to excessive voltage. In this embodiment, the insulating layer I is in the form of pins.

In some embodiments, please refer to FIG. 1 and FIG. 2 , the signal transmission device is provided with a metal isolation layer M as the isolation between the electrical structure and the physical structure (between a plurality of pins of the signal transmission device). In detail, as shown in FIG. 1 and FIG. 2 , the power signal pins 31 , 32 , the positive differential pins 111 , 121 , 131 , 141 , 171 , 181 , 191 , 101 and the negative differential pins 112 , 122 , 132, 142, 172, 182, 192, 102 and ground pins 21, 22, 23, 24, 25, 26, 27, 28, 29 are located on one side of the metal isolation layer M in the direction D2; positive differential low speed Pin 51, Negative Differential Low Speed Pin 52, First Positive Differential High Speed Pin 151, First Negative Differential High Speed Pin 152, Tenth Ground Pin 20, Second Positive Differential High Speed Pin 161, The two negative differential high-speed pins 162, the plurality of control signal pins, the power signal pins 33, 34, the high-voltage ground pins 61, the high-voltage ground pins 62 and the insulating layer I are located on the other side of the metal isolation layer M in the direction D2 side, and the direction D2 is perpendicular to the direction D1 (for example, the direction D2 can be the length direction of the signal transmission device), in other words, the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential The pins 112, 122, 132, 142, 172, 182, 192, 102, the positive differential low-speed pins 51 and the negative differential low-speed pins 52 are arranged in parallel along the direction D2 through the metal isolation layer M; Positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 and first positive differential high-speed pins 151. The first negative differential high-speed pin 152, the second positive differential high-speed pin 161, and the second negative differential high-speed pin 162 are arranged side by side along the direction D2 through the metal isolation layer M; the positive difference The dynamic pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 and the plural control signal pins are connected by The metal isolation layers M are arranged in parallel along the direction D2; the power signal pins 31, 32 and the power signal pins 33, 34 are arranged in parallel along the direction D2 through the metal isolation layer M. In some embodiments, the metal isolation layer M can be an iron sheet, and can provide signal grounding. Based on this, the metal isolation layer M can prevent the pins on both sides from interfering with each other, and provide a good reference ground plane to enhance the signal quality and impedance matching characteristics. The double row of parallel pins can also reduce the size of the signal transmission device. And improve the convenience of production.

In some embodiments, please refer to FIG. 1 , FIG. 2 and FIG. 3 , all the pins of the signal transmission device can be formed by winding a core wire, and their arrangement can be arranged in the same linear direction. For example, as shown in FIG. 3 , the wire G1 can be a twisted pair with a grounding pin as a shield, the wire G2 can be a twisted pair without a grounding pin as a shield, and the wire G3 can be a thin single-core wire and a wire G4 can be a thick single-core wire, and all the pins of the signal transmission device can be bundled into wire G1, wire G2, wire G3, and wire G4 respectively and arranged in the same straight direction. In other embodiments, as shown in FIG. 4 , the wires G1-G4 can also be a bundle of wires wrapped in a ring shape, that is, the wires G1, G2, G3, and G4 may not be arranged in the same straight line direction.

In some embodiments, the signal transmission device includes a housing. The signal transmission device can be designed as one of a male connector or a female connector. The male connector and the female connector correspond to each other, and the signal transmission device as the male connector and the signal transmission device as the female connector can be connected. Please refer to FIGS. 5A to 5D. FIGS. 5A and 5B are embodiments of a female connector and a male connector, respectively. FIG. 5C is a schematic side view of one side SA of the signal transmission device in FIG. 5A, and FIG. 5D is the signal transmission in FIG. 5B. A schematic side view of one side SB of the device. As shown in FIG. 5C and FIG. 5D , the ends A and A' are designed as chamfered corners, and the ends B and B' are also designed as chamfered corners. Therefore, the two signal transmission devices, which are the female connector and the male connector respectively, can be designed according to the The A end is connected to the A' end and the B end is connected to the B' end, and the chamfered angle can be used as a foolproof mechanism to prevent the wrong connection between the male connector and the female connector. In other embodiments, the casing includes a chamfered corner and a right angle, and the chamfered corner and the right angle are located on two sides of the casing, respectively. Please refer to FIGS. 6A and 6B. FIG. 6A is another schematic view of the signal transmission device as a female connector, and FIG. 6B is another schematic view of the signal transmission device as a male connector. As shown in FIG. 6A and FIG. 6B , the C end and the C' end are designed as right angles, and the D end and D' end are designed as chamfered angles. Therefore, the two signal transmission devices, which are the female connector and the male connector respectively, can be paired according to the C end. The C' end and the D end are connected to the D' end. In other embodiments, please refer to FIGS. 7A and 7B , FIG. 7A is another schematic diagram of the signal transmission device as a female connector, and FIG. 7B is another schematic view of the signal transmission device as a male connector. As shown in FIG. 7A and FIG. 7B , the E and E' ends are designed as chamfered angles, and the F and F' ends are designed as right angles. Therefore, the two signal transmission devices, which are the female connector and the male connector, can be paired according to the E end. The E' end and the F end are connected to each other with respect to the F' end. Based on this, the signal transmission device can provide a combination of signal transmission devices on different products and separate the signal transmission device connectors according to the different chamfered angles of the connectors, so as to prevent the possibility of misconnection between the male connector and the female connector.

In some embodiments, please refer to FIG. 8A to FIG. 8E , FIG. 8A and FIG. 8B are the appearance schematic view and side view of the female connector, respectively, FIG. 8C and FIG. 8D are the appearance schematic view and side view of the male connector, respectively, and FIG. 8E is the corresponding FIG. 8A and FIG. 8B are schematic appearance diagrams of one embodiment of the female connector of FIGS. 8A and 8B butted against the male connector of FIGS. 8C and 8D . As shown in FIG. 8A and FIG. 8B , the female connector includes a housing O1, a tongue O2, an accommodating space O3 surrounded by the housing, and a plurality of pins, and the tongue O2 is arranged in the accommodating space O3, and the tongue Part O2 is an insulating material. In some embodiments, a metal isolation layer M is embedded in the tongue portion O2. Therefore, the tongue portion O2 can be provided with pins, when the metal isolation layer M is connected to a fixed potential (eg, ground potential), the metal isolation layer M It can be used for electrical isolation of signals on the upper and lower surfaces of the tongue O2, and as a reference ground for high-speed signals. The female connector is arranged on the substrate Z which is the circuit board. The plurality of pins are the above-mentioned differential pins 111, 121, 131, 141, 171, 181, 191, 101, 51, 151, 161, 112, 122, 132, 142, 172, 182, 192, 102 , 52, 152, 162, ground pins 20-29, 61-62, power signal pins 31-34, control signal pins 410-423, the pins and the insulating layer I are arranged on the tongue O2, and Arranged on the upper and lower surfaces of the tongue O2, for example, power signal pins 31, 32, positive differential pins 111, 121, 131, 141, 171, 181, 191, 101 and negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 and ground pins 21, 22, 23, 24, 25, 26, 27, 28, 29 can be located on the upper surface of the tongue O2, and the positive differential low speed Pin 51, Negative Differential Low Speed Pin 52, First Positive Differential High Speed Pin 151, First Negative Differential High Speed Pin 152, Tenth Ground Pin 20, Second Positive Differential High Speed Pin 161, The two negative differential high-speed pins 162, a plurality of control signal pins, power signal pins 33, 34, high voltage ground pins 61, high voltage ground pins 62 and the insulating layer I may be located on the lower surface of the tongue O2. In addition, the metal isolation layer M is also located on the tongue portion O2, and the metal isolation layer M is located between the upper surface and the lower surface of the tongue portion O2. In another example, the aforementioned pins arranged on the upper surface of the tongue portion O2 can also be arranged on the lower surface, and the aforementioned pins arranged on the lower surface can be arranged on the upper surface.

In some embodiments, the housing O1 includes a protruding portion O11, and the protruding portion O11 is located on a surface of the housing O1. For example, as shown in FIG. 8A and FIG. 8B, the protruding portion O11 may be located on the housing O1 surface. The protruding portion O11 includes a pair of side walls Oa, Ob, and a top wall Oc, the side walls Oa, Ob are respectively connected to the housing O1, and the top wall Oc is connected between the side walls Oa, Ob, whereby the side walls Oa, Ob, the top wall The Oc together form the insertion space O4 of the female connector, and the insertion space O4 and the accommodating space O3 communicate with each other.

In some embodiments, the casing O1 includes a plurality of snap buttons O12, wherein the number of snap buttons O12 can be adjusted, and the snap buttons O12 are located on at least one surface of the casing. For example, as shown in FIG. 8A and FIG. 8B , the snap buttons O12 The number is two, and the snap button O12 can be located on the upper surface of the housing O1, that is, on the same surface as the protruding portion O11. In other embodiments, the casing O1 includes a plurality of button holes O13, wherein the number of button holes O13 can be adjusted, and the button holes O13 are located on at least one surface of the casing. As shown in FIG. 8A and FIG. 8B , the button holes O13 The number is two, and the button hole O13 can be located on the upper surface of the housing O1, that is, on the same surface as the protruding portion O11 and the elastic buckle O12.

In some embodiments, as shown in FIG. 8C and FIG. 8D, the male connector includes a housing K1, an insulator T inside the housing K1, an accommodating space K2 surrounded by the insulator T, and a plurality of pins , the pins are arranged on the insulator T. The plurality of pins are the above-mentioned differential pins 111, 121, 131, 141, 171, 181, 191, 101, 51, 151, 161, 112, 122, 132, 142, 172, 182, 192, 102 , 52, 152, 162, ground pins 20-29, 61-62, power signal pins 31-34, control signal pins 410-423, the pins and the insulating layer I are arranged on the inner side of the casing K1 ( That is, the inner side of the insulator T), and are arranged on the upper and lower surfaces of the casing K1 (that is, the upper and lower surfaces of the inner side of the insulator T), for example, the power signal pins 31, 32, positive differential pins 111, 121, 131, 141, 171, 181, 191, 101 and negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 and ground pins 21, 22, 23, 24, 25, 26, 27, 28, and 29 can be located on the inner upper surface of the casing K1 (ie, the inner upper surface of the insulator T), and the positive differential low-speed pins 51, the negative differential low-speed pins 52, and the first positive differential high-speed pins Pin 151, first negative differential high-speed pin 152, tenth ground pin 20, second positive differential high-speed pin 161, second negative differential high-speed pin 162, multiple control signal pins, power signal connection The pins 33, 34, the high voltage grounding pin 61, the high voltage grounding pin 62 and the insulating layer I may be located on the lower surface of the inner side of the casing K1 (ie, the lower surface of the inner side of the insulator T). In another example, the aforementioned pins arranged on the upper surface of the inner side of the casing K1 can also be arranged on the lower surface, and the aforementioned pins arranged on the inner lower surface can be arranged on the upper surface.

In some embodiments, the housing K1 includes a protruding portion K11, and the protruding portion K11 is located on a surface of the housing K1. For example, as shown in FIG. 8C and FIG. 8D, the protruding portion K11 may be located on the housing K1 surface. The protruding portion K11 includes a pair of side walls Ka, Kb, and a top wall Kc, the side walls Ka, Kb are respectively connected to the housing K1, and the top wall Kc is connected between the side walls Ka, Kb, whereby the side walls Ka, Kb, the top wall The Kc together form the insertion space K3 of the male connector.

In some embodiments, the casing K1 includes a plurality of grooves K12, wherein the number of the grooves K12 corresponds to the number of the spring buckles O12 of the female connector to be connected, and the position of the grooves K12 on the casing K1 corresponds to The snap button O12 is located at the position of the casing O1. For example, as shown in FIG. 8C and FIG. 8D , the number of grooves K12 is two, and the groove K12 and the snap button O12 are both arranged on the upper surface of the casing. The groove K12 The protruding portion K11 is located on the same surface of the casing K1. In other embodiments, the casing K1 includes a plurality of button holes K13, wherein the number of the button holes K13 corresponds to the number of button holes O13 of the female connector to be connected to it, and the position of the button holes K13 on the casing K1 corresponds to When the button hole O13 is located at the position of the casing O1, as shown in FIG. 8C, the number of button holes K13 is two, and the button hole K13 can be located on the upper surface of the casing K1, that is, the same as the protrusion K11 and the groove K12. surface.

In some embodiments, please refer to FIG. 8E . FIG. 8E is a schematic diagram of the mating structure of the female connector of FIG. 8A ( FIG. 8B ) and the male connector of FIG. 8C ( FIG. 8D ) (connected according to the mating direction SV). When the two signal transmission devices are connected, the housing O1 of the female connector surrounds the housing K1 of the male connector. In other words, the surfaces of the housing O1 cover the surfaces of the housing K1, and the housing K1 is located on the side of the housing O1. Inside, in detail, the housing O1 is connected to the housing K1, the protruding portion O11 is connected to the protruding portion K11 and the protruding portion O11 covers the protruding portion K11, and the tongue portion O2 of the female connector is inserted into the accommodating space K2 of the male connector , so that the pins of the female connector are electrically connected to the pins of the male connector respectively. In addition, the snap buckle O12 and the groove K12 are connected with each other by a buckle, and the button hole O13 is also connected with each other by the buckle hole K13, so that the female connector and the male connector cannot be easily disengaged after being butted.

In some embodiments, please refer to FIG. 8F , which is a top view of the male connector and the female connector of FIG. 8E before being connected. It can be seen from the figure that the protruding portion O11 of the female connector is located at the left position of the center of the housing O1 (according to the horizontal direction SH in FIG. 8F ), that is, the central axis Y of the protruding portion O11 to the right inner side SE of the housing O1 The distance (hereinafter referred to as the first distance) is the length a1, the distance from the central axis Y of the protruding portion O11 to the left inner side surface SF of the housing O1 (hereinafter referred to as the second distance) is the length a2, and the length a1 is greater than or equal to the length a2. Similarly, the protruding portion K11 of the male connector is located at the left position of the central axis Y of the housing K1 (according to the horizontal direction SH in FIG. 8F ), that is, the distance from the central axis Y of the protruding portion K11 to the right outer side surface SG of the housing K1 (the following The third distance) is the length a3, the distance from the protrusion K11 to the left outer side SH of the casing K1 (hereinafter referred to as the fourth distance) is the length a4, and the length a3 is greater than or equal to the length a4. The first distance corresponds to the third distance, and the second distance corresponds to the fourth distance. Therefore, when the male connector is connected to the female connector, the housing of the female connector surrounds the housing of the male connector.

In some embodiments, the positions of the protruding parts O11 and K11 on the housings O1 and K1 can be adjusted according to the user's design, as long as the protruding part O11 of the female connector housing O1 can be smoothly connected when the female connector is butted with the male connector It is sufficient to cover the protruding portion K11 of the male connector housing K1. In some embodiments, the positions of the protruding parts O11 and K11 on the housings O1 and K1 can also be configured as shown in FIG. 9 , FIG. 10 or FIG. 11 . In FIG. 9 , the length b1 of the first distance is greater than or equal to the length b2 of the second distance, the length b3 of the third distance is greater than or equal to the length b4 of the fourth distance, and compared with FIG. 8F , the length b1 is smaller than the length a1 , the length b2 is greater than the length a2, the length b3 is less than the length a3, and the length b4 is greater than the length a4. In other embodiments, in FIG. 10 , the protruding portion O11 can also be located at a position to the right of the center of the housing O1 (according to the horizontal direction SH in FIG. 8F ), and the length c1 of the first distance is less than or equal to the length of the second distance c2, the length c3 of the third distance is less than or equal to the length c4 of the fourth distance. In other embodiments, in FIG. 11 , the length d1 of the first distance is less than or equal to the length d2 of the second distance, and the length d3 of the third distance is less than or equal to the length d4 of the fourth distance, and compared with FIG. 10 , the length d1 is less than the length c1, the length d2 is greater than the length c2, the length d3 is less than the length c3, and the length d4 is greater than the length c4. Based on this, after the distance between the protruding parts O11, K11 and the two sides of the housing O1, K1 is designed, only a specific male connector can be connected to a specific female connector, that is, the specific male connector protruding part K11 is connected to the housing. The position of K1 can correspond to the position of the specific female connector protruding part O11 in the housing O1, so through the design of the protruding parts O11 and K11, it is possible to provide a combination of signal transmission devices on different products and to separate the signal transmission device connectors. , in order to prevent the possibility of misconnection between the male connector and the female connector of different products.

In some embodiments, the housing of the signal transmission device can also be designed with protruding parts and chamfered corners at the same time, that is, as shown in FIGS. The end and the J' end can also be designed to be chamfered. The outgoing portion O11 and the protruding portion K11 are connected to each other. Therefore, more combinations of signal transmission devices are added to achieve the effect of a foolproof mechanism.

In some embodiments, the number of the protruding parts O11 and K11 is not limited, and the number of the protruding parts O11 and K11 can also be multiple, which is determined according to the user's design, and the number of the protruding parts O11 is equal to K11 The position of each protruding portion O11 in the housing O1 corresponds to the position of each protruding portion K11 in the housing K1.

In some embodiments, please refer to FIG. 12 , which illustrates a transmission line and an electronic device N suitable for the transmission line. The transmission line includes signal transmission devices P and Q and a connecting part L. The signal transmission devices P and Q are arranged at both ends of the transmission line, and the connecting part L is connected between the signal transmission device P and the signal transmission device Q. The electronic device N includes a signal transmission device R corresponding to the signal transmission devices P and Q of the transmission line. Since the signal transmission devices P, Q, and R are respectively designed as one of a male connector or a female connector, the male connector can be connected with the female connector. Therefore, the signal transmission device P or the signal transmission device Q can be connected with the electronic device N. The signal transmission device R is connected, and the electronic device N can be a notebook computer, a mobile phone, a tablet, a monitor or other audio-visual related devices. For example, when the signal transmission device P, which is a male connector, is connected to the signal transmission device R, which is a female connector, and the signal transmission device Q, which is a female connector, is connected to the signal transmission device, which is a male connector, of another electronic device, Another electronic device can send a signal from the signal transmission device Q of the transmission line to the electronic device N through the connection part L, and then through the signal transmission device P and the signal transmission device R.

In some embodiments, the two signal transmission devices P and Q of the transmission line are both male connectors or both are female connectors. In some embodiments, the pin assignments of the two signal transmission devices P and Q of the transmission line are the same or different.

In some embodiments, the insulating layer I is not designed in the form of pins and the total number of pins is 52 as an example, as shown in FIG. 2 (from top to bottom and from left to right), the first, fourth, and seventh , 10, 13, 16, 19, 22, 25, 33, 49, 50 pins are GND; pins 21, 23 respectively P3_RTK1_P, P3_RTK1_M, P3_RTK0_P, P3_RTK0_M, P2_RTK1_P, P2_RTK1_M, P2_RTK0_P, P2_RTK0_M, P1_RTK1_P, P1_RTK1_M, P1_RTK0_P, P1_RTK0_M, P0_RTK1_P, P0_RTK1_M, P0_RTK0_P, P0_RTK0_M; the first pin 26, 27 is HV_POWER; Pins 51 and 52 are UHV_POWER; pins 28-32 and 34-48 are USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK_P_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSRX_M/PCIE_HSIN, USB_SSRX_P/PCIE_HSIP, USB_SSTX_M/PCIE_HSON, USB_SSTX_P/PCIE_HSOP, HOT_PLUG_DETECT, SDA /PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, iRealOne_LINK, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO.

In some embodiments, the insulating layer I is not designed in the form of pins and the total number of pins is 52 as an example, as shown in FIG. 13A (from top to bottom and from left to right), the first, fourth, seventh , 10, 13, 16, 19, 22, 25, 33, 49, 50 pins are GND; pins 21, 23 respectively P3_RTK1_P, P3_RTK1_M, P3_RTK0_P, P3_RTK0_M, P2_RTK1_P, P2_RTK1_M, P2_RTK0_P, P2_RTK0_M, P1_RTK1_P, P1_RTK1_M, P1_RTK0_P, P1_RTK0_M, P0_RTK1_P, P0_RTK1_M, P0_RTK0_P, P0_RTK0_M; the first pin 26, 27 is HV_POWER; Pins 51 and 52 are UHV_POWER; pins 28-32 and 34-48 are USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK_P_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSRX_M/PCIE_HSIN, USB_SSRX_P/PCIE_HSIP, USB_SSTX_M/PCIE_HSON, USB_SSTX_P/PCIE_HSOP, HOT_PLUG_DETECT, SDA /PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, iRealOne_LINK, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO.

In some embodiments, the insulating layer I is not designed in the form of pins and the total number of pins is 52 as an example, as shown in FIG. 13B (from top to bottom and from left to right), the first, fourth, seventh , 10, 13, 16, 19, 22, 25, 33, 49, 50 pins are GND; pins 21, 23 respectively P0_RTK0_M, P0_RTK0_P, P0_RTK1_M, P0_RTK1_P, P1_RTK0_M, P1_RTK0_P, P1_RTK1_M, P1_RTK1_P, P2_RTK0_M, P2_RTK0_P, P2_RTK1_M, P2_RTK1_P, P3_RTK0_M, P3_RTK0_P, P3_RTK1_M, P3_RTK1_P; the first pin 26, 27 is HV_POWER; Pins 51 and 52 are UHV_POWER; pins 28-32 and 34-48 are USB_DP/REFCLK_P_PCIE, USB_DM/REFCLK_M_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSTX_P/PCIE_HSIP, USB_SSTX_M/PCIE_HSIN, USB_SSRX_P/PCIE_HSOP, USB_SSRX_M/PCIE_HSON, HOT_PLUG_DETECT, SDA /PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, iRealOne_LINK, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO.

In some embodiments, the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 31-35th pins can be unused according to the design of FIG. The total number is 35. That is, as shown in Figure 1, the 1st, 4th, 7th, 10, 13, 32, and 33rd pins are GND; the 2nd, 3rd, 5th, 6th, 8th, 9th, 11th, and 12th pins are P1_RTK1_M, P1_RTK0_P, P1_RTK0_M, P0_RTK1_P, P0_RTK1_M, P0_RTK0_P, P0_RTK0_M; pins 14 and 15 are HV_POWER; pins 34 and 35 are UHV_POWER; pins 16-31 are USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK__POWER, MAIN_PCIE, SYSTEM_POWER respectively HOT_PLUG_DETECT, SDA/PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, iRealOne_LINK, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO.

In some embodiments, the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 31-35th pins can be unused (also called as Empty pins, NC, Not connected), that is, the total number of pins is 35. That is, as shown in Figure 14A, the 1st, 4th, 7th, 10th, 13th, 32nd, and 33rd pins are GND; the 2nd, 3rd, 5th, 6, 8, 9, 11, and 12th pins are P1_RTK1_M, P1_RTK0_P, P1_RTK0_M, P0_RTK1_P, P0_RTK1_M, P0_RTK0_P, P0_RTK0_M; pins 14 and 15 are HV_POWER; pins 34 and 35 are UHV_POWER; pins 16-31 are USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK__POWER, MAIN_PCIE, SYSTEM_POWER respectively HOT_PLUG_DETECT, SDA/PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, iRealOne_LINK, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO.

In some embodiments, the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 31-35th pins can be unused (also called as Empty pins, NC, Not connected), that is, the total number of pins is 35. That is, as shown in Figure 14B, the 1st, 4th, 7th, 10, 13, 32, and 33rd pins are GND; the 2nd, 3rd, 5th, 6, 8, 9, 11, and 12th pins are P0_RTK0_P, P0_RTK1_M, P0_RTK1_P, P1_RTK0_M, P1_RTK0_P, P1_RTK1_M, P1_RTK1_P; pins 14 and 15 are HV_POWER; pins 34 and 35 are UHV_POWER; pins 16-31 are USB_DP/REFCLK_P_PCIE, USB_DM/REFCLK__POWER_M_PCIE, SYSTEM_MAIN HOT_PLUG_DETECT, SDA/PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, iRealOne_LINK, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO.

Please refer to FIG. 15A to FIG. 20B , which are schematic diagrams of an embodiment of the signal transmission device according to the present application, respectively. 15A and 15B can be respectively applied to the two signal transmission devices P and Q of the transmission line in FIG. 12; the signal transmission device of FIG. 16A and FIG. Q; the signal transmission device of FIG. 17A and FIG. 17B can be applied to the two signal transmission devices P and Q of the transmission line in FIG. 12 respectively; the signal transmission device of FIG. 18A and FIG. 18B can be respectively applied to the two signal transmission devices P, Q; the signal transmission device of FIG. 19A and FIG. 19B can be applied to the two signal transmission devices P and Q of the transmission line in FIG. 12 respectively; the signal transmission device of FIG. 20A and FIG. 20B can be respectively applied to the two signal transmission devices P and Q of the transmission line of FIG. Q.

Figure 1 and Figure 14A to Figure 20B have no defined pin positions (as shown in Figure 1, the top 12 pins on the left side (pins 1-12) and the 4th to 8th pins on the right side (pins 31-35) pin)) is an empty pin (NC, not-connected), but not limited to this. In some embodiments, without affecting the electrical characteristics, the free pin can be electrically connected to a power terminal or a ground terminal, or used as a General Purpose Input/Output pin, or used as a connection for other purposes. foot.

The pins of the signal transmission device in Fig. 15A are numbered sequentially from the 1st pin to the 54th pin (the upper left of Fig. 15A is vertically downward, and then vertically downward from the upper right of Fig. 15A ) are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND, P1_RTK1_P, P1_RTK1_M, GND, P1_RTK0_P, P1_RTK0_M, GND, P0_RTK1_P, P0_RTK1_M, GND, P0_RTK0_P, P0_RTK0_M, GND, HV USB_DM, USB_DP, SYSTEM_MAIN_POWER_EN, NC, NC, GND, NC, NC, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK, NC, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, UHV_POWER. Among them, NC means empty pin, PHYSICAL INSULATOR means physical insulation, to avoid fire arc or electrical coupling effect caused by excessive voltage between the power signal pin and the ground pin, HOT_PLUG_DETECT means hot plug detection , GND means ground, POWER means power. PDM stands for Pulse Density Modulation, SCL/SDA stands for a set of I2C interfaces, iRealOne_SCL and iRealOne_SDA stand for a set of dedicated I2C interfaces for the signal transmission device, GPIO stands for general-purpose output and input ports, and P0_RTK0_M and P0_RTK0_P stand for this signal transmission Differential signal pins of the same group of devices. HV_POWER and HV_POWER2 represent two sets of high-voltage power supplies transmitted through this signal transmission device, UHV_POWER and UHV_GND respectively represent the ultra-high voltage power supply and the corresponding ground signal transmitted through this signal transmission device, SYSTEM_MAIN_POWER_EN means to control the main power on and off The signal of iRealOne_LINK indicates that this signal transmission device is used to transmit the signal of a specific packet.

The pins of the signal transmission device in Figure 15B are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54 respectively. , P0_RTK0_M, P0_RTK0_P, GND, P0_RTK1_M, P0_RTK1_P, GND, P1_RTK0_M, P1_RTK0_P, GND, P1_RTK1_M, P1_RTK1_P, GND, HV_POWER, HV_POWER, USB_OneDP, USB_DM, SYSTEM_MAIN_POWER_EN, NC, NC, GND, NC, NC, HOT_PLUG5_DETECT , NC, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 16A are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54 respectively. , NC, NC, GND, P0_RTK1_P, P0_RTK1_M, GND, P0_RTK0_P, P0_RTK0_M, GND, NC, NC, GND, HV_POWER, HV_POWER, USB_DM, USB_DP, SYSTEM_MAIN_POWER_EN, NC, NC, GND, NC, NC, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK , NC, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 16B are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54. , NC, NC, GND, P0_RTK0_M, P0_RTK0_P, GND, P0_RTK1_M, P0_RTK1_P, GND, NC, NC, GND, HV_POWER, HV_POWER, USB_DP, USB_DM, SYSTEM_MAIN_POWER_EN, NC, NC, GND, NC, NC, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK , NC, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 17A are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54. , NC, NC, GND, NC, NC, GND, P0_RTK1_P, P0_RTK1_M, GND, P0_RTK0_P, P0_RTK0_M, GND, HV_POWER, HV_POWER, USB_DM, USB_DP, SYSTEM_MAIN_POWER_EN, NC, NC, GND, NC, NC, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK , NC, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 17B are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54. , NC, NC, GND, NC, NC, GND, P0_RTK0_M, P0_RTK0_P, GND, P0_RTK1_M, P0_RTK1_P, GND, HV_POWER, HV_POWER, USB_DP, USB_DM, SYSTEM_MAIN_POWER_EN, NC, NC, GND, NC, NC, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK , NC, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 18A are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54. , P1_RTK1_P, P1_RTK1_M, GND, P1_RTK0_P, P1_RTK0_M, GND, P0_RTK1_P, P0_RTK1_M, GND, P0_RTK0_P, P0_RTK0_M, GND, HV_POWER, HV_POWER, USB_DM / REFCLK_M_PCIE, USB_DP / REFCLK_P_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSRX_M / PCIE_HSIN, USB_SSRX_P / PCIE_HSIP, GND, USB_SSTX_M /PCIE_HSON, USB_SSTX_P/PCIE_HSOP, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK, GPIO8, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 18B are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54. , P0_RTK0_M, P0_RTK0_P, GND, P0_RTK1_M, P0_RTK1_P, GND, P1_RTK0_M, P1_RTK0_P, GND, P1_RTK1_M, P1_RTK1_P, GND, HV_POWER, HV_POWER, USB_DP / REFCLK_P_PCIE, USB_DM / REFCLK_M_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSTX_M / PCIE_HSIP, USB_SSTX_M / PCIE_HSIN, GND, USB_SSRX_P /PCIE_HSOP, USB_SSRX_M/PCIE_HSON, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK, GPIO8, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 19A are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54. , NC, NC, GND, P0_RTK1_P, P0_RTK1_M, GND, P0_RTK0_P, P0_RTK0_M, GND, NC, NC, GND, HV_POWER, HV_POWER, USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK_P_PCIE, SYSTEM_MAIN_MPOWER_EN, USB_SSRX_M/PCIE_HSIN, USB_SSRX_P/PCIE_HSTXIP, GND, USB_SS /PCIE_HSON, USB_SSTX_P/PCIE_HSOP, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK, GPIO8, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 19B are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54. , NC, NC, GND, P0_RTK0_M, P0_RTK0_P, GND, P0_RTK1_M, P0_RTK1_P, GND, NC, NC, GND, HV_POWER, HV_POWER, USB_DP/REFCLK_P_PCIE, USB_DM/REFCLK_M_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSTX_P/PCIE_HSIP, USB_SSTX_M/PCIE_HSIN_P_GND, USB_SSRX /PCIE_HSOP, USB_SSRX_M/PCIE_HSON, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK, GPIO8, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 20A are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54 respectively. , NC, NC, GND, NC, NC, GND, P0_RTK1_P, P0_RTK1_M, GND, P0_RTK0_P, P0_RTK0_M, GND, HV_POWER, HV_POWER, USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK_P_PCIE, SYSTEM_MAIN_MPOWER_EN, USB_SSRX_M/PCIE_HSIN, USB_SSRX_P/PCIE_HSTXIP, GND, USB_SS /PCIE_HSON, USB_SSTX_P/PCIE_HSOP, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK, GPIO8, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

The pins of the signal transmission device in Figure 20B are GND, GPIO1, GPIO2, GND, iRealOne_SCL, iRealOne_SDA, GND, SDA, SCL, GND, GPIO3/PDM_D1, GPIO4/PDM_D0, GND from pin 1 to pin 54 respectively. , NC, NC, GND, NC, NC, GND, P0_RTK0_M, P0_RTK0_P, GND, P0_RTK1_M, P0_RTK1_P, GND, HV_POWER, HV_POWER, USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK_P_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSTX_P/PCIE_HSIP, USB_SSTX_M/PCIE_HSIN_P_GND, USB_SSRX /PCIE_HSOP, USB_SSRX_M/PCIE_HSON, HOT_PLUG_DETECT, iRealOne_LINK, GPIO5_PDM_CLK, GPIO8, GND, GND, HV_POWER2, HV_POWER2, HV_POWER2, HV_POWER2, GND, GND, NC, UHV_GND, UHV_GND, PHYSICAL INSULATOR, PHYSICAL INSULATOR, UHV_POWER, and UHV_POWER.

In some embodiments, the number of the aforementioned core wires can be adjusted according to different applications and embodiments. For example, the number of pins is 52 and all the pins are used. The signal transmission device can be formed by winding 50 core wires. The number is 52 and 35 pins are used as an example, the signal transmission device can be formed by winding 33 core wires. Users can choose different differential pins and control signal wiring combinations according to the specifications to be supported to achieve the purpose of transmitting data and power signals.

To sum up, according to an embodiment of the signal transmission device of the present application, the same pair of differential signal pins is arranged between the two ground pins, which can avoid signal crosstalk and obtain better impedance matching characteristics. Furthermore, the most edge position end of the pin accommodating space is provided with a ground pin, which can prevent the differential signal from being interfered by the noise outside the signal transmission device, and reduce the energy that the differential signal transmits to the outside of the signal transmission device in the form of electromagnetic waves. , in order to reduce electromagnetic interference (Electromagnetic Interference; EMI) to achieve better electromagnetic compatibility (electromagnetic compatibility; EMC), and electrostatic protection effect (Electro-Static discharge; ESD). The signal transmission device thus improves the transmission quality, and the transmission line can transmit the signal to the electronic device more efficiently. In addition, the signal transmission device can support a variety of existing transmission specifications, such as USB specification, PCIe specification, Display Port specification and HDMI specification, so that a single signal transmission device can transmit a larger amount of data transmission through multiplexing, and users do not need to prepare multiple Support different specifications of transmission lines to promote the convenience of use.

Although this case has been disclosed with the above examples, it is not intended to limit this case. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of this case. Therefore, the protection scope of this case is The scope of the patent application attached herewith shall prevail.

111: The first positive differential pin 112: The first negative differential pin 121: The second positive differential pin 122: Second negative differential pin 131: The third positive differential pin 132: The third negative differential pin 141: Fourth positive differential pin 142: Fourth negative differential pin 151: The first positive differential high-speed pin 152: The first negative differential high-speed pin 161: The second positive differential high-speed pin 162: The second negative differential high-speed pin 171: seventh positive differential pin 172: seventh negative differential pin 181: Eighth positive differential pin 182: Eighth negative differential pin 191: ninth positive differential pin 192: Ninth negative differential pin 101: The tenth positive differential pin 102: Tenth negative differential pin 21: The first ground pin 22: The second ground pin 23: The third ground pin 24: Fourth ground pin 25: Fifth ground pin 26: The sixth ground pin 27: seventh ground pin 28: Eighth ground pin 29: ninth ground pin 20: Tenth ground pin 31: Power signal pin 32: Power signal pin 33: Power signal pin 34: Power signal pin 410: System main power enable pin 411: hot plug detection pin 412: SDA/PCIE_PERST_N pin 413: CLK pin 414: SCL/PCIE_WAKE_N pin 415: iRealOne_LINK pin 416: SPI_DI pin 417:SPI_CS pin 418: SPI_CLK pin 419: REALONE_SCL pin 420: REALONE_SDA pin 421:SPI_WP_PWM pin 422:SPI_HOLD_PWM pin 423:SPI_DO pin 51: Positive differential low-speed pin 52: Negative differential low-speed pin 61: High voltage ground pin 62: High voltage ground pin I: insulating layer M: Metal isolation layer D1: Direction D2: Direction G1: Wire G2: Wire G3: Wire G4: Wire SA: one side SB: one side SE: Right medial side SF: Left medial side SG: Right outer side SH: Left outer side A: end A': end B: end B': end C: end C': end D: end D': end E: end E': end F: end F': end H: end H': end J: end J': end O1: Shell O11: Projection O12: Snap O13: button hole O2: Tongue O3: accommodating space O4: Insert Space Oa: Sidewall Ob: Sidewall Oc: top wall K1: Shell K11: Projection K12: Groove K13: button hole K2: accommodating space K3: Insert Space Ka: sidewall Kb: Sidewall Kc: top wall T: insulator Z: substrate P: Signal transmission device Q: Signal transmission device R: signal transmission device L: connecting part N: electronic device SV: docking direction SH: horizontal direction Y: center axis a1: length a2: length a3: length a4: length b1: length b2: length b3: length b4: length c1: length c2: length c3: length c4: length d1: length d2: length d3: length d4: length

[FIG. 1] is a schematic diagram of an embodiment of the signal transmission device according to the present application. FIG. 2 is a schematic diagram of another embodiment of the signal transmission device of FIG. 1 . FIG. 3 is a schematic diagram of an embodiment of the pin arrangement of the signal transmission device according to the present application. FIG. 4 is a schematic diagram of an embodiment of the pin arrangement of the signal transmission device according to the present application. FIG. 5A is a schematic view of the appearance of an embodiment of the female connector of the signal transmission device according to the present application. FIG. 5B is a schematic diagram of the appearance of one embodiment of the male connector of the signal transmission device corresponding to FIG. 5A . 5C is a schematic side view of an embodiment of the signal transmission device of FIG. 5A . 5D is a schematic side view of an embodiment of the signal transmission device of FIG. 5B . 6A is a schematic side view of another embodiment of the female connector of the signal transmission device according to the present application. 6B is a schematic side view of another embodiment of the male connector of the signal transmission device corresponding to FIG. 6A . 7A is a schematic side view of another embodiment of the female connector of the signal transmission device according to the present application. FIG. 7B is a schematic side view of another embodiment of the male connector of the signal transmission device corresponding to FIG. 7A . 8A is a schematic view of the appearance of another embodiment of the female connector of the signal transmission device according to the present application. 8B is a schematic side view of another embodiment of the signal transmission device of FIG. 8A . 8C is a schematic view of the appearance of another embodiment of the male connector of the signal transmission device corresponding to FIG. 8A . 8D is a schematic side view of another embodiment of the signal transmission device corresponding to FIG. 8C . 8E is a schematic diagram of an external appearance of an embodiment corresponding to the interconnection between the female connector of the signal transmission device of FIG. 8A and the male connector of the signal transmission device of FIG. 8C . 8F is a schematic top view of an embodiment of the female connector of the signal transmission device of FIG. 8A and the male connector of the signal transmission device of FIG. 8C . 9 is a schematic top view of another embodiment of the female connector and the male connector of the signal transmission device according to the present application. 10 is a schematic top view of another embodiment of the female connector and the male connector of the signal transmission device according to the present application. 11 is a schematic top view of another embodiment of the female connector and the male connector of the signal transmission device according to the present application. 12 is a schematic diagram of an embodiment of a transmission line including a signal transmission device and an electronic device according to the present application. 13A and 13B are schematic diagrams of another embodiment of the signal transmission device according to the present application, respectively. [FIG. 14A and FIG. 14B] are schematic diagrams of another embodiment of the signal transmission device of FIG. 13, respectively. [FIG. 15A and FIG. 15B] are schematic diagrams of one embodiment of the signal transmission device according to the present application, respectively. [FIG. 16A and FIG. 16B] are schematic diagrams of one embodiment of the signal transmission device according to the present application, respectively. [FIG. 17A and FIG. 17B] are schematic diagrams of an embodiment of the signal transmission device according to the present application, respectively. [FIG. 18A and FIG. 18B] are schematic diagrams of an embodiment of the signal transmission device according to the present application, respectively. [FIG. 19A and FIG. 19B] are schematic diagrams of one embodiment of the signal transmission device according to the present application, respectively. 20A and 20B are schematic diagrams of an embodiment of the signal transmission device according to the present application, respectively.

111: The first positive differential pin

112: The first negative differential pin

121: The second positive differential pin

122: Second negative differential pin

131: The third positive differential pin

132: The third negative differential pin

141: Fourth positive differential pin

142: Fourth negative differential pin

21: The first ground pin

22: The second ground pin

23: The third ground pin

24: Fourth ground pin

25: Fifth ground pin

31: Power signal pin

32: Power signal pin

33: Power signal pin

34: Power signal pin

410: System main power enable pin

411: hot plug detection pin

412: SDA/PCIE_PERST_N pin

413: CLK pin

414: SCL/PCIE_WAKE_N pin

415: iRealOne_LINK pin

416: SPI_DI pin

417:SPI_CS pin

418: SPI_CLK pin

419: REALONE_SCL pin

420: REALONE_SDA pin

421:SPI_WP_PWM pin

422:SPI_HOLD_PWM pin

423:SPI_DO pin

51: Positive differential low-speed pin

52: Negative differential low-speed pin

61: High voltage ground pin

62: High voltage ground pin

I: insulating layer

M: Metal isolation layer

D1: Direction

D2: Direction

Claims (10)

A signal transmission device capable of transmitting complex data streams, comprising: A plurality of positive differential pins, one of the positive differential pins is a first positive differential pin for transmitting a positive signal component of a first differential signal, one of the positive differential pins is a second one The positive differential pin is used for transmitting a positive signal component of a second differential signal; A plurality of negative differential pins, one of the negative differential pins is a first negative differential pin for transmitting a negative signal component of a first differential signal, and one of the negative differential pins is a second one The negative differential pin is used for transmitting a negative signal component of a second differential signal; a positive differential low-speed pin for transmitting the positive signal component of a low-speed differential signal; a negative differential low-speed pin for transmitting the negative signal component of the low-speed differential signal; Plural ground pins; Plural power signal pins; a plurality of control signal pins; and a metal isolation layer; Wherein, the first positive differential pin and the first negative differential pin are located on one side of one of the ground pins, the second positive differential pin and the second negative pin The differential pin is located on the other side of the first ground pin, the positive differential pins and the negative differential pins are located on one side of the metal isolation layer, the positive differential low-speed pin, the negative differential pin The differential low-speed pins and the control signal pins are located on the other side of the metal isolation layer. The signal transmission device of claim 1, wherein the second positive differential pin and the second negative differential pin are further located on the first ground pin and a second ground among the ground pins between the pins. The signal transmission device of claim 2, wherein the first positive differential pin and the first negative differential pin are further located on the first ground pin and a third ground among the ground pins between the pins. The signal transmission device of claim 1, wherein the positive differential pins and the negative differential pins transmit high-speed signals. The signal transmission device of claim 4, wherein a first positive differential high-speed pin among the positive differential pins is used to transmit a positive signal component of a fifth differential signal, and the negative differential pins are used for transmitting a positive signal component of a fifth differential signal. A first negative differential high-speed pin among the pins is used for transmitting a negative signal component of the fifth differential signal, and a second positive differential high-speed pin among the positive differential pins is used for transmitting a first differential high-speed pin the positive signal components of the six differential signals, a second negative differential high-speed pin among the negative differential pins is used for transmitting the negative signal components of the sixth differential signal; Wherein, the control signal pins include a system main power enable pin, and the system main power enable pin is located at the positive differential low-speed pin, the negative differential low-speed pin and the first positive differential high-speed pin between the pin, the first negative differential high-speed pin, the second positive differential high-speed pin, and the second negative differential high-speed pin, and the first positive differential high-speed pin and the first The negative differential high-speed pin is located on one side of a tenth ground pin among the ground pins, and the second positive differential high-speed pin and the second negative differential high-speed pin are located on the tenth ground pin on the other side. The signal transmission device according to claim 3, wherein the power signal pins are a plurality of low-voltage power pins and a plurality of high-voltage power pins, the low-voltage power pins are used for transmitting low-voltage power signals, and the high-voltage power pins are used for transmitting low-voltage power signals. The pin is used for transmitting high-voltage power signal, and the third ground pin is located between the low-voltage power pins, the first positive differential pin and the first negative differential pin. A signal transmission device capable of transmitting complex data streams, comprising: A plurality of positive differential pins, one of the positive differential pins is a first positive differential pin for transmitting a positive signal component of a first differential signal, one of the positive differential pins is a second one The positive differential pin is used for transmitting a positive signal component of a second differential signal; A plurality of negative differential pins, one of the negative differential pins is a first negative differential pin for transmitting a negative signal component of a first differential signal, and one of the negative differential pins is a second one The negative differential pin is used for transmitting a negative signal component of a second differential signal; a positive differential low-speed pin for transmitting the positive signal component of a low-speed differential signal; a negative differential low-speed pin for transmitting the negative signal component of the low-speed differential signal; Plural ground pins; Plural power signal pins; Plural control signal pins; a metal isolation layer; a shell; and an insulator located in the casing, the casing is used for accommodating the positive differential pins, the negative differential pins, the ground pins, the power signal pins and the control signal pins , the shell includes a chamfered corner, the chamfered corner is located on one side of the shell; Wherein, the first positive differential pin and the first negative differential pin are located on one side of one of the ground pins, the second positive differential pin and the second negative pin The differential pin is located on the other side of the first ground pin, the positive differential pins and the negative differential pins are located on one side of the metal isolation layer, the positive differential low-speed pin, the negative differential pin The differential low-speed pins and the control signal pins are located on the other side of the metal isolation layer. The signal transmission device according to claim 7, wherein the housing has an accommodating space and a protruding portion, the protruding portion includes a pair of side walls and a top wall, and the top wall is connected between the pair of side walls, The pair of side walls and the top wall together form an insertion space, the insertion space and the accommodating space communicate with each other; the insulator is a tongue, the tongue is located in the accommodating space, the positive differential pins, the The negative differential pins, the ground pins, the power signal pins and the control signal pins are located on the tongue. The signal transmission device as claimed in claim 7, wherein the housing has an accommodating space surrounded by the insulator and a protruding portion, the positive differential pins, the negative differential pins, the The ground pins, the power signal pins and the control signal pins are located on the inner surface of the insulator, the protruding portion includes a pair of side walls and a top wall, the top wall is connected between the pair of side walls, the pair of side walls and the top wall together form an insertion space. A signal transmission device capable of transmitting complex data streams, comprising: The complex positive differential pins are used to transmit the positive signal component of the complex differential signal; a plurality of negative differential pins for transmitting the negative signal components of the differential signals; a positive differential low-speed pin for transmitting the positive signal component of a low-speed differential signal; a negative differential low-speed pin for transmitting the negative signal component of the low-speed differential signal; Plural ground pins; Plural power signal pins; Plural control signal pins; a metal isolation layer, the positive differential pins and the negative differential pins are located on one side of the metal isolation layer, the positive differential low-speed pins, the negative differential low-speed pins and the control signals are connected to The pins are located on the other side of the metal isolation layer, and the positive differential pins and the negative differential pins and the plurality of positive differential high-speed pins and the plurality of negative differential high-speed pins are connected by the The metal isolation layers are arranged side by side; and a casing with an accommodating space and a protruding part, the positive differential pins, the negative differential pins, the ground pins, the power signal pins and the control signal pins Located on the inner surface of the housing, the protruding portion includes a pair of side walls and a top wall, the top wall is connected between the pair of side walls, the pair of side walls and the top wall together form an insertion space, the insertion space and the accommodating space interconnected.

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