TW202425335A - P-gan high electron mobility transistor field plating - Google Patents

Abstract

A high electron mobility transistor (HEMT) which includes a source disposed on a surface, a drain disposed on the surface, a gate disposed on the surface between the source and the drain, and a first field plate disposed on the surface between the gate and the drain. In some implementations, the first field plate includes a p-type doped GaN (P-GAN). In some implementations, the first field plate includes a doping concentration, doping material, geometry, and/or position that is configured to minimize an increase of an on-resistance of the HEMT. In some implementations, the first field plate extends continuously between and parallel to the source and the drain regions, such that any path from the source to the drain passes under, through, or over the first field plate. In some implementations, the first field plate extends continuously beyond an entire width of the surface between the source and the drain.

Description

P-type GaN high electron mobility transistor field deposition

The present invention relates to transistor devices, and more particularly to field plating of high electron mobility transistor (HEMT) devices.

A HEMT is a field effect transistor (FET) that has a junction between two materials with different bandgaps as a channel. Such a junction may be called a heterojunction, and a HEMT may also be called a heterostructure FET (HFET). A HEMT may also be called a modulation-doped FET (MODFET). This is in contrast to the doped region that typically serves as the channel in a metal-oxide semiconductor FET (MOSFET). HEMTs are typically characterized by relatively low on-resistance, high breakdown voltage, and low switching losses.

Typical HEMTs are used in power amplifiers, wireless communication systems, voltage converters, and other applications.

During operation, HEMTs generate electromagnetic fields. In some cases, the electromagnetic fields may interfere with gate operation. Some HEMTs include a metal structure, called a field plate, to mitigate the effects of the electromagnetic fields.

A high electron mobility transistor (HEMT) includes a source disposed on a surface, a drain disposed on the surface, a gate disposed on the surface between the source and the drain, and a first field plate disposed on the surface between the gate and the drain. In some embodiments, the first field plate includes p-type doped gallium nitride (p-type doped GaN, P-GAN). In some embodiments, the first field plate includes a doping concentration, doping material, geometry, and/or location configured to minimize an increase in the on-resistance of the HEMT. In some embodiments, the first field plate extends continuously between and parallel to the source and drain regions, such that any path from the source to the drain passes below, inside, or above the first field plate. In some embodiments, the first field plate extends continuously beyond the entire width of the surface between the source and the drain.

Some embodiments provide a high electron mobility transistor (HEMT). The HEMT includes a source disposed on a surface; a drain disposed on the surface; a gate disposed on the surface between the source and the drain; and a first field plate disposed on the surface between the gate and the drain.

In some embodiments, the first field plate comprises doped gallium nitride (GaN). In some embodiments, the first field plate is at a floating voltage. In some embodiments, the first field plate is not electrically connected to a voltage source. In some embodiments, the second field plate is disposed on a surface between the gate and the first field plate. In some embodiments, the second field plate is electrically connected to a voltage source. In some embodiments, the second field plate is electrically connected to a source. In some embodiments, the first field plate comprises GaN and has a different dopant concentration, a different dopant type, or a different dopant material than the gate. In some embodiments, the first field plate comprises a doping concentration, doping material, geometry, and/or location configured to minimize an increase in the on-resistance of the HEMT. In some embodiments, the first field plate is continuous. In some embodiments, the first field plate extends continuously between and parallel to the source and drain regions such that any path from the source to the drain passes below, within, or above the first field plate. In some embodiments, the first field plate extends continuously beyond the entire width of the surface between the source and the drain. In some embodiments, the first field plate is closer to the gate than to the drain. In some embodiments, the first field plate includes p-type doped gallium nitride (P-GAN). In some embodiments, the first field plate includes p-type doped aluminum gallium nitride (AlGaN) or n-type doped AlGaN.

Some embodiments provide a method for fabricating a high electron mobility transistor (HEMT). A gate material is deposited on a surface between a source and a drain. A first field plate material is deposited on a surface between the gate material and the drain.

In some embodiments, the gate material and the first field plate material include doped gallium nitride (GaN). In some embodiments, the first field plate material extends continuously across the surface between the source and the drain, so that any path from the source to the drain passes below, inside, or above the first field plate material. In some embodiments, the first field plate material includes p-type doped GaN (P-GaN). In some embodiments, the first field plate material includes p-type doped aluminum gallium nitride (AlGaN) or n-type doped AlGaN.

Reference will now be made in detail to various specific examples, embodiments of which are illustrated in the accompanying drawings. Although described in conjunction with these specific examples, it should be understood that it is not intended to limit the scope of the application to these specific examples. On the contrary, the description is intended to cover alternatives, modifications and equivalents, which may be included in the spirit and scope of this specification as defined by the attached application. In addition, in the following detailed description of the invention, many specific details are set forth to provide a thorough understanding. However, a person of ordinary skill in the art will recognize that the various specific examples can be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the particular embodiments.

Certain terms are used in the following description for convenience only and are not limiting. The words "right," "left," "top," and "bottom" indicate directions in the drawings to which reference is made. Unless specifically stated otherwise, the words "a" and "one" as used in the claims and the corresponding portions of this specification are defined to include one or more of the items mentioned. This term includes the words specifically mentioned above, their derivatives, and words of similar meaning. The phrase "at least one" followed by two or more items such as "A, B, or C" means any individual one of A, B, or C and any combination thereof. It may be noted that some of the figures are shown with partial transparency for purposes of explanation, illustration and demonstration purposes only, and are not intended to indicate that the elements themselves will be transparent in their final manufactured form.

It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of this specification, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and/or" includes any one of the relevant listed items and all combinations of one or more.

It should be understood that when an element such as a layer, region, substrate, conductor, clip, pad, or contact is referred to as being "on" or extending "onto" another element, it may be directly on or directly extending onto another element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. It should be understood that these terms are intended to encompass different orientations of elements in addition to any orientation depicted in the figures.

Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The figures are not drawn to scale, and only portions of structures and the various layers forming those structures may be shown in the figures. In general, the figures depict symbolized and simplified structures for ease of understanding, and are not intended to reproduce physical structures in detail. In addition, manufacturing processes and operations may be performed in conjunction with the processes and operations discussed herein; that is, there may be several process operations before, between, and/or after the operations shown and described herein. In addition, specific examples may be implemented in conjunction with these other (possibly known) processes and operations without significantly interfering with them. In general, specific examples may replace and/or supplement portions of known processes without significantly affecting surrounding processes and operations.

The term "HEMT" is generally understood to be synonymous with the terms heterostructure FET (HFET) and modulation doped FET (MODFET). The term "HEMT" includes devices commonly known or referred to as HEMT, FET, or MODFET.

The term "MOSFET" is generally understood to be synonymous with the term insulated-gate field-effect transistor (IGFET) because many modern MOSFETs include non-metallic gates and/or non-oxide gate insulators. As used herein, the term "MOSFET" does not necessarily imply or require a FET including metal gates and/or oxide gate insulators. Rather, the term "MOSFET" includes devices commonly known or referred to as MOSFETs.

The term "substantially" in the description and claims of this application is used to refer to design intent, not the physical result. Semiconductor technology has deployed the ability to measure many aspects of semiconductors with increasing accuracy. Therefore, when measured to available accuracy, the physical aspects of semiconductors are generally not exactly as designed. In addition, measurement technology can easily identify differences in structures that are intended to be the same. Therefore, terms such as "substantially equal" should be interpreted as designed to be equal, subject to manufacturing variations and measurement accuracy.

FIG. 1 is a cross-sectional view of an exemplary HEMT 100. HEMT 100 includes a source contact 105, a drain contact 110, a gate 115, a substrate 120, a buffer layer 125, a channel layer 130, a barrier layer 135, a dielectric 140, a gate contact 150, and a field plate 160. For purposes of example, HEMT 100 is an enhancement mode device, however, it should be noted that the principles described herein also apply to depletion mode HEMT devices. Some embodiments include a subset of the exemplary components described with respect to FIG. 1 or additional components. For example, some embodiments include a source, a gate, and a drain on a substrate that includes a different combination of layers, or omit the field plate.

1, the HEMT 100 is in an off state when both the gate contact 150 and the source contact 105 are at ground potential, and in an on state when the gate contact 150 is above a critical voltage. The barrier layer 135 has a higher band gap than the channel layer 130, thereby promoting the formation of the 2DEG 170. In the on state, since the drain contact 110 is increased in potential relative to the source contact 105, the electric field forces the high mobility electrons in the 2DEG 170 to migrate from the source contact 105 to the drain contact 110, thereby causing current to flow. The presence of the 2DEG 170 below the gate contact 150 depends on the voltage applied to the gate contact 150. Above a critical gate voltage, the 2DEG 170 is continuous between the source contact 105 and the drain contact 110. Below the critical gate voltage, the 2DEG 170 becomes depleted until the 2DEG 170 below the gate contact 150 between the source contact 105 and the drain contact 110 is disconnected. When the gate contact 150 is below the critical gate voltage, the 2DEG 170 stops flowing between the drain contact 110 and the source contact 105, thereby preventing current flow and putting the HEMT 100 into an off state.

The substrate 120 may be made of any suitable material, such as silicon (Si), an engineered substrate (e.g., QST®), silicon carbide (SiC), gallium nitride (GaN), or any other suitable material or combination of materials, such as a material capable of supporting the growth of a III-nitride material. In this embodiment, the substrate 120 is made of QST. In some embodiments, a nucleation layer (not shown) may be formed on the substrate 120, such as to reduce the lattice mismatch between the substrate of the HEMT 100 and the buffer layer 125. The nucleation layer may include any suitable material and may be formed on the substrate 120 using any suitable one or more semiconductor growth techniques, such as metal oxide chemical vapor deposition (MOCVD), hybrid vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

The buffer layer 125 may be formed on the substrate 120 (or the corresponding nucleation layer). In some embodiments, the buffer layer 125 is a high-resistivity material or includes a high-resistivity material. In this case, the high-resistivity material is a material whose resistivity in the device does not cause leakage current to be higher than the required amount (e.g., higher than the critical leakage current). In some embodiments, such materials may have a doping concentration (intentionally or unintentionally doped) of (or approximately, or about) 1×10 ¹⁵ /cm ^3. In some embodiments, the buffer layer 125 includes a doped or undoped III-nitride material layer. In this embodiment, the buffer layer 125 is made of a single layer or multiple layers of AlGaN, however, any suitable group III nitride material may be used. In some embodiments, the buffer layer 125 is doped with iron, carbon, or any other suitable dopant, for example to reduce trap density. The buffer layer 125 may be formed on the substrate 120 (or corresponding nucleation layer) using AlN or any suitable one or more semiconductor growth techniques, such as metal oxide chemical vapor deposition (MOCVD), hybrid vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

The channel layer 130 may be formed on the buffer layer 125. In some embodiments, the channel layer 130 includes any suitable doped or undoped III-nitride material. In this embodiment, the channel layer is made of GaN, however, any suitable III-nitride material may be used. The channel layer 130 may be formed on the buffer layer 125 using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE.

In some embodiments, the channel layer 130 has a thickness suitable for preventing wafer warping. In some embodiments, the channel layer 130 has a minimum thickness suitable for preventing wafer warping. In some embodiments, the channel layer 130 has a thickness in the range of hundreds of nanometers. In some embodiments, the channel layer 130 is a high resistance layer that can be made of unintentionally doped or low-doped materials. In this case, the high resistance material is a material whose resistance in the device does not cause leakage current to be higher than the desired amount (e.g., higher than the critical leakage current). In some embodiments, such materials may have (or approximately, or about) a doping concentration (intentional or unintentional doping) of 1×10 ¹⁵ /cm ³ . In some embodiments, the channel layer 130 is or includes an n-type III-nitride material. Conceptually, some embodiments may use a p-type III-nitride material, where the device is configured to operate using a two-dimensional hole gas (2DHG).

The barrier layer 135 may be formed on the channel layer 130. Like the buffer layer 125, the barrier layer 135 may include a doped or undoped III-nitride material layer. The barrier layer 135 may be formed on the channel layer 130 using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In some of these embodiments, the barrier layer 135 includes AlGaN with a thickness in the range of 12 nm to 25 nm for an Al mole fraction of 0.18 to 0.23. In some implementations, the thickness of the barrier layer 135 can vary between different regions of the device (eg, the barrier layer 135 can have different thicknesses under the gate 115 and/or in the drain access region and/or under the source contact 105 and/or the drain contact 110).

The gate 115 may be formed on the surface of the barrier layer 135. In some embodiments, the gate 115 includes any suitable III-nitride material. In this embodiment, the gate 115 is made of doped GaN (p-type GaN in this embodiment) grown on the barrier layer 135. In some embodiments, the gate 115 has a non-uniform doping concentration (p-type in this embodiment). For example, such non-uniform doping concentration can be selected to form a specific electric field and depletion region in the gate 115.

The gate 115 can be formed on the surface of the barrier layer 135 using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In some embodiments, the gate 115 is made of GaN (e.g., p-type GaN). In some embodiments, the gate 115 has a doping concentration in the range of 1×10 ¹⁶ cm ³ to 1×10 ²⁰ cm ³ (e.g., 2×10 ¹⁹ cm ³ to 3×10 ¹⁹ cm ³ ) and a thickness in the range of 50 nm to 150 nm.

The gate contact 150 is an electrode that is in Schottky contact or Ohmic contact with the gate 115 and is formed using any suitable one or more metal deposition techniques. The gate contact 150 is made of aluminum or any other suitable metal, metal stack, or any other conductor or conductor layer. In some embodiments, these materials are configured to provide Ohmic or Schottky contact. In some embodiments, as shown in FIG. 1 , the gate contact 150 extends over the barrier layer 135 in the direction of the drain contact 110, but does not contact the barrier layer (e.g., separated by a dielectric). In some such embodiments, an extended portion of gate contact 150 can act as a field plate to shield gate 115 from electric fields (e.g., high electric fields, such as fields having a strength greater than a critical field strength, or fields greater than a critical electric field ( _Ec )) of one or more layers of material. In some embodiments, _Ec is typically equal to or approximately 4 MV/cm.

The drain contact 110 exhibits ohmic characteristics at the barrier interface with the barrier layer 135, forming an electrode of the drain region. The drain contact 110 includes one or more metal layers disposed on the barrier layer 135 to form the drain region of the HEMT 100. The drain contact 110 is made of aluminum or any other suitable metal, metal stack or other conductor. The drain contact 110 includes one or more contact metal layers disposed on the barrier layer 135.

The source contact 105 exhibits ohmic characteristics at the barrier interface with the barrier layer 135, forming an electrode of the source region. The source contact 105 is made of aluminum or any other suitable metal, metal stack or other conductor. The source contact 105 includes one or more contact metal layers disposed on the barrier layer 135. In some embodiments, as shown in FIG. 1, the source contact 105 extends above the barrier layer 135 in the direction of the drain contact 110, but does not contact the barrier layer 135. In some such embodiments, the extended portion of the gate contact 150 can act as a field plate to shield the gate 115 from the electric field (e.g., high electric field, such as a field having a strength above the critical field strength or above E _c ) of one or more layers of material. In some embodiments, E _c is typically equal to or about 4 MV/cm. In some embodiments, several metal layers are deposited to form the source contact 105, and as shown in FIG. 1, portions of each of the metal layers extend over the barrier layer 135 in the direction of the drain contact 110, but do not touch the barrier layer 135. In some such embodiments, the multiple extensions of the source contact 105 can act as field plates to shield the gate 115 from the electric field (e.g., high electric field, such as a field having a strength above the critical field strength or above E _c ) of one or more layers of material. In some embodiments, E _c is typically equal to or about 4 MV/cm. In some such embodiments, a dielectric 140 is deposited between the extensions of the metal layers of the source contact 105 that form the field plates, between the field plates and the gate contact 115, and between the field plates and the barrier layer 135, for example, as shown in FIG. 1 .

The dielectric 140 is a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), any other suitable dielectric material, or any suitable combination of these dielectric materials or other dielectric materials. As shown in FIG1 , the dielectric 140 is deposited over the HEMT 100 to electrically and physically separate the structure of the HEMT 100 from the environment and from each other. In some embodiments, the dielectric 140 is deposited in several layers. For example, as shown in FIG1 , the dielectric 140 is deposited in a first layer over the barrier layer 135 and the gate 115. In this embodiment, the first layer of dielectric 140 is patterned and etched or otherwise processed to expose gate 115 so that gate contact 150 can be deposited on gate 115. After gate contact 150 is deposited, a second layer of dielectric 140 is deposited to cover gate contact 150 and the first layer of dielectric 140. The layers of dielectric 140 are patterned and etched or otherwise processed so that the first layer of source contact 105 can be deposited on barrier layer 135, and a portion of source contact 105 can be deposited on the second layer of dielectric 140 to form field plate 160. Patterning, etching, and deposition of multiple layers of dielectric 140 may be performed repeatedly to produce layers of dielectric 140 and other HEMT structures as shown in FIG. 1 or any other suitable HEMT structure.

FIG2 is a cross-sectional view of the exemplary HEMT 100 shown and described with respect to FIG1 , further illustrating the presence of an electric field when the HEMT 100 is in an off state. In this embodiment, the HEMT 100 is an enhancement mode device. Thus, in the off state, the gate contact 150 and the source contact 105 are both at ground potential, while the drain contact 110 is at a relatively high potential.

In this embodiment, in the off state, the ground potential of the gate 115 prevents the 2DEG 170 from flowing from the source contact 105 through the channel layer 130 to the drain contact 110. As shown by the shading covering the HEMT 100 in FIG2 , in the off state, with a positive voltage at the drain contact 110, the electric field is stronger in the region immediately adjacent to the gate 115 (i.e., at the edge of the gate 115). It should be noted that this is true even though the field plate 160 mitigates the electric field to some extent. In some cases, the strong electric fields present at the edge of the gate 115 may cause or contribute to improper operating characteristics of the HEMT 100 and/or contribute to the capture of electrons or holes that may lead to gate and device failure. For example, in some cases, such electric fields may have the effect of lowering the device critical voltage of the HEMT 100, generating drain-source leakage current and/or gate-drain leakage current in the HEMT 100, and/or promoting gate failure during degradation or aging of the HEMT 100.

3A is a cross-sectional view of an exemplary HEMT 300. HEMT 300 includes a source contact 305, a drain contact 310, a gate 315, a substrate 320, a buffer layer 325, a channel layer 330, a barrier layer 335, a dielectric 340, a gate contact 350, and a field plate 360. HEMT 300 also includes a field plate 380 and a field plate 390.

HEMT 300 is substantially similar in structure and materials to HEMT 100 as shown and described with respect to FIGS. 1 and 2 , except that it includes two field plates, field plate 380 and field plate 390, on the surface of barrier layer 335, and structural adjustments to field plates 380 and 390. HEMT 300 includes two such field plates, however, it should be noted that in other embodiments, the HEMT may include only one such field plate, or more than two such field plates.

For purposes of example, HEMT 300 is an enhancement mode device, however, it should be noted that the principles described herein also apply to depletion mode HEMT devices. Some embodiments include a subset of the exemplary components described with respect to FIG. 3A or additional components. For example, some embodiments include a source, gate, and drain on a substrate that includes a different combination of layers, or omit the field plate.

In the embodiment of FIG3A , HEMT 300 is in an off state when gate contact 350 and source contact 305 are both at ground potential, and in an on state when gate contact 350 is above a critical voltage. Barrier layer 335 has a higher band gap than channel layer 330, thereby promoting the formation of 2DEG 370. In the on state, since drain contact 310 increases in potential relative to source contact 305, the electric field forces high mobility electrons in 2DEG 370 to migrate from source contact 305 to drain contact 310, thereby causing current to flow. The presence of the 2DEG 370 below the gate contact 350 depends on the voltage applied to the gate contact 350. Above the critical gate voltage, the 2DEG 370 is continuous between the source contact 305 and the drain contact 310. Below the critical gate voltage, the 2DEG 370 becomes depleted until the 2DEG 370 below the gate contact 350 between the source contact 305 and the drain contact 310 is disconnected. When the gate contact 150 is below the critical gate voltage, the 2DEG 370 stops flowing between the drain contact 310 and the source contact 305, thereby preventing current flow and placing the HEMT 300 into an off state.

Substrate 320 may be made of any suitable material, such as silicon (Si), an engineered substrate (e.g., QST®), silicon carbide (SiC), gallium nitride (GaN), or any other suitable material or combination of materials, such as a material capable of supporting the growth of a III-nitride material. In this embodiment, substrate 320 is made of QST. In some embodiments, a nucleation layer (not shown) may be formed on substrate 320, such as to reduce the lattice mismatch between the substrate of HEMT 300 and buffer layer 325. The nucleation layer may include any suitable material and may be formed on substrate 320 using any suitable one or more semiconductor growth techniques, such as metal oxide chemical vapor deposition (MOCVD), hybrid vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

The buffer layer 325 may be formed on the substrate 320 (or the corresponding nucleation layer). In some embodiments, the buffer layer 325 is a high-resistivity material or includes a high-resistivity material. In this case, the high-resistivity material is a material whose resistivity in the device does not cause leakage current to be higher than the desired amount (e.g., higher than the critical leakage current). In some embodiments, such materials may have a doping concentration (intentionally or unintentionally doped) of (or approximately, or about) 1×10 ¹⁵ /cm ^3. In some embodiments, the buffer layer 325 includes a doped or undoped III-nitride material layer. In this embodiment, the buffer layer 325 is made of a single layer or multiple layers of AlGaN, however, any suitable III-nitride material may be used. The buffer layer 325 may be formed on the substrate 320 (or the corresponding nucleation layer) using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE or MBE.

The channel layer 330 may be formed on the buffer layer 325. In some embodiments, the channel layer 330 includes any suitable doped or undoped III-nitride material. In this embodiment, the channel layer is made of GaN, however, any suitable III-nitride material may be used. The channel layer 330 may be formed on the buffer layer 325 using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE.

Field plate 380 can be formed on the surface of barrier layer 335 using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In some embodiments, field plate 380 is made of GaN (e.g., p-type GaN). In some embodiments, field plate 380 acts as a field plate to shield gate 315 from electric fields (e.g., high electric fields, such as fields having a strength greater than a critical field strength).

In some implementations, the field plate 380 is formed (eg, by patterning and/or etching) from the same GaN (eg, P-GAN) material layer used to form the gate 315 .

In some embodiments, the field plate 380 has a doping concentration different from the doping concentration of the gate 315. In some embodiments, the field plate 380 is doped with a doping material different from the doping material of the gate 315. In some embodiments, the field plate 380 has a doping concentration in the range of 1×10 ¹⁶ cm ³ to 1×10 ²⁰ cm ³ (e.g., 2×10 ¹⁹ cm ³ to 3×10 ¹⁹ cm ³ ). In some embodiments, the field plate 380 is substantially thinner than the gate 315. In some embodiments, the field plate 380 is or is approximately one-third to one-half the thickness of the gate 335. In some embodiments, the field plate 380 has dimensions that are different from the dimensions (e.g., length, height, width) of the gate 335. In some embodiments, the reduced thickness or different dimensions of the field plate 380 compared to the gate 315 is achieved by applying a masking and etching process to the field plate 380. In some embodiments, the field plate 380 is electrically connected to or in communication with the source contact 305 via metal, or is otherwise maintained at the same potential as the source contact 305. In some embodiments, the field plate 380 is formed of a different material than the material used to form the gate 315. For example, where the gate 315 is formed of PGaN, the field plate 380 can be formed of AlGaN.

Field plate 390 may be formed on the surface of barrier layer 335. In some embodiments, field plate 390 comprises any suitable III-nitride material. In this embodiment, field plate 390 is made of doped GaN (p-type GaN in this embodiment) grown on barrier layer 335. In some embodiments, field plate 390 has a non-uniform doping concentration (p-type in this embodiment). For example, in some embodiments, such non-uniform doping concentration may be selected to form a specific electric field and depletion region within field plate 390.

Field plate 390 can be formed on the surface of barrier layer 335 using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In some embodiments, field plate 390 is made of GaN (e.g., p-type GaN). In some embodiments, field plate 380 acts as a field plate to shield gate 315 from electric fields (e.g., high electric fields, such as fields having a strength greater than a critical field strength).

In some embodiments, the field plate 390 is formed (e.g., by patterning and/or etching) from the same GaN (e.g., P-GAN) material layer used to form the gate 315 and/or the field plate 380. In some embodiments, the field plate 390 has a doping concentration that is different from the doping concentration of the gate 315. In some embodiments, the field plate 390 is doped with a doping material that is different from the doping material of the gate 315. In some embodiments, the field plate 390 has a doping concentration in the range of 1×10 ¹⁶ cm ³ - 1×10 ²⁰ cm ³ (e.g., 2×10 ¹⁹ cm ³ ~3×10 ¹⁹ cm ³ ). In some embodiments, field plate 390 is substantially thinner than gate 315. In some embodiments, field plate 390 is or is approximately one-third to one-half the thickness of gate 335. In some embodiments, field plate 390 has dimensions that are different from the dimensions (e.g., length, height, width) of gate 335. In some embodiments, the reduced thickness or different dimensions of field plate 390 compared to gate 315 is achieved by applying a masking and etching process to field plate 390 (e.g., the same process used to achieve the thickness of field plate 380).

In some embodiments, field plate 390 floats and is not electrically connected to or in communication with source contact 105 via metal, or is otherwise held at the same potential as source contact 105. Note that field plate 390 is closer to drain 110 than field plate 380. In some embodiments with more than one such field plate, the field plate closest to the drain floats and is not electrically connected to or in communication with ground via metal. In some embodiments with only one such field plate, the single field plate floats and is not electrically connected to or in communication with ground via metal.

The gate contact 350 is an electrode that is in Schottky or Ohmic contact with the gate 315 and is formed using any suitable one or more metal deposition techniques. The gate contact 350 is made of aluminum or any other suitable metal, metal stack, or any other conductor or conductor layer. In some embodiments, these materials are configured to provide Ohmic or Schottky contact. In some embodiments, as shown in FIG. 3A , the gate contact 350 extends over the barrier layer 335 in the direction of the drain contact 310 but does not contact the barrier layer (e.g., separated by a dielectric). In some such embodiments, an extended portion of the gate contact 350 can act as a field plate to shield the gate 315 from electric fields (eg, high electric fields, such as fields having a strength greater than a critical field strength).

The drain contact 310 exhibits ohmic characteristics at the barrier interface with the barrier layer 335, forming an electrode of the drain region. The drain contact 310 includes one or more metal layers disposed on the barrier layer 335 to form the drain region of the HEMT 300. The drain contact 310 is made of aluminum or any other suitable metal, metal stack or other conductor. The drain contact 310 includes one or more contact metal layers disposed on the barrier layer 335.

The source contact 305 exhibits ohmic characteristics at the barrier interface with the barrier layer 335, forming an electrode of the source region. The source contact 305 is made of aluminum or any other suitable metal or other conductor. The source contact 305 includes one or more contact metal layers disposed on the barrier layer 335. In some embodiments, as shown in FIG. 3A, the source contact 305 extends above the barrier layer 335 in the direction of the drain contact 310, but does not contact the barrier layer 335. In some such embodiments, an extended portion of the gate contact 350 can act as a field plate to shield the gate 315 from electric fields (eg, high electric fields, such as fields having a strength greater than a critical field strength).

In some embodiments, several metal layers are deposited to form source contact 305, and as shown in FIG3A, portions of each of the metal layers extend over barrier layer 335 in the direction of drain contact 310, but do not touch barrier layer 335. In some of these embodiments, the multiple extended portions of source contact 305 can act as field plates to shield gate 315 from electric fields (e.g., high electric fields, such as fields with an intensity greater than a critical field intensity). In some of these embodiments, dielectric 340 is deposited between the extended portions of each metal layer of source contact 305 that form the field plates, between the field plates and gate contact 315, and between the field plates and barrier layer 335, for example, as shown in FIG3A.

It should be noted that in some embodiments, field plates 380 and 390 have the advantage of providing significantly more shielding of gate 315 from electric fields (e.g., being more effective in controlling the peak electric field at the edge of gate 315) than a field plate formed by field plate 360 due to, for example, their closer proximity to gate 315. Thus, in some embodiments, field plate 360 is omitted. An advantage of omitting field plate 360 may be to reduce parasitic capacitance between the metal of source contact 305 and drain contact 310.

The dielectric 340 is a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO ₂ ), aluminum oxide (Al 2 O ₃ ), or any other suitable dielectric material. As shown in FIG3A , the dielectric 340 is deposited over the HEMT 300 to electrically and physically separate the structure of the HEMT 300 from the environment and from each other. In some embodiments, the dielectric 340 is deposited in several layers. For example, as shown in FIG3A , the dielectric 340 is deposited in a first layer over the barrier layer 335 and the gate 315 . In this embodiment, the first layer of dielectric 340 is patterned and etched or otherwise processed to expose gate 315 so that gate contact 350 can be deposited on gate 315. After gate contact 350 is deposited, a second dielectric layer 340 is deposited to cover gate contact 350 and the first layer of dielectric 340. The layers of dielectric 340 are patterned and etched or otherwise processed so that the first layer of source contact 305 can be deposited on barrier layer 335, and a portion of source contact 305 can be deposited on the second layer of dielectric 340 to form field plate 360. Patterning, etching, and deposition of multiple layers of dielectric 340 may be performed repeatedly to produce layers of dielectric 340 and other HEMT structures as shown in FIG. 3A , or any other suitable HEMT structure.

FIG3B is an enlarged view of HEMT 300 showing additional structures. As shown in FIG3B , metal contact 385 is deposited on field plate 380. Metal contact 385 creates an electrical connection between field plate 380 and source contact 305 via one or more metal layers (the connection portion of metal contact 385 is not shown).

FIG4 is a cross-sectional view of the exemplary HEMT of FIG3, further illustrating the presence of an electric field when the HEMT 300 is in an off state. In this embodiment, the HEMT 300 is an enhancement mode device. Thus, in the off state, the gate contact 350 and the source contact 305 are both at ground potential, while the drain contact 310 is at a relatively high potential.

In this embodiment, in the off state, the ground potential of gate 315 prevents 2DEG 370 from flowing from drain contact 310 through channel layer 330 to source contact 305. As shown by the shading covering HEMT 300 in FIG4 , with a positive voltage at drain contact 310, in the off state, the electric field is strong in the region adjacent to field plate 390, but is substantially absent in the region of gate 315. In some cases, this is due to the shielding effect of field plate 390 and/or field plate 380. In some cases, this advantage is avoiding or reducing unsuitable operating characteristics and/or electron or hole trapping of the HEMT 300 that may otherwise be caused or contributed to by the strong electric field present at the edge of the gate 315. For example, in some cases, this advantage is avoiding reducing the device critical voltage of the HEMT 300, avoiding generating drain-source leakage current and/or gate-drain leakage current in the HEMT 300, avoiding causing gate damage during aging or aging of the HEMT 300, and/or avoiding electron or hole trapping that may cause gate and device failure.

FIG. 5 is a line graph illustrating the electric field strength at the boundary of the barrier layer 135 and the dielectric 140 in the HEMT 100 due to the electric field shown in FIG. 2. The electric field strength at the edge of the gate 115 in the direction of the drain 110 is plotted. A peak field strength of 500 is indicated. FIG. 6 is a line graph illustrating the electric field strength at the boundary of the barrier layer 335 and the dielectric 340 of the HEMT 300 due to the electric field shown in FIG. 4. The electric field strength at the edge of the gate 315 in the direction of the drain 310 is plotted. A peak field strength of 600 is indicated.

It should be noted that the distance between gate 315 and the electric field at peak field strength 600 is greater than the distance between gate 115 and the electric field at peak field strength 500. Peak field strength 600 is also lower than peak field strength 500. In some embodiments, this difference is due to the shielding effect of field plate 390 and/or field plate 380. In some embodiments, the increased distance from gate 315 to peak field strength 600 has the advantage of avoiding or reducing unsuitable operating characteristics of HEMT 300 that may otherwise be caused or contributed to by the strong electric field present at the edge of gate 315.

FIG. 7 is a line graph illustrating the electric field strength at the 2DEG 170 of the HEMT 100 due to the electric field shown in FIG. 2 . The electric field strength from the edge of the gate 115 in the direction of the drain 110 is plotted. A peak field strength of 700 is indicated. FIG. 8 is a line graph illustrating the electric field strength at the 2DEG 170 of the HEMT 300 due to the electric field shown in FIG. 4 . The electric field strength from the edge of the gate 315 in the direction of the drain 310 is plotted. A peak field strength of 800 is indicated.

It should be noted that the distance between gate 315 and the electric field at peak field strength 800 is greater than the distance between gate 115 and the electric field at peak field strength 700. In some embodiments, this difference is due to the shielding effect of field plate 390 and/or field plate 380. In some embodiments, the advantage of increasing the distance from gate 315 to peak field strength 800 is that unsuitable operating characteristics of HEMT 300 that may otherwise be caused or contributed to by the strong electric field present at the edge of gate 315 are avoided or reduced. It should be noted that in some embodiments, this is true even if peak field strength 800 is higher than peak field strength 700 (e.g., due to the increased distance from gate 315).

FIG. 9 is a plan view of HEMT 300 as shown and described with respect to FIG. 3A , FIG. 3B , and FIG. 4 . Cross-section A indicates the viewing angle as shown in FIG. 3A , FIG. 3B , and FIG. 4 . FIG. 9 omits several features of HEMT 300 for purposes of clarity. As shown in FIG. 9 , field plates 380 and 390 extend continuously and completely across (in the vertical direction, as shown in FIG. 9 ) HEMT 300 , such that any path along (in the horizontal direction, as shown in FIG. 9 ) HEMT 300 between source 305 and drain 310 passes under, within, or over field plates 380 and 390 . In some embodiments, an advantage of having field plates 380 and 390 continuous is to avoid or reduce the effect of a strong electric field on gate 315 when HEMT 300 is in the off state and the voltage at drain 310 increases.

10 is a flow chart illustrating an exemplary process 1000 for fabricating an exemplary HEMT. For example, some or all of the steps of process 1000 may be used to fabricate the HEMT 300 as shown and described above.

In this embodiment, the HEMT is formed on a substrate. The substrate may be a silicon (Si) substrate, an engineered substrate (QST), silicon carbide (SiC), gallium nitride (GaN), or may include any other material or combination of materials capable of supporting the growth of group III nitride materials. In some embodiments, the substrate 120 of the HEMT 300 corresponds to this substrate.

In step 1005, a nucleation layer is formed on the substrate material. In some embodiments, this may have the advantage of reducing the lattice mismatch between the substrate and the next layer in the HEMT. The nucleation layer may include any suitable material (e.g., aluminum nitride (AlN)) and may be formed on the substrate using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In some embodiments, forming a nucleation layer on the substrate 120 of the HEMT 300 corresponds to this step.

In step 1010, a buffer layer is formed on the nucleation layer. In some embodiments, the buffer layer is a high resistivity layer, which may include a doped or undoped III-nitride material layer. In some embodiments, the buffer layer is made of multiple AlGaN layers. The buffer layer may be formed on the nucleation layer using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In some embodiments, the buffer layer 125 of the HEMT 300 corresponds to this step.

In step 1015, a channel layer is formed on the buffer layer. In some embodiments, the channel layer is made of doped or undoped III-nitride material. In some embodiments, the channel layer is made of GaN. The channel layer can be formed on the buffer layer using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE or MBE. In some embodiments, the channel layer has a thickness in the range of hundreds of nanometers. In some embodiments, the channel layer is a high resistance layer that can be made of unintentionally doped or low-doped materials. In some embodiments, the channel layer is or includes n-type III-nitride material. In some implementations, the channel layer 130 of the HEMT 300 corresponds to this step.

In step 1020, a barrier layer is formed on the channel layer. The barrier layer may include a layer of doped or undoped Group III nitride material. The barrier layer may be formed on the channel layer using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. The thickness and composition of the barrier layer may be selected to obtain a positive critical voltage. In some embodiments, the thickness and composition of the barrier layer are selected to provide a larger bandgap than the channel layer, the barrier layer typically having AlGaN with an Al mole fraction of 0.18 to 0.23. In some such examples, the barrier layer comprises AlGaN with a thickness in the range of 12 nm to 25 nm. In some implementations, the barrier layer 135 of the HEMT 300 corresponds to this step.

In step 1025, a GaN layer is formed on the barrier layer. In some embodiments, the GaN layer comprises any suitable Group III nitride material. In this embodiment, the GaN layer is made of doped GaN (p-type GaN in this embodiment) grown on the barrier layer. In some embodiments, the GaN layer has a non-uniform doping concentration (p-type in this embodiment). In some embodiments, this non-uniform doping concentration is selected to form a specific electric field and depletion region within the GaN layer.

The GaN layer may be formed on the barrier layer 135 using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In step 1030, the GaN layer is etched to define a gate region and one or more field plate regions proximate to but not connected to the gate. In some embodiments, a mask layer is defined and the masking and etching processes are performed such that the field plate GaN region is substantially thinner than the gate GaN region. In some embodiments, the field plate GaN is one-half to one-third the thickness of the gate GaN. In some embodiments, the gate GaN region has a doping concentration in the range of 1×10 ¹⁶ cm ³ - 1×10 ²⁰ cm ³ (e.g., 2×10 ¹⁹ cm ³ -~3×10 ¹⁹ cm ³ ) and a thickness in the range of 50 nm to 150 nm. In some embodiments, the gate region 315 and the field plates 380 and 390 of the HEMT 300 correspond to this step.

In step 1035, the HEMT is electrically isolated from other inactive areas of the device or other devices on the substrate. In some embodiments, this is performed based on mesa etching or ion implantation, such as nitrogen or argon, external to the active HEMT.

In step 1040, a dielectric layer is deposited on the surface of the structure. In some embodiments, the dielectric layer is a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or any other suitable dielectric material. In some embodiments, the dielectric layer is deposited over the HEMT to electrically and physically isolate the structure of the HEMT from the environment and from each other. In some embodiments, the dielectric layer is deposited in several layers. In some embodiments, dielectric 340 of HEMT 300 corresponds to this step.

In step 1045, after masking and etching the dielectric layer, metal source and drain electrodes are formed to form ohmic contacts with the barrier layer. In some embodiments, pre-deposition and/or post-deposition treatment and annealing processes may be applied. In some embodiments, the source contact 305 and drain contact 310 of the HEMT 300 correspond to this step.

In step 1050, a metal gate electrode is formed on the GaN gate region. In some embodiments, the metal gate electrode is a Schottky or Ohmic gate metal contact to the GaN gate region after masking and etching the dielectric layer. In some embodiments, pre-deposition and/or post-deposition treatment and annealing processes may be applied. In some embodiments, the gate contact 350 of the HEMT 300 corresponds to this step. It should be noted that in some embodiments, the order of forming the source, drain, and gate metal contacts (e.g., step 1045 and step 1050) is reversible.

In step 1055, one or more field plates are formed on the barrier layer. In some embodiments, the field plates include any suitable III-nitride material, such as GaN or AlGaN. For example, in some embodiments, the field plates are made of doped GaN (p-type GaN in this embodiment) grown on the barrier layer. In some embodiments, the field plates have a non-uniform doping concentration. In some embodiments, this non-uniform doping concentration is selected to form a specific electric field and depletion region within the field plate.

In some embodiments, the field plate can be formed on the barrier layer using any suitable one or more semiconductor growth techniques, such as MOCVD, HVPE, or MBE. In some embodiments, the field plate is made of GaN (e.g., p-type GaN). In some embodiments, the field plate shields the gate region and/or gate contact from electric fields (e.g., high electric fields, such as fields with an intensity greater than a critical field intensity). In some embodiments, the field plate is formed (e.g., by patterning and/or etching) from the same GaN (e.g., p-GAN) material layer used to form the GaN gate region.

In some embodiments, the field plate has a doping concentration that is different from the doping concentration of the gate region. In some embodiments, the field plate is doped with a doping material that is different from the doping material of the gate region. In some embodiments, the field plate has a doping concentration in the range of 1×10 ¹⁶ cm ³ to 1×10 ²⁰ cm ³ (e.g., 2×10 ¹⁹ cm ³ to 3×10 ¹⁹ cm ³ ). In some embodiments, the field plate is substantially thinner than the gate region. In some embodiments, the thickness of the field plate is or is approximately one-third to one-half of the gate region. In some embodiments, the field plate has a size that is different from the size (e.g., length, height, width) of the gate region. In some embodiments, the reduced thickness or different size of the field plate compared to the gate region is achieved by applying masking and etching processes to the field plate.

In some implementations, field plate 380 and field plate 390 of HEMT 300 correspond to this step.

In step 1060, one or more of the field plates are electrically connected to a reference voltage. In some embodiments, some of the field plates are electrically connected to or in communication with the source contact 305 via metal, or are otherwise maintained at the same potential as the source contact 305, and other field plates are floating and not connected to a fixed voltage source or reference voltage. In some embodiments, the field plate from the plurality of field plates closest to the drain region is floating, and one or more of the other field plates are electrically connected to a reference voltage, such as the source or ground. In some embodiments, there is only one field plate, which is floating. In some embodiments, the field plate closest to the gate is at ground (i.e., source potential), for example to prevent the field plate from acquiring an excessively high potential.

In step 1065, a dielectric layer (e.g., SiN, SiO ₂ , or Al ₂ O ₃ ) is deposited over the barrier region between the gate and the source, between the gate and the field plate, between the field plate and the drain, and partially on the source and drain. In some embodiments, the dielectric layer electrically and physically isolates the structure of the HEMT from the environment and from each other. In some embodiments, the dielectric layer is deposited in several layers. In some embodiments, the dielectric 340 of the HEMT 300 corresponds to this step.

It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in particular combinations, each feature or element may be used alone without other features and elements or in various combinations with or without other features and elements.

100: High Electron Mobility Transistor (HEMT) 105: Source Contact 110: Drain Contact 115: Gate 120: Substrate 125: Buffer Layer 130: Channel Layer 135: Barrier Layer 140: Dielectric 150: Gate Contact 160: Field Plate 170: Two-Dimensional Electron Gas (2DEG) 300: High Electron Mobility Transistor (HEMT) 305: Source Contact 310: Drain Contact 315: Gate 320: Substrate 325: Buffer Layer 330: Channel Layer 335: barrier layer 340: dielectric 350: gate contact 360: field plate 370: two-dimensional electron gas (2DEG) 380: field plate 385: metal contact 390: field plate 500: peak field strength 600: peak field strength 700: peak field strength 800: peak field strength 1000: step process 1005: step 1010: step 1015: step 1020: step 1030: step 1035: step 1040: step 1045: step 1050: step 1055: Step 1060: Step 1065: Step A: Cross section

A more detailed understanding may be obtained from the following description given by way of example in conjunction with the accompanying drawings, in which:

[FIG. 1] is a cross-sectional view of an exemplary HEMT;

[FIG. 2] is a cross-sectional view of the exemplary HEMT of FIG. 1, showing the electric field distribution;

[FIG. 3A] is a cross-sectional view of another exemplary HEMT;

[FIG. 3B] is an enlarged view of a portion of FIG. 3A, showing details of the exemplary HEMT of FIG. 3A.

[FIG. 4] is a cross-sectional view of the exemplary HEMT of FIG. 3A and FIG. 3B , illustrating electric field distribution;

FIG. 5 is a line diagram illustrating the field intensity at the AlGaN region of the HEMT of FIGS. 1 and 2 , corresponding to the electric field shown in FIG. 2 ;

FIG. 6 is a line diagram illustrating the field intensity at the AlGaN region of the HEMT of FIG. 3A , FIG. 3B and FIG. 4 , corresponding to the electric field shown in FIG. 4 ;

FIG. 7 is a line diagram illustrating the field intensity in the two-dimensional electron gas (2DEG) region of the HEMT of FIG. 1 and FIG. 2 , corresponding to the electric field shown in FIG. 2 ;

FIG. 8 is a line diagram illustrating the field intensity at the 2DEG region of the HEMT of FIG. 3A , FIG. 3B and FIG. 4 , corresponding to the electric field shown in FIG. 4 ;

FIG. 9 is a plan view of the HEMT of FIG. 3A , FIG. 3B and FIG. 4 ; and

[ FIG. 10 ] is a flow chart illustrating exemplary steps for fabricating an exemplary HEMT.

100: High Electron Mobility Transistor (HEMT)

105: Source contact

110: Drain contact

115: Gate

120: Substrate

125: Buffer layer

130: Channel layer

135: Barrier layer

140: Dielectric

150: Gate contact

160: Field board

170: Two-dimensional electron gas (2DEG)

Claims (20)

A high electron mobility transistor (HEMT) comprising: a source disposed on a surface; a drain disposed on the surface; a gate disposed on the surface between the source and the drain; and a first field plate disposed on the surface between the gate and the drain. A high electron mobility transistor as claimed in claim 1, wherein the first field plate comprises doped gallium nitride (GaN). A high electron mobility transistor as claimed in claim 1, wherein the first field plate is at a floating voltage. A high electron mobility transistor as claimed in claim 1, wherein the first field plate is not electrically connected to a voltage source. The high electron mobility transistor of claim 1, further comprising a second field plate disposed on the surface between the gate and the first field plate. A high electron mobility transistor as claimed in claim 5, wherein the second field plate is electrically connected to a voltage source. A high electron mobility transistor as claimed in claim 5, wherein the second field plate is electrically connected to the source. A high electron mobility transistor as in claim 1, wherein the first field plate comprises GaN and has a different dopant concentration, a different dopant type, or a different dopant material than the gate. A high electron mobility transistor as in claim 1, wherein the first field plate comprises a doping concentration, doping material, geometry and/or position configured to minimize an increase in the on-resistance of the high electron mobility transistor. A high electron mobility transistor as claimed in claim 1, wherein the first field plate is continuous. A high electron mobility transistor as claimed in claim 1, wherein the first field plate extends continuously between the source region and the drain region and parallel to the source region and the drain region, so that any path from the source to the drain passes below, inside or above the first field plate. A high electron mobility transistor as in claim 1, wherein the first field plate extends continuously over the entire width of the surface between the source and the drain. A high electron mobility transistor as claimed in claim 1, wherein the first field plate is closer to the gate than to the drain. A high electron mobility transistor as claimed in claim 1, wherein the first field plate comprises p-type doped GaN (P-GaN). A high electron mobility transistor as claimed in claim 1, wherein the first field plate comprises p-type doped aluminum gallium nitride (AlGaN) or n-type doped AlGaN. A method for manufacturing a high electron mobility transistor (HEMT), the method comprising: depositing a gate material on a surface between a source and a drain; and depositing a first field plate material on the surface between the gate material and the drain. The method of claim 16, wherein the gate material and the first field plate material comprise doped gallium nitride (GaN). The method of claim 16, wherein the first field plate material extends continuously across the surface between the source and the drain such that any path from the source to the drain passes below, within, or above the first field plate material. The method of claim 16, wherein the first field plate material comprises p-type doped GaN (P-GaN). The method of claim 16, wherein the first field plate material comprises p-type doped aluminum gallium nitride (AlGaN) or n-type doped AlGaN.

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