TW202425451A - Power module with decentralized staggered conductive busbar and low parasitic inductance capable of creating individual inductances that cancel each other, and reducing an overall parasitic inductance, through a plurality of interdigitated contact ports provided on busbars - Google Patents

Abstract

A power module with decentralized staggered conductive busbars and low parasitic inductance, which comprises at least one base extending along the length direction, equipped with at least one current input and output busbar, and each formed with a plurality of interdigitated contact ports; a first unit, which has a first circuit base arranged on the above-mentioned base along the width direction. A plurality of first power modules are arranged on the first circuit base that also have respective first current input terminals and respective first current output terminals connected in parallel with each other. The first current input terminals and the first current output terminals are connected to the first circuit base and a second unit. As the current passes through the units and the respective interdigitated contact ports, it forms individual inductances that cancel each other, so that an overall parasitic inductance is reduced. Therefore, the invention creates individual inductances that cancel each other, and reduces the overall parasitic inductance.

Description

Power module with distributed cross-conductivity bus and low parasitic inductance

The present invention is a power module, in particular a power module with a distributed staggered conductive bus and low parasitic inductance.

The third generation of semiconductors is currently a hot high-tech field, playing a vital role in the development of 5G, electric vehicles, and renewable energy. The so-called third generation semiconductors, also known as "wide bandgap semiconductors", generally refer to silicon carbide (SiC) or gallium nitride (GaN), whose bandgap is about three times that of traditional semiconductors silicon (Si) and gallium arsenide (GaAs). They can be used in high-frequency, high-temperature, high-current, and high-voltage operating environments, and generally have excellent performance and stability.

Among the many application fields of third-generation semiconductors, the demand for electric vehicles is undoubtedly the main driving force for power semiconductor components. The core technology of electric vehicles lies in "batteries, motors and electronic controls". The following is a brief explanation: First, the three-phase motor is the heart of the electric vehicle. It uses the generation of a rotating magnetic field (RMF, Rotating Magnetic Field) to drive the rotor inside the motor and then drive the axle. In order to generate a rotating magnetic field, the three-phase motor needs to use AC with phase difference as power. However, the battery pack equipped in electric vehicles, such as lithium batteries, is a DC power source, which means that DC and AC conversion is required between the battery and the motor. This conversion is achieved by the brain of the electric vehicle - the inverter.

The function of the inverter is not only to convert the input current into an AC signal, but also to regulate the three-phase motor through technologies such as Pulse Width Modulation (PWM). In essence, the inverter is a power module that includes the above-mentioned power semiconductors and realizes electronic control of the motor through circuit design. For example, the faster the rotating magnetic field rotates, the faster the rotor in the motor will rotate. The speed of the rotating magnetic field is determined by the frequency of the AC signal. In other words, electric vehicles only need to control the frequency of the input current to directly change the motor speed, which provides a more reliable and linear control method compared to the mechanism of traditional internal combustion engines. In addition, the input current of the motor also directly affects the strength of the magnetic field generated. For electric vehicles with high power output, power modules that can handle large currents are necessary.

In an AC circuit, current flowing through a wire or component will generate a time-varying magnetic field according to Ampere's law. According to Faraday's law of induction and Lenz's law, this time-varying magnetic field will generate an opposing induced electromotive force, affecting the current signal. The above effect is similar to inductance, so it is generally called "parasitic inductance" or "stray inductance". This unexpected parasitic inductance is not desirable in practice because it will hinder the rapid change of the current signal. Usually, this effect can be ignored when the frequency is not high, but under high-frequency and high-current operating conditions, the influence of inductance becomes increasingly serious, which may cause the phase delay or lead of the signal, distort the overall signal, affect the transmission and conversion efficiency, reduce stability, and significantly affect the efficiency of the motor in converting electrical energy into mechanical energy.

In US Patent No. 10405450, it is disclosed that parasitic inductance in high-power modules causes problems such as voltage shooting and ringing. In addition, for parallel-mounted power modules, there is also the problem of uneven temperature caused by current imbalance. The above factors will cause circuit system instability, reduce conversion efficiency, and even limit the maximum switching frequency. Therefore, as shown in Figure 1, the case proposes to reduce the circuit length, increase the conductor cross-sectional area, generate a destructive magnetic field, reduce the module height, and make the power module closer to the end point. After the current passes through two power components 7 along the current direction 8, a return area 9 is formed at the output bus, which can reduce the parasitic inductance generated locally. However, this layout method is limited in its ability to reduce parasitic inductance because the output bus located in the upper center of the figure can only be close to the circuit below in the local area of the center, and the right side of the figure must avoid the wire bonding area and must maintain a distance. As shown in Figure 2, US Patent No. USP 8637964 also attempts to disclose a low stray inductance power module. By making the return current as close to the original current path as possible in the circuit design, the current direction 8 also forms a return path in the power module. However, this horizontal double-loop layout will cause uneven current under high current and high frequency conversion because the distances between the inner and outer loops of each loop are different, and the distances between the inner and outer loops in the outer loops are relatively far, which limits the effect of the inductance offsetting each other.

In summary, parasitic inductance is a problem that must exist in high-frequency circuits and that the industry wants to get rid of as soon as possible. In order to overcome this problem, the inventor has already conducted research and development on the return path in the power module and filed an earlier invention patent application. However, in subsequent research, further research found that the power module disclosed by the present invention still has room for further optimization.

One purpose of the present invention is to provide a power module with low parasitic inductance. The interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus will form individual inductances that cancel each other out when current passes through, so that the overall parasitic inductance is further reduced.

Another purpose of the present invention is to provide a power module with low parasitic inductance, which connects large current signals in parallel and facilitates circuit output through a bus structure that is dispersed and located on the same side.

Another purpose of the present invention is to provide a power module with low parasitic inductance, which makes the circuit structure design of the power module with low parasitic inductance more flexible through the staggered distributed configuration of horizontal and vertical allocation transformation.

According to the above-mentioned case, a low parasitic inductance power module is disclosed for use in equipment requiring high-frequency and high-power input, such as electric vehicle motors. The low parasitic inductance power module includes: at least one base extending along a length direction and having two opposite sides in the length direction, at least one current input bus and at least one current output bus insulated from each other are arranged at one of the two opposite sides, and the current input bus and the current output bus are respectively formed with a plurality of interdigitated contact ports; a first unit, The invention comprises at least one first circuit base, on which a plurality of first power elements are arranged, each of which has a first current input terminal connected in parallel with each other and a first current output terminal connected in parallel with each other; wherein one of the first current input terminal or the first current output terminal is connected to the first circuit base by conductive connection; and a second unit, comprising at least one second circuit base, and the second circuit base is spaced from the first circuit base, on which a plurality of second power elements are arranged. The power element is a power element, each of the second power elements has a second current input terminal connected in parallel and a second current output terminal connected in parallel; wherein the second current input terminal or the second current output terminal is conductively mounted to the second circuit base; wherein the first unit and the second unit are connected in series via a plurality of series conductive elements at one end, and the first unit and the second unit are connected in series at opposite ends to each other via a plurality of input conductive elements and a plurality of output conductive elements dispersedly arranged. The forked contacts of the current input bus and the current output bus are respectively connected in series to the current input bus and the current output bus; wherein, when the forked contacts of the current input bus and the forked contacts of the current output bus correspond to each other in the length direction, the projections of the planes formed in the length direction and the width direction are arranged in pairs and staggered and dispersed; thereby, the forked contacts of the current input bus and the forked contacts of the current output bus will form individual inductances that cancel each other when current passes through, so that the overall parasitic inductance is reduced.

The low parasitic inductance power module disclosed in the present invention is configured such that when the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus are positioned in the length direction, the projections of the planes formed in the length direction and the width direction are arranged in pairs and staggered and dispersed with each other; thereby, the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus will form a mutual staggered and dispersed arrangement when the current passes through. The individual inductance is eliminated, so that the parasitic inductance of the bus part before and after the return circuit of the whole power module is further reduced, and the power semiconductors such as SiC and GaN connected in parallel are matched to each other to distribute the large current signal of the input module; each power semiconductor is further matched with multiple wires distributed in the above width direction, and the long direction is connected to provide large current dispersion and stable input and output; the induced magnetic field generated by a wire will be The parasitic inductance effect caused by high-frequency current is effectively reduced by the dispersed and staggered design of the wires. In particular, whether it is staggered in the width direction or the height direction, or even staggered in the width and height directions at the same time, for users with different structural needs, their height restrictions or width restrictions can be flexibly met to produce high-frequency response and excellent electrical performance. The power module can effectively reduce the adverse effects of parasitic inductance; and the current input bus and the current output bus are closely and staggeredly arranged on the same side, which not only enables the high-frequency, high-current power module to obtain better electrical performance and not be interfered by the inductance and degrade the performance, but also makes the arrangement and configuration of the current input bus and the current output bus easy to derive, achieving the above-mentioned purpose that the present invention wants to achieve.

1. 1”: Power module

2: Base

20, 20’, 20”: Current input bus

22, 22’, 22”: Current output bus

200, 220, 200’, 220’, 200”, 220”: forked contact port

3: Unit 1

3’, 30, 30’, 30”: Base of the first circuit

32, 32’, 32”: First power element

34: First current input terminal

36: First current output terminal

300, 300’, 300”: First welding port

4, 4’, 40, 40’, 40”: Second circuit base

42, 42’, 42”: Second power element

44: Second current input terminal

46: Second current output terminal

402’: Metal circuit layer

50: Conductive parts connected in series

52: Input conductive parts

54: Output conductive parts

56: Elevated board

60: Magnetic field integration path

70: Base of the third circuit

70’, 70”: Elevated output circuit board

700, 700’, 700”: Second welding port

X: Length direction

Y: width direction

Z: height direction

7: Power components

8: Current direction

9: Reflux area

Figure 1 is a schematic diagram of a learning technique.

Figure 2 is a schematic diagram of another learning technique.

FIG3 is a three-dimensional structural schematic diagram of the first preferred embodiment of the forked contact port of the present invention, illustrating that the forked contact ports of the current input bus and the forked contact ports of the current output bus are single-interlaced.

Figure 4 is a top view schematic diagram of the first preferred embodiment of the present invention, illustrating how the projections of the input conductive element, the output conductive element, and the series conductive element on the plane formed in the length and width directions are scattered and staggered.

FIG5 is a schematic side view of the embodiment of FIG4, illustrating how the busbars are positioned in the length direction to correspond to each other during the circuit traversal process, so that the noise cancels out.

FIG6 is a schematic diagram of the current path projection of the embodiment of FIG4, illustrating the principle of parasitic inductance cancellation.

FIG7 is a schematic top view of a power module of the second preferred embodiment of the structure of FIG3, illustrating the width and height position of the first welding port and the second welding port.

FIG8 is a three-dimensional structural schematic diagram of the second preferred embodiment of the forked contact port of the present invention, illustrating that the forked contact ports of the current input bus correspond to the forked contact ports of the current output bus in pairs and staggered.

FIG9 is a schematic top view of the embodiment of FIG8, illustrating the width and height position of the first welding port and the second welding port.

FIG10 is a schematic diagram of the three-dimensional structure of the third preferred embodiment of the forked contact port of the present invention, illustrating that each forked contact port of the current output bus is located on both sides of each forked contact port of the current input bus.

FIG11 is a schematic top view of the embodiment of FIG10, illustrating the width and height position of the first welding port and the second welding port.

The relevant technical content, features and effects of this case will be clearly presented in the following detailed description of the preferred embodiment with reference to the drawings. The same components in each embodiment are marked with similar numbers.

The first preferred embodiment of the low parasitic inductance power module 1 of the present case, as shown in Figures 3 to 6, includes a base 2, a current input bus 20 and a current output bus 22, the current input bus 20 is formed with a plurality of finger-shaped contact ports 200, and the current output bus 22 is formed with a plurality of finger-shaped contact ports 220, for the overall large current signal (tens to hundreds of amperes) to be connected and input to each power element. For the sake of convenience, the vertical direction of Figure 4 is defined as a length direction X, and the horizontal direction in the figure is also defined as a width direction Y, and the direction perpendicular to the paper is a height direction Z. The base 2 in this example adopts a ceramic layer substrate of a dielectric material, so that a heat sink can be set on the lower side of the power element (not shown).

For the sake of convenience, in this example, the ends of the current input bus 20 and the current output bus 22 soldered to the base are respectively divided into four interdigitated contact ports 200 and 220. In particular, as shown in FIG5 , when the lengthwise positions correspond, the projection on the plane formed by the lengthwise and widthwise directions will form that between every two interdigitated contact ports 200 of the current input bus, there must be one interdigitated contact port 220 of the current output bus, so that the two are arranged in pairs and staggered and dispersed. Therefore, from the top view of FIG. 4 , when each first soldering port 300 is used to solder one of the interdigitated contact ports 200 of the current input bus 20, and each second soldering port 700 is used to solder one of the interdigitated contact ports 220 of the current output bus 22, the plurality of first soldering ports 300 formed by the first circuit base 30 and the plurality of second soldering ports 700 formed by the third circuit base 70 are separated from each other and have corresponding intervals, and are arranged in pairs in a staggered manner in the projection of the plane in the length and width directions. Thus, the interdigitated contact ports 200 of the current input bus 20 and the interdigitated contact ports 220 of the current output bus 22 will form individual inductances that cancel each other out when current passes through, so that the parasitic inductance of the bus portion before entering the substrate and after leaving the substrate is reduced.

In addition, the first unit 3 is connected to the current input bus 20. The first unit 3 includes a first circuit base 30 extending along the width direction Y. For example, eight first power elements 32 are welded and arranged side by side on the first circuit base 30. The first power elements 32 are illustrated as power transistors made of SiC in this example. Of course, in other embodiments, other power transistors can be selected according to application requirements, and the quantity can also be adjusted. Therefore, the example description of this case should not become a limiting condition. The first circuit base 30 in this example is illustrated as four metal circuit layers formed side by side in the width direction on the base 2, which are defined as input conductors 52. When the input current enters the first welding port 300 from the interdigitated contact port 200 of the current input bus 20, it will be input to the first power element 32 through a plurality of input conductors 52 connected in parallel to each other. For ease of explanation, the electrode on the bottom side of the first power element 32 that is welded and connected to the current input bus 20 is defined as the first current input terminal 34. After the input current is driven and turned on by the gate (unnumbered) of the first power element 32, it reaches the first current output terminal 36 located on the top surface of the first power element 32. And the welding is dispersed to dozens of wires, so the input current of tens to hundreds of amperes can be evenly distributed, effectively alleviating the current thermal effect of each conductive component.

In the first unit 3 of this example, each first power element 32 is synchronously controlled by a first gate signal. When the aforementioned gate signal acts, the source (Source) and the collector (Drain) of each power transistor are connected, and the input current signal is transmitted to the second circuit base 40 formed on the base 2 through a plurality of first current output terminals 36 connected in parallel, connected to the series conductive element 50, and then flows into the eight second power elements 42 connected in parallel through the second current input terminal 44. It is also explained that the current signal flows out of the first power element 32 through the series conductive element 50, which in this example is a total of forty aluminum strips as conductors, and the first current output terminal 36 of each first power element 32 is welded with five aluminum strips in parallel.

The eight second power elements 42 are synchronously controlled by the second gate signal to drive the source and collector of each power transistor to conduct. The output current is transmitted from the second current output terminal 46 through the example of forty aluminum strips to a raised plate 56 above the second circuit base 4, and then through the output conductive member 54 including twenty aluminum strips to the four parallel second welding ports 700 on the third circuit base 70, and finally flows out from the interdigitated contact port 220 of the current output bus 22.

It can be seen that if the three-dimensional coordinates of each circuit or conductor are gradually defined in the length direction of X, the projections of the forked contact ports 200 and 220 of the adjacent current input bus 20 and the current output bus 22 in the corresponding positions where the coordinates in the length direction match, will be staggered and dispersed one by one in the top view plane formed by the length and width directions, while the projections on the side view plane formed by the length and height directions will partially overlap and stagger. Therefore, the parasitic inductances cancel each other out as shown in Figure 6, so that the overall inductance of the module using the dispersed staggered conductive bus circuit structure of the present invention can be reduced by one third compared with the more than ten nH of the control group.

Of course, as in the present embodiment, the input conductive element 52 and the third circuit base 70 are coplanar with each other, and the projections from the XY plane are also staggered in pairs; and the aluminum strips of the series conductive element 50 and the output conductive element 54 are not only scattered and staggered in the projections from the XY plane, but also partially cross in the projections from the XZ plane. The elevated plate 56 is even stacked on the second circuit base 40 below, so that the projections from the XY plane completely overlap, so that the current flowing through the elevated plate 56 and the second circuit base below generate a distribution relationship of current completely dispersed and corresponding, that is, at the same coordinate position along the length direction X, the inflow current and the outflow current almost completely go through the same dispersed corresponding path, and at Each projection surface generates multiple intersections, that is, if it is not in the XY plane, it is in the XZ plane, there will inevitably be relative currents with overlapping projections, and through the corresponding distribution of such dispersed and interlaced current paths, as shown in Figure 6, each group of current paths that are opposite to each other will be based on Ampere's law, and the magnetic field path integral of the closed loop is proportional to the current passing through the closed loop. It can be obtained that the magnetic field integral path 60 is zero at the closed loop containing four currents, achieving the effect of eliminating local inductance, and complementing the dispersed and interlaced pairs of conductive buses of the present invention, which can further reduce the overall parasitic inductance of the power module.

In this example, although the conductive part does not simply extend along the X direction, it will have components in the width direction Y and the height direction Z when the circuit board is routed or the aluminum strip is welded. However, those familiar with this field should understand that this staggered dispersion loop design can still ensure a sufficiently uniform distribution of the overall current on the one hand, while maintaining a very close round-trip loop structure in three-dimensional space, so that the inductance of the overall power module can be reduced to below 5nH, and can even perfectly reach below 2nH. Compared with the long-distance loop design of the previous proposal, not only is the current distribution more uniform, but through the analysis of Ampere's law, it also has a much smaller integration path than the previous proposal, and there is no need to expand the integration area to cover the cross-section of the entire module; in other words, even if the previous proposal proposed a theoretical concept of reducing stray inductance, the round-trip current distribution area is too large, which not only causes uneven current, but also makes the calculation cross-section area for the stray inductance to cancel out very wide, and the actual effect of eliminating the induced magnetic field is limited. This is the excellent effect of the dispersed staggered design of this proposal on eliminating parasitic inductance.

For the convenience of explanation, in this embodiment, the current inflow path is defined as the current inflow half from the current input bus 20 through the first unit 3 and the series conductive element 50 to the second circuit base 40; in contrast, the current outflow half from the second circuit base 40 through the second power element 42, the elevated plate 56 and the output conductive element 54 to the current output bus 22. It can be clearly seen that the current in the inflow half and the current outflow half not only correspond to each other in space, but also the current path is fully dispersed, and even forms a projection surface staggered in multiple places, so that the paired round-trip paths are paired and close enough. This structural arrangement also makes the conductive element have an excellent structure of back and forth pairs of dispersed and staggered.

Even though the first circuit base 30, the second circuit base 40 and the third circuit base 70 of the above embodiment are all isolated and independent circuit blocks located on a ceramic substrate, the circuit configuration of the present invention is not limited to the above scheme. The power module 1' of the second preferred embodiment of the present invention is shown in FIG7, wherein the same parts as the first preferred embodiment such as the first circuit base 30', the second circuit base 40', the first soldering port 300', the first power element 32', the second power element 42', and the metal circuit layer 402' for soldering the second power element 42' are not further described. The main difference between this embodiment and the previous embodiment is that the third circuit base of this embodiment is an elevated output circuit board 70' stacked on the first circuit base 30'. In this example, a direct bonded copper (DBC) circuit board is used as an example, and the second solder port 700' is formed on the elevated output circuit board 70'. Therefore, when the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus correspond to each other in the length direction, the plurality of first soldering ports 300' and the plurality of second soldering ports 700' formed by the first circuit base 30' are not only separated from each other but also arranged in pairs at intervals and slightly staggered in the height direction. From the projection on the length and width planes, it can be seen that they are arranged in pairs in an alternating and dispersed manner, while from the projection on the length and height planes, they are partially overlapped and interdigitated. In this way, the interdigitated contacts of the current input bus and the interdigitated contacts of the current output bus will form individual inductances that cancel each other out when current passes through them, so that the overall parasitic inductance is effectively reduced from the input bus and the output bus due to the dispersed interleaving.

The forked contact ports of the current input bus and the current output bus are arranged in a staggered manner in pairs. The three-dimensional structure schematic diagram of the forked contact ports of the second preferred embodiment of the present invention is shown in FIG8, and the corresponding power module 1' is shown in FIG9. The configuration of the first circuit base 3' and the second circuit base 4' of the second embodiment is similar to that of the forked contact ports 20' and the current output bus 22'. 00' and 220' are arranged in pairs in a staggered manner, and each second soldering port 700' is also arranged in pairs on the elevated lead-out circuit board 70'. Each pair of first soldering ports 300' and each pair of second soldering ports 700' are arranged in a staggered manner, so that when the current passes through, it will form individual inductances that cancel each other out, so that the overall parasitic inductance is reduced. However, the parasitic inductance reduction efficiency of this embodiment is slightly inferior to the aforementioned embodiment in which the interdigitated soldering ports are independently staggered.

The schematic diagram of the three-dimensional structure of the interdigitated contact port of the third preferred embodiment of the present invention is shown in Figures 10 and 11. In the corresponding power module 1', the configuration of the first circuit base 3' and the second circuit base 4' is the same as the second embodiment. The interdigitated contact ports 200" of the current input bus 20" are four completely adjacent to each other in a single group, and the interdigitated contact ports 220" of the current output bus 22" are in pairs. The second soldering ports 700' on the elevated circuit board 70' of the third circuit base are also arranged in four pairs in a row, and the first soldering ports 300' of each group on the first circuit base 30' are located in pairs on both sides of the second soldering port 700', so that the overall parasitic inductance is reduced. Of course, the parasitic inductance reduction effect of this example is slightly inferior.

The current input bus, current output bus and power module disclosed in the present invention not only form individual inductances that cancel each other out when current passes through the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus, but also reduce the overall parasitic inductance. In addition, the circuits and power elements connected in parallel as in the inventor's previous application can be combined with the present invention to achieve a better effect of reducing inductance; and the large input current is evenly shared by multiple interdigitated contact ports that are dispersedly arranged and have corresponding paths, ensuring the uniform distribution of the current flow process; and the circuit forms a dispersed loop inside the module with paths that are staggered and correspond to each other and are close to overlapping. This dispersed and staggered conduction method can significantly reduce the parasitic inductance effect. In this way, the module of the present invention can reduce the parasitic inductance to less than 5nH, especially when the input bus and the output bus are arranged on the same side, which is convenient for circuit output. The description of the above embodiments is only for the convenience of understanding and is not restrictive. Any equivalent effects and other changes and modifications produced according to the following claim structure of this case are within the scope of the patent covered by this case.

20: Current input bus

200: Forked contact port

22: Current output bus

220: Forked contact port

Claims (5)

A power module with a dispersed staggered conductive bus and low parasitic inductance, comprising At least one base extending along a length direction and having two opposite sides in the aforementioned length direction, at one of the two opposite sides corresponding to the aforementioned two opposite sides is provided with at least one current input bus and at least one current output bus insulated from each other, and the above-mentioned current input bus and the above-mentioned current output bus are respectively formed with a plurality of interdigitated contact ports; A first unit, comprising at least one first circuit base, on which a plurality of first power elements are arranged, each of which has a first current input terminal connected in parallel with each other and a first current output terminal connected in parallel with each other; wherein one of the first current input terminal or the first current output terminal is connected and mounted to the first circuit base; and A second unit, comprising at least one second circuit base, and the second circuit base is spaced apart from the first circuit base, and a plurality of second power elements are arranged on the second circuit base, each of the second power elements having a second current input terminal connected in parallel with each other and a second current output terminal connected in parallel with each other; wherein one of the second current input terminal or the second current output terminal is connected and mounted to the second circuit base; Wherein, the aforementioned first unit and the aforementioned second unit are connected in series with each other at one end through a plurality of series conductive elements, and the aforementioned first unit and the aforementioned second unit are connected in series to the aforementioned current input bus and the aforementioned current output bus respectively through a plurality of input conductive elements and a plurality of output conductive elements dispersedly arranged at the opposite ends of the series connection; Among them, when the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus correspond to each other in the length direction, the projections of the planes formed in the length direction and the width direction are arranged in pairs and staggered and dispersed with each other; thereby, the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus will form individual inductances that cancel each other when current passes through, so that the overall parasitic inductance is reduced. A power module with a dispersed staggered conductive bus and low parasitic inductance as described in claim 1, wherein the base is a dielectric layer, and the first circuit base and the second circuit base are metal circuit layers formed on the dielectric layer and insulated from each other. As described in claim 2, a power module with dispersed staggered conductive buses and low parasitic inductance, wherein when the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus correspond to each other in the longitudinal direction, the first circuit base and the second circuit base are respectively formed with a plurality of first welding ports and second welding ports separated from each other and correspondingly spaced, and arranged in an interdigitated manner in the projections of the planes formed in the longitudinal direction and the width direction, for welding and connecting the interdigitated contact ports of the current input bus and the interdigitated contact ports of the current output bus, respectively. A power module with a dispersed staggered conductive bus and low parasitic inductance as described in claim 1, wherein the base is an insulating base, and the first circuit base and the second circuit base are two circuit boards respectively disposed on the insulating base. As described in claim 4, the power module with dispersed staggered conductive busbars and low parasitic inductance, wherein when the interdigitated contact ports of the current input busbar and the interdigitated contact ports of the current output busbar correspond to each other in the longitudinal direction, the first circuit base and the second circuit base are respectively formed with a plurality of first welding ports and second welding ports separated from each other and correspondingly spaced, and arranged in a staggered and dispersed manner in the projections of the planes formed in the width and height directions and the longitudinal directions, for welding and connecting the interdigitated contact ports of the current input busbar and the interdigitated contact ports of the current output busbar, respectively.

Images