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Application filed by United Microelectronics CorpfiledCriticalUnited Microelectronics Corp
Priority to TW84107066ApriorityCriticalpatent/TW264546B/en
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Publication of TW264546BpublicationCriticalpatent/TW264546B/en
A computer system comprises: one central processing unit; one system kernel logical circuit including memory refreshing counter of one dynamic random access memory; one subsystem of dynamic random access memory; one local bus that connects the central processing unit with system kernel logical circuit; one memory address bus that the system kernel logical circuit with dynamic random access memory subsystem; and one system bus; It features that the system kernel logical circuit connects the memory address bus to the system bus through one set of buffer, when the counter periodically sends memory refreshing address signal to the dynamic random access memory subsystem, the set of buffer is enabled, in order to transfer those memory refreshing address signal to the system bus.
TW84107066A1995-07-081995-07-08Memory refreshing path for computer system
TW264546B
(en)
A pipelined microprocessor that makes memory requests to the cache memory and to the external memory controller during the same clock cycle (A Pipelined Microprocessor that Makes Memory Requests to a Cache Memory and an External Memory Controller During the Same Clock Cycle)