A7 B7 ^8164 五、發明説明（l ) 【發明赞景】 本發明條關於半導體積體電路，特別是一電源供應電 避轉換電路供轉換外部電源供應電壓至内部電源供應電® 以産生一最佳的内部電源供應電壓。 近幾年來，當半導體記憶體裝置之密度係以高速率增 加，每一 ·元件之尺寸，諸如電晶體，偽愈形精減。結果， 内部電壓位準早己依元件尺寸裁減之比例而降低。因此， 為：r包含内部電路的穩定且可靠之操作過程，提供至每一 元件的操作電歷位準必須被降低。針對此點，電源供應電 ®偽廣泛地安裝於半導體記億裝置之中以轉換此裝置外部 之外部電源供應電壓而至内部電源供應電壓。 第1圖係一電路圖顯示一傳統電源供應電蹈轉換電路 ，而第^圖傜一波形顯示第1圖中電源供應電壓轉換電路 之特性。 第1圖之電源供應電壓轉換電路，一般條構築以電流 鏡型態。如同眾所皆知的，此電路型態擔任一差動放大器 。於第1圖中，-=*參考電歷VREF及一内部電源供應電壓 k 丄NT. VCC均被接收於此電路之内且一放電晶體18根據節點 N4之狀態而執行放會操作。藉此，介於參考電壓VREF與内 部電源供應電壓INT. VCC間之差值像被放大。 在第1圖的結構之中，其係提供P-通道（p-channei )MOS電晶體4與8，且源極端(source terminal)分別接 至外部電源供應電歷EXT· VCC而蘭極端（sate terminal) 貝丨J互相相接；-η-通道（n-channei) HOS電晶體14其汲極 —2 — 本紙張尺度逋用中國國家揲準（CNS ) A4規格（210X297公釐） 11 裝 ―訂 —II 一 線 (請先閱讀背面之注$項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 ^68164 A7 ___B7___ 五、發明説明P ) 端（drain terminal)連接到P-通道（.p-channeij MOS電 晶體4之汲極端（drain tenminai),而其閘極端（sate terminal)則由參考電源供應電壓VREF所控制；-η-通道 (n-channeU MOS電晶體 16其汲極端（drain terminal) 與P-通道（p-charmei) MOS電晶釀8之汲極和閘極端共同 連接，且其閘極端接至内部電源供應電壓iNT.VCC; -η-通 道（n-channe.l) MOS電晶體 18其汲極端（drain terminal )與η-通道（n-channel) MOS電晶禮14與16之源極端共同 連接，其源極端連接至地電位（ground potential) VSS ，其闊極端(gate terminal)連接至節點N4 ; -P-通道（. p-channe 1 ) M〇S|區動電晶體12，其源極端(source terminal)連接至外部電源供應電壓EXT. VCC,其汲極端 (drain terminal)連接至内部電源供應電壓iNT.VCC^ 經濟部中央揉準房貝工消费合作社印氧 (請先《讀背面之注意事項再填寫本頁) 其蘭極端(gate terminal)連接至P-通道(p-channei) MCJS電晶體4之汲極端（drain terminai) ; -P-通道（. P-channe 1) MO岑.電晶體2，其源極端(source terminal) 連接至外部電源供應電歷EXT. VCC,其汲極端（drain terminal)連接室P-通道(p-channe 1) MOS電晶體4之汲 極端（drain terMni'nal)，其鬧極端（gate terminal) 連接至控制時脈A ; -P-通道（p-channei) MOS霜晶體1〇, 其通道之一端連接至P-通道（p-charmei) MOS電晶體4之 汲極（drain terminal),另一端則連接到P-通道（P-channel) M0S電晶體8之汲極端(drain terminal),其 閘極（gate terminal)則連接至控制時脈A; -P-通道（ 一 3 — 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央揉率局Λ工消费合作社印製 ^68X64 五、發明説明（3 ) p-channei.) MCJS電晶體20，其源極端（source terminal .)連接至内部電源供應電壓iNT.VCC,汲極端（drain terminal)連接至節點N4,蘭極端（gate terminal.)貝U 連接至控制時脈B ;以及-η-通道（n-channei) M0S電晶體 22，其汲極端（drain terminal)連接至節點N4，源極端 連接至地電位VSS,閘極端（gate terminal)則連接至控 制時脈B。 P-通道（p-channei) M0S驅動電晶體12供給電流量--定比例之電流流過η-通道（n-channei) M0S電晶體14,其 自内部電源供應電壓iNT. VCC之輸入節點接收參考電暱 VREF以保持内部電源供應電臟為常數位準。此時，毎値P-通道M0S電晶體2、4、8、10及12均有一背鬧極（back sate)顯示出帶一表面操作功能的面積以成為通道，@背 閘極（back gate)像分別地連接至外部電源供應電壓 EXT.VCC，而P-通道（p-channei) M0S電晶髏20之背鬧極 (back sate) ψ]連接至内部電源供應電超INT.VCC,請參 考第一圖與第二圖，茲説明傳統電源供應電壓轉換電路之 操作情形。 ' 首先，在預充電操作方面，當控制時脈A自邏輯“高 ”態改變至邏輯“低”態時，P-通道M0S電晶體2開始導通 。所以，節點N1僳被預充到外部電源供應電壓EXT. VCC之 位能。同時，P-通道M0S電晶體10由控制時脈A導通且節點 N1與N2其電位則被提昇至外部電源供應電壓EXT. VCC。另 —方面，當控制時脈B自邏輯“低”態改變至邏輯“高” 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210Χ297公釐） (請先聞讀背面之注意事項再填寫本頁) 装. 訂 五、發明説明（4 ) 態時，η-通道MOS電晶體22開始導通，然後，節點N4成為 地電位VSS之位能且η-通道MOS電晶濃18截止，結果，放電 操作後由η-通道MOS電晶體18之截止操作所中止，Ρ-通道 MOS電晶體4、8、10與η-通道MOS電晶體14、16、18所組合 成之差動放大器係被消能。再者，Ρ-通道M0S驅動電晶體 12之鬧源電壓（gate source Voltage) Vgs偽連接至節點 NT而預充電至外部電源供應電歷EXT. VCC之位準而成為0伏 特，因而截止了P-通道M0S驅動電晶體12。故，在外部電 源供應電魔EXT. V CC與内部電源供應電歷INT. VCC之間之電 連接端像完全截止，且電流路徑並未形成。 繼之，在主動操作方面，當控制時脈A自邏輯《低” 態改變至邏輯“高”態時，P-通道M0S電晶體2及10則截止 。同時，當時脈B且邏輯“高”態改變至邏輯“低”態時 ,P-通道M0S電晶體20俗導通且η-通道M0S電晶體22係截止 ，因而，η-通道M0S電晶體18傺導通。結果，放電操作偽 由η-通道M0S電晶體18之導通操作所完成差動放大器係被 j 致能。 經濟部中央揲李扃Λ工消费合作社印装 (請先Μ讀背面之注意事項再樓寫本頁) 電源供應電歷轉換電路，供給參考電歷VREF及内部電 源供應霄壓INT.VCC：之間放大霄壓位階差。亦即，如果内 部電源供應電壓INT. VCC之位準低於參考電壓VREF，則流 經η-通道M0S電晶體14的大置霉流，會愈增愈多，且電壓 輸入至Ρ-通道M0S驅動電晶體12之蘭端像下降。結果， Ρ-通道M0S驅動電晶體12截止且内部電源供應電歷INT. VCC 之電位則昇高。 本紙張尺度適用中國國家棣準（CNS ) Α4规格（210X297公釐〉 經濟部中央揉率局Λ工消费合作社印装 A7 B7 五、發明説明（5 ) 另一方面，如果内部電源供應電壓iNT. VCC之位準高 於參考電Μ V R E F ,則流經η -通道Μ 0 S電晶體16之大量電流 會愈增愈多，且電遞輸入至Ρ-通道MOS驅動電晶體12之閘 端係漸漸地增高，結果，Ρ-通道MOS驅動電晶體12像導通 且内部電源供應電壓ίNT. VCC電位之增加量則被抑制。 電源供應電腰轉換電路顯示於第一圖中條構築以電流 鏡型態，其中，流經P-通道MOS電晶體4及8之大量電流幾 乎保持固定，如第一圖及第二圖所示，在電源供應電蹈轉 換電路之預充電週期完成之後，若差動效大級條由控制時 脈A及B之輸入所致能，則建立在節點H1連接至P-通道MOS 驅動電晶體12閘極端之電壓會自外部電源供應電壓EXT. VCC 跌落至電艇EXT· VCC-Vtp。（其中Vtp偽為P-通道MOS電晶 體4之臨界電壓），此時，對於外部電源供應電壓EXT. VCC 達到電壓EXT. VCC-Vtp之時間要求，在内部電源供應電歷 INT. VCC之穩定度上有一連串的影響，因為對於P-通道MOS 驅動電晶體12之導通操作而言當抵逹時間遲到時，時間點 像被延遲，結果、在外部電源供應電壓EXT. VCC及内部電 源供應電壓INT .VCC間之電流路徑傜過時地形成。 在外部電源供應電壓EXT. VCC及内部電源供應電歷 DJT. VCC之間之電流路徑形成之前，若由於雜訊造成内部 電源供應電壓INT.VCC下降之情形發生，則内部電源供應 電壓iNT.VCC之恢復時間變長。由於這個理由，内部電源 供應電壓INT. VCC之需求位準不能被保持。 然後，在主動週期開始之後，P-通道MOS驅動電晶體 —6 _ 本纸張尺度適用中國國家梂準（CNS ) Α4規格（210Χ297公* ) -----·----^ 裝------^訂-----A 球 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消费合作杜印«. 08164_B7_五、發明説明（6 ) 12像儘童地快導通且内部電源供應電壓iNT· VCC應被設定 至一預定需求電壓位準如第二圖所示，在傳統電源供應電 蹈轉換電路之中，主動週期開始且過了大約50奈秒（nano-second)之後，因為P-通道M0S驅動電晶體12導通，故設 定内部電源供應電壓IHT.VCC至一預定的需求電壓位準是 困難的。 【發明之總論】 本發明之目的傜提供一電源供應電顧轉換電路能夠快 速設定内部電源供應電壓至一預定需求電壓位準，以轉換 一外部電源供應電壓至内部電源供應電壓。 本發明之另一目的像提供一電源供應電壓轉換電路能 夠避免内部電源供應電壓遒受内部電源供應電壓之雜訊而 被降低，並在外部電源供應電壓與内部電源供應電壓之間 快速地形成一電流路徑。 為了逹到本發明的上述與其他目的，本發明提供一霣 ΊΓ 源供應電颸轉換電路於半導體積體電路之中，以轉換外部 電源供應電壓而成為内部電源供應電壓，因此産生一最佳 内部電源供應電丨壓V電源供應電壓轉換電路包括一差動放 大單元，其個別在第一輸入節點與第二輸入節點接收一參 考電壓與内部電源供應電壓並放大參考電壓與内部電源供 應電歷之間的差值，差動放大單元在預充電操作之時間内 被消能並在主動操作之時間内被激能；一驅動單元自外部 電源供應電壓供應電流至内部電源供應電想以接受差勤放 —Ύ — (請先閱讀背面之注^^項再填窝本頁) 衮. 訂 球 本纸張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） 經濟部中央橾準局員工消费合作社印製 ^68164 五、發明説明（7 ) 大單元之輸出；以及一控制單元。當差動放大器單元被驅 動至主動操作區時，其能同時操作驅勤單元，之後驅動單 元之驅動信號在預充電操作之期間内被預充至一已知位準 〇 【圖式之簡單説明】 附圖者： V/第一圖為傳統電源供應電廳轉換電路之電路圖； 二圖為第一圖中電源供應電壓轉換電路特性波形圖； _三圖為根據本發明電源供應電壓轉換電路结構之電路圖 ;以及 四圖為第三圖中電源供應電壓轉換電路待性波形圖。 【較佳具體實施例之描述】 第三圖傜根據本發明結構之電源供應電颳轉換電路之 電路圖於第三圖的結構之中，像提供P-通道MOS電晶體4與 ·» 8其源極端分別疾受外部電源供應電壓EXT.VCC,且閘端相 互連接一起，-η-通道MOS電晶髏14其汲極端連接至P-通道 MOS電晶體4之汲極端，且閘極端由參考電源供應電歷VREF 控制；-η-通道MOS電晶體16其汲極端共同連接至Ρ-通道 MOS電晶體8之汲極與閘極端，且閘極端由内部電源供應電 ariirr.vcc控制；-η-通道mos楚晶體is其汲極端共同連接 至η-通道MOS電晶體14與16之源極端，源極端連接至地電 位VSS,以及閑極端連接至節點Ν4; -Ρ-通道MOS驅動電晶 —S 一 本纸張尺度逋用中國國家標率（CNS ) Α4规格（210X297公釐） ---------袈-------訂—-----4 球 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央揉準局員工消费合作社印装 ^68164 A7 B7 五、發明説明（3 ) 體12其源極端連接至外部電源供應電壓EXT. VCC ,汲極端 連接至内部電源供應電壓iNT.VCC,以及閘極端連接至P-遒道MUS電晶體4的汲極端；一二極體連接（diode-conneetion) P -通道MOS電晶體24其源極端連接至外部電 滕供應道壓liXT.VCC,蘭極端連接全.一汲極端；-卜-通道 M(〕S電晶體2其源極端連接至P -通道MOS電晶義24之汲極端 ，以及蘭極端連接至控制時脈A ; -P-通道MOS電晶體10其 通道之-端接至P-通道卜i〔)S電晶體4之汲極端，另一端則接 至P-通道M0S電晶體8的汲極端，以及閘極端連接至控制時 脈A ; -P-通道M0S電晶體20其源極端連接至内部電源供應 電歷iNT.VCC, —汲極端連接至節點N4，以及一閘極端連 接至控制時脈B ;以及-η-通道M0S電晶體22其汲極端連接 至節點N4,源極端連接至地電位VSS,以及一閘極端連接 至控制時脈B。 二極體一連接（diode-connection) P-通道 M0S 電晶 體24及P-通道M0S電晶體2像由第三圖中虛線框所圍住之部 份，其擔任控制電路以控制P-通道M0S驅動電晶體12。此 二極體一連接（diode-connection) P-通道M0S電晶體24 於預充電操作期間使用外部電源供應電壓EXT. VCC做為源 極電壓以設定P-通道M0S驅動電晶體12之閘極電壓至電壓 EXT· VCC-Vtp。P-通道M0S電晶體2俗連接於二極體一連接 P-通道M0S電晶體之汲極端與p-通道M0S驅動電晶體12之間 ，旦其於預充電操作期間内導通並於主動操作期間截止。 此時，每個P-通道M0S電晶禮4、8、10、12與24均有 —y — 本紙張尺度適用中國國家棣準（CNS ) Α4规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 1 丁 經濟部中央糅準局負工消费合作社印装 A7 B7 五、發明说明（9 ) --赞鬧極（back gate)顯示出帶一表面操作功能的面積 以成為通道，其背蘭極（back gate)係f連接至外部電源 供應電蹈EXT.VCC,而P-通道（p-channei) MOS電晶體20 之背蘭極（back sate)則連接至内部電源供應電壓 IMT. VCCc P-m.M Cp-channeU M0S電晶勺源極i尚與=/# 蘭極像相互連接。 請參考第三圖第四圖，茲說明本發明電源供應電壓轉 換電路結構之操作情形。 首先，在預充電操作狀態中，當控制時脈A條自邏輯 “高〃態改變至邏輯“低”態，P-通道（p-channei) M0S 電晶體2因而導通。故，節點N1條被預充電至電壓EXT. VCC -Vtp的電位，其電®藉由降落外部電源供應電壓EXT_ VCC 越過臨界電_Vtp而達到。同時，P-通道（p-channei) M0S電晶體10由控制時脈A而導通以及節點N1與N2俗預充電 至外部電源供應電壓EXT. VCC。 另一方面，當控制時脈B像自邏輯“低”態改變至遲 輯“高”態時，η-通道（n-channei) M0S電晶體22導通。 然後，節點N4變成地電位VSS且η-通道（n-channei) M0S 電晶體18截止，結果，放電操作像由n-通道（n-channei )M0S電晶體18之截止操作所中止，P-通道（p-channei) M0S電晶體4、8、10與η-通道（n-channei) M0S電晶體14 、：L6、18所組合成之差動放大器像被消能。 接下來，在主動操作方面，當控制時脈A像自遇輯“ 低”態改變至涵輯“高”態時，P-通道M0S電晶體2與10條 —1 〇 — 本紙张尺度逍用中國國家榡準（CNS ) Λ4规格（210X297公釐） 裝— (請先《讀背面之注$項再填寫本頁) 訂 線 2^8te4 Α7 Β7_ 五、發明説明（1ϋ ) (請先«讀背面之注$項再填寫本頁) 截止，同時，富控制時脈B像自邏輯“高”態，改變至邏 輯“低”態，P-通道MOS電晶體20像導通且η-通道MOS電晶 體22像截止。因而，η-通道M0S電晶體18導通，結果，放 電操作係由η-通道M0S電晶體18之導通操作所完成，差動 放大器像被致能。 請參考第三圖與第四圖，在電源供應電腰轉換電路的 預充電週期完成之後，建立在節點Ν1連接至Ρ-通道M0S驅 動電晶體12閘極端之電壓像事先預充電至電壓EXT. VCC-Vtp 。故，若差動放大器由控制時脈A與B的輸入所致能，則P-通道M0S驅動電晶體12立刻導通且在初始主動週期期間内 ，内部電源供應電腰INT.VCC的電蹈下降也能被抑制。換 句話說，P-通道M0S驅動電晶體12之閘極節點在預充電週 期中能充電到電壓EXT. VCC-Vtp,以及若内部電源供應電 壓INT. VCC的位準比參考電HEVREF低，P-通道M0S驅動電晶 體12能藉由察覺上述描述之情形而快速導通。 經濟部中央揉準肩貝工消费合作社印装 在傳統電源、供應電腰轉換電路之中，於主動週期開始 之後，這個問題/亦即，由於内部霜源供應電歷産生之雜 訊持缠約50ns (nano-second)造成的内部電源供應電壓 下降，能被改變（移動）以具體化表現電路之穩定操作。 在第三圖中，若P-通道M0S電晶體24與P-通道M0S驅動 晶體12之臨界電歷條相互相同，微董的漏電流能自外部電 源供應電艇EXT. VCC流經P-通道M0S電晶體2而至内部電源 供應電壓INT.VCC。若漏電流大於内部電源供應電壓節點 中損耗的備用電流，則在預充電操作期間内便有可能提高 一 11 _ 本紙張尺度遑用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央揉準局貝工消费合作社印装 A7 B7 五、發明説明P ) 内部電源供應電壓iNT.VCC的位準。為了解決本問題，將 P-通道MOS電晶體24之臨界電壓設定低於P-通道MOS驅動電 晶體12偽值得的，進一步而言，因為P-通道MOS電晶體24 之汲一源電壓(drain-source Voltage) Vds係僅在臨界 電壓，故，P-通道MDS電晶體24之臨界電啦能被設定低於 其他正常的P-通道MOS電晶髓之臨界電壓。控制P-通道MOS 電晶體24與P-通道MOS驅動電晶體12之臨界電懕之方法俗 藉區分每一電晶體之通道長度或一次離子植入法（ion implantation)達成。就調整每一電晶體通道長度的情形 而言，若P-通道MOS電晶體24的通道長度短於P-通道MOS驅 動電晶體12的通道長度，則P-通道MOS電晶體24的臨界電 壓低於P-通道MOS驅動電晶體12的臨界電丨E。除此以外， 一次離子植入法的調整能藉使用光罩過程而達成。 如上所述，根據本發明之電源供應電壓轉換電路條能 夠快速設定内部震源供應電蹈至預定需求電躔位準，以轉 換外部電源供應電歷而成為内部電源供應電應。尤有甚者 電源供應電颸轉換k電路條能夠避免内部電源供應電鼷遭受 内部電源供應電歷之雜訊而降低其電壓，並在外部電源供 應電壓與内部電源供應電壓之間快速地建立一電流路徑。 — 12 — 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 装 訂 線A7 B7 ^ 8164 V. Description of the Invention (l) [Inventive Highlights] The present invention relates to semiconductor integrated circuits, especially a power supply avoidance conversion circuit for converting external power supply voltage to internal power supply to generate a The best internal power supply voltage. In recent years, as the density of semiconductor memory devices has increased at a high rate, the size of each element, such as transistors, has been reduced. As a result, the internal voltage level has been reduced in proportion to the size reduction of the device. Therefore, in order for r to include a stable and reliable operation process of the internal circuit, the operation history level provided to each element must be reduced. In response to this, power supply devices are widely installed in semiconductor memory devices to convert the external power supply voltage outside the device to the internal power supply voltage. Fig. 1 is a circuit diagram showing a conventional power supply circuit conversion circuit, and Fig. 1A waveform shows the characteristics of the power supply voltage conversion circuit in Fig. 1. The power supply voltage conversion circuit in Figure 1 is generally constructed with a current mirror type. As is well known, this circuit type acts as a differential amplifier. In the first figure,-= * reference calendar VREF and an internal power supply voltage k 丄 NT. VCC is received in this circuit and a discharge crystal 18 performs the release operation according to the state of node N4. By this, the difference between the reference voltage VREF and the internal power supply voltage INT. VCC is enlarged. In the structure of Figure 1, it provides P-channel (p-channei) MOS transistors 4 and 8, and the source terminal (source terminal) is respectively connected to an external power supply electrical calendar EXT · VCC and the blue terminal (sate terminal) Shell and J are connected to each other; -η-channel (n-channei) HOS transistor 14 and its drain-2-This paper scale uses the Chinese National Standard (CNS) A4 specification (210X297 mm) 11 pack ― Order-II first line (please read the note $ item on the back and fill in this page) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 68164 A7 ___B7___ 5. Description of invention P) The drain terminal is connected to the P-channel ( .p-channeij MOS transistor 4 drain terminal (drain tenminai), and its gate terminal (sate terminal) is controlled by the reference power supply voltage VREF; -η-channel (n-channeU MOS transistor 16 its drain terminal ( drain terminal) is connected to the drain and gate terminals of the P-channel (p-charmei) MOS transistor 8, and the gate terminal is connected to the internal power supply voltage iNT.VCC; -η-channel (n-channe.l ) MOS transistor 18 and its drain terminal (drain terminal) and n-channel (n-channel) MOS transistors 14 and 16 The source terminals are connected together, their source terminals are connected to ground potential (VSS), and their wide terminals (gate terminal) are connected to node N4; -P-channel (.p-channe 1) M〇S | 区 动 电 晶 12 , Its source terminal is connected to the external power supply voltage EXT. VCC, and its drain terminal is connected to the internal power supply voltage iNT.VCC ^ Central Ministry of Economic Affairs, Ministry of Economics, Housing and Food Industry Consumer Cooperative Ink Oxygen (please first "Read the precautions on the back and then fill out this page." Its blue terminal (gate terminal) is connected to the P-channel (p-channei) MCJS transistor 4 drain terminal (drain terminai); -P-channel (. P-channe 1 ) MO Cen. Transistor 2, whose source terminal is connected to the external power supply EXT. VCC, and its drain terminal is connected to the P-channel (p-channe 1) of the drain terminal MOS transistor 4 Extreme (drain terMni'nal), its gate terminal is connected to the control clock A; -P-channel (p-channei) MOS frost crystal 10, one end of its channel is connected to the P-channel (p-charmei ) The drain terminal of MOS transistor 4, the other end is connected to the P-channel (P-channel) M0S transistor The drain terminal of 8, the gate terminal of which is connected to the control clock A; -P- channel (一 3 — This paper standard uses the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Central Bureau of Economic Development of the Ministry of Economy ^ 68X64. 5. Description of the invention (3) p-channei.) MCJS transistor 20, whose source terminal (source terminal.) Is connected to the internal power supply voltage iNT.VCC, Ji The drain terminal is connected to the node N4, the blue terminal is connected to the control clock B; and the -n-channel (n-channei) MOS transistor 22, whose drain terminal is connected to the drain terminal At the node N4, the source terminal is connected to the ground potential VSS, and the gate terminal is connected to the control clock B. P-channel (p-channei) M0S drive transistor 12 supplies a current amount-a fixed proportion of current flows through the η-channel (n-channei) M0S transistor 14, which is received from the input node of the internal power supply voltage iNT. VCC Refer to VREF to keep the internal power supply dirty as a constant level. At this time, every P-channel M0S transistors 2, 4, 8, 10 and 12 have a back sate that shows the area with a surface operation function to become a channel, @ 背 门 极 (back gate) It is connected to the external power supply voltage EXT.VCC separately, and the P-channel (p-channei) M0S back crystal (back sate) ψ] is connected to the internal power supply power supply INT.VCC, please refer to The first and second figures illustrate the operation of the conventional power supply voltage conversion circuit. 'First, in terms of precharge operation, when the control clock A changes from a logic "high" state to a logic "low" state, the P-channel MOS transistor 2 starts to conduct. Therefore, the node N1 is precharged to the potential of the external power supply voltage EXT. VCC. At the same time, the P-channel MOS transistor 10 is turned on by the control clock A and the potentials of the nodes N1 and N2 are raised to the external power supply voltage EXT. VCC. On the other hand, when the control clock B changes from a logic "low" state to a logic "high", the paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) (please read the precautions on the back before filling in (This page). Fifth, the description of the invention (4) In the state, the η-channel MOS transistor 22 starts to turn on, and then the node N4 becomes the potential of the ground potential VSS and the η-channel MOS transistor 18 is turned off. As a result, After the discharge operation is terminated by the cut-off operation of the n-channel MOS transistor 18, the differential amplifier formed by the combination of the p-channel MOS transistors 4, 8, 10 and the n-channel MOS transistors 14, 16, 18 is eliminated can. Furthermore, the gate source voltage Vgs of the P-channel M0S driving transistor 12 is pseudo-connected to the node NT and is pre-charged to the external power supply voltage EXT. VCC level becomes 0 volts, thus ending P -Channel M0S drives transistor 12. Therefore, the electrical connection between the external power supply EXT. V CC and the internal power supply INT. VCC is completely cut off, and the current path is not formed. Next, in terms of active operation, when the control clock A changes from the logic "low" state to the logic "high" state, the P-channel MOS transistors 2 and 10 are cut off. At the same time, the clock B and the logic "high" When the state changes to a logic "low" state, the P-channel MOS transistor 20 is normally turned on and the η-channel MOS transistor 22 is turned off. Therefore, the η-channel MOS transistor 18 is turned on. As a result, the discharge operation is falsely caused by η- The differential amplifier completed by the conduction operation of the channel M0S transistor 18 is enabled by j. Printed by the Central Government of the Ministry of Economic Affairs, Li Ligong Consumer Cooperative (please read the precautions on the back and write this page on the floor) Power supply calendar The conversion circuit supplies the reference electrical calendar VREF and the internal power supply voltage INT.VCC: the difference between the voltage levels is amplified. That is, if the level of the internal power supply voltage INT.VCC is lower than the reference voltage VREF, it flows through η -The large mold flow of the channel M0S transistor 14 will increase more and more, and the voltage input to the P-channel M0S drive transistor 12 will decrease the blue end image. As a result, the P-channel M0S drive transistor 12 will be cut off and the internal power supply The potential of the supply electricity calendar INT. VCC will increase. Applicable to China National Standards (CNS) Α4 specifications (210X297mm). The Ministry of Economic Affairs Central Bureau of Industry and Commerce Cooperative Printed A7 B7 5. Invention description (5) On the other hand, if the internal power supply voltage is iNT. VCC Quasi-higher than the reference voltage MVREF, then a large amount of current flowing through the n-channel MOS transistor 16 will increase more and more, and the gate terminal of the teletransmission input to the P-channel MOS drive transistor 12 gradually increases, As a result, the P-channel MOS drive transistor 12 is turned on and the increase in the internal power supply voltage NTV. The potential of the VCC potential is suppressed. The power supply waist conversion circuit is shown in the first diagram as a current mirror type structure, in which the flow A large amount of current through the P-channel MOS transistors 4 and 8 remains almost fixed. As shown in the first and second figures, after the precharge cycle of the power supply circuit is completed, if the differential effect is large The control clock A and B inputs are enabled, and the voltage established at the gate terminal of node H1 connected to the P-channel MOS drive transistor 12 will drop from the external power supply voltage EXT. VCC to the electric boat EXT · VCC-Vtp. (Where Vtp is pseudo P-channel MOS The critical voltage of crystal 4), at this time, for the time requirement of the external power supply voltage EXT. VCC to reach the voltage EXT. VCC-Vtp, there is a series of influence on the stability of the internal power supply calendar INT. VCC, because of the P -For the turn-on operation of the channel MOS drive transistor 12, when the arrival time is late, the time point is delayed. As a result, the current path between the external power supply voltage EXT. VCC and the internal power supply voltage INT .VCC is obsolete. form. Before the current path between the external power supply voltage EXT. VCC and the internal power supply calendar DJT. VCC is formed, if the internal power supply voltage INT.VCC drops due to noise, the internal power supply voltage iNT.VCC The recovery time becomes longer. For this reason, the demand level of the internal power supply voltage INT. VCC cannot be maintained. Then, after the start of the active cycle, the P-channel MOS drive transistor — 6 _ This paper scale is applicable to China National Standards (CNS) Α4 specification (210Χ297 公 *) ----- · ---- ^ Pack- ----- ^ Subscribe ----- A ball (please read the precautions on the back and then fill out this page) The Ministry of Economic Affairs Central Bureau of Customs and Appraisal of Beigong Consumer Cooperation Du Yin «. 08164_B7_ V. Description of the invention (6) 12 It turns on as fast as possible and the internal power supply voltage iNT · VCC should be set to a predetermined demand voltage level. As shown in the second figure, in the traditional power supply circuit conversion circuit, the active cycle starts and passes approximately After 50 nanoseconds, it is difficult to set the internal power supply voltage IHT.VCC to a predetermined required voltage level because the P-channel MOS drive transistor 12 is turned on. [Overview of the Invention] The purpose of the present invention is to provide a power supply converter conversion circuit that can quickly set the internal power supply voltage to a predetermined demand voltage level to convert an external power supply voltage to an internal power supply voltage. Another object of the present invention is to provide a power supply voltage conversion circuit that can prevent the internal power supply voltage from being reduced by the noise of the internal power supply voltage, and quickly form a voltage between the external power supply voltage and the internal power supply voltage. Current path. In order to achieve the above and other objects of the present invention, the present invention provides a ΊΓ source supply electrical conversion circuit in a semiconductor integrated circuit to convert an external power supply voltage into an internal power supply voltage, thus generating an optimal internal The power supply voltage and voltage V power supply voltage conversion circuit includes a differential amplifier unit, which individually receives a reference voltage and an internal power supply voltage at the first input node and the second input node and amplifies the reference voltage and the internal power supply The difference between the differential amplifier unit is dissipated during the pre-charge operation and excited during the active operation; a drive unit supplies current from the external power supply voltage to the internal power supply to accept the difference放 —Ύ — (Please read the note ^^ on the back and fill in this page) 衮. The size of the book is applicable to China National Standards (CNS) A4 (210X297mm). Printed by the consumer cooperative ^ 68164 V. Description of the invention (7) The output of the large unit; and a control unit. When the differential amplifier unit is driven to the active operating area, it can simultaneously operate the driving unit, and then the driving signal of the driving unit is precharged to a known level during the precharge operation. ] Attached figures: V / The first figure is the circuit diagram of the conventional power supply circuit conversion circuit; The second figure is the characteristic waveform diagram of the power supply voltage conversion circuit in the first figure; The third figure is the structure of the power supply voltage conversion circuit according to the present invention The circuit diagram; and the four diagrams are the standby waveform diagram of the power supply voltage conversion circuit in the third diagram. [Description of the preferred embodiment] The third figure shows the circuit diagram of the power supply scraper conversion circuit according to the structure of the present invention in the structure of the third figure, like providing P-channel MOS transistors 4 and 8 The extremes are affected by the external power supply voltage EXT.VCC, and the gate terminals are connected together, the drain terminal of the -η-channel MOS transistor 14 is connected to the drain terminal of the P-channel MOS transistor 4, and the gate terminal is derived from the reference power supply Supply electric calendar VREF control; -η- channel MOS transistor 16 whose drain terminal is connected to the drain terminal and gate terminal of the P-channel MOS transistor 8 in common, and the gate terminal is controlled by the internal power supply circuit ariirr.vcc; -η- The channel MOS transistor is its drain terminal connected to the source terminals of the n-channel MOS transistors 14 and 16, the source terminal is connected to the ground potential VSS, and the idle terminal is connected to the node N4; -P-channel MOS drive transistor -S A paper standard uses the Chinese National Standard Rate (CNS) Α4 specification (210X297mm) --------- 袈 ------- set ------ 4 ball (please first Read the precautions on the back and fill out this page) Printed by the Employees Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economy ^ 68164 A7 B7 V. Inventions Description (3) The source terminal of the body 12 is connected to the external power supply voltage EXT. VCC, the drain terminal is connected to the internal power supply voltage iNT.VCC, and the gate terminal is connected to the drain terminal of the P-channel MUS transistor 4; one or two Pole body connection (diode-conneetion) P-channel MOS transistor 24 whose source terminal is connected to the external power supply channel voltage liXT.VCC, blue terminal connection is all. A drain terminal;-Bu-channel M (] S transistor 2 Its source terminal is connected to the drain terminal of the P-channel MOS transistor 24, and the blue terminal is connected to the control clock A; -P-channel MOS transistor 10 whose channel-is terminated to the P-channel BUi () S electric The drain terminal of the crystal 4, the other end is connected to the drain terminal of the P-channel MOS transistor 8, and the gate terminal is connected to the control clock A; -The source terminal of the P-channel MOS transistor 20 is connected to the internal power supply calendar iNT.VCC,-the drain terminal is connected to node N4, and a gate terminal is connected to the control clock B; and -η- channel MOS transistor 22 whose drain terminal is connected to node N4, the source terminal is connected to ground potential VSS, and a The gate terminal is connected to the control clock B. Diode one connection (diode-connection) The P-channel M0S transistor 24 and the P-channel M0S transistor 2 are surrounded by a dotted frame in the third figure, which acts as a control circuit to control the P-channel M0S Drive transistor 12. This diode-connection P-channel M0S transistor 24 uses an external power supply voltage EXT during the precharge operation. VCC is used as the source voltage to set the gate voltage of the P-channel M0S drive transistor 12 To voltage EXT · VCC-Vtp. The P-channel M0S transistor 2 is commonly connected to the diode between the drain terminal of the P-channel M0S transistor and the p-channel M0S drive transistor 12, once it is turned on during the precharge operation period and during the active operation period cutoff. At this time, each P-channel M0S electronic crystal ceremony 4, 8, 10, 12 and 24 have -y — This paper standard is applicable to China National Standard (CNS) Α4 specification (210X297 mm) (please read the back of the first (Notes and then fill out this page) 1 Ding, Ministry of Economic Affairs, Central Ministry of Economic Development, Consumer Cooperative Printed A7 B7 V. Description of the invention (9)-The back gate shows the area with a surface operation function to become Channel, its back gate is connected to the external power supply EXT.VCC, and the back sate of the p-channel (p-channei) MOS transistor 20 is connected to the internal power supply The voltage IMT. VCCc Pm.M Cp-channeU M0S electric crystal spoon source i is still connected with the = / # blue pole image. Please refer to the third and fourth figures of the third figure to explain the operation of the power supply voltage conversion circuit structure of the present invention. First, in the precharge operation state, when the control clock A changes from a logic "high" state to a logic "low" state, the P-channel (p-channei) MOS transistor 2 is thus turned on. Therefore, the node N1 is It is precharged to the voltage EXT. VCC-Vtp potential, its power is achieved by dropping the external power supply voltage EXT_ VCC across the critical power _Vtp. At the same time, the P-channel (p-channei) M0S transistor 10 is controlled by the clock A is turned on and the nodes N1 and N2 are pre-charged to the external power supply voltage EXT. VCC. On the other hand, when the control clock B changes from the logic "low" state to the late "high" state, the n-channel ( n-channei) MOS transistor 22 is turned on. Then, the node N4 becomes the ground potential VSS and the n-channel (n-channei) M0S transistor 18 is turned off, as a result, the discharge operation is like the n-channel (n-channei) M0S transistor The cut-off operation of 18 is suspended, and the differential amplifier image formed by the combination of P-channel (p-channei) M0S transistors 4, 8, 10 and η-channel (n-channei) M0S transistors 14, L6, 18 Energy dissipation. Next, in terms of active operation, when the control clock A changes from the "low" state to the "edit" "At the time, P-channel M0S transistors 2 and 10 strips-1 〇-The size of this paper is easy to use the Chinese National Standard (CNS) Λ4 specifications (210X297 mm)-(please read" Notes on the back of the item and then (Fill in this page) Line 2 ^ 8te4 Α7 Β7_ V. Description of the invention (1ϋ) (please first «read the $ item on the back and then fill in this page) The deadline, at the same time, the rich control clock B image is from the logic" high "state, Changing to a logic "low" state, the P-channel MOS transistor 20 is turned on and the n-channel MOS transistor 22 is turned off. Therefore, the n-channel MOS transistor 18 is turned on, and as a result, the discharge operation is performed by the η-channel MOS transistor After the conduction operation of the crystal 18 is completed, the differential amplifier image is enabled. Please refer to the third and fourth figures, after the precharge cycle of the power supply waist conversion circuit is completed, a connection is established at the node N1 to the P-channel M0S The voltage at the gate terminal of the driving transistor 12 is pre-charged to the voltage EXT. VCC-Vtp in advance. Therefore, if the differential amplifier is enabled by the inputs of the control clocks A and B, the P-channel M0S driving transistor 12 is turned on immediately And during the initial active period, the internal power supply provides power The drop can also be suppressed. In other words, the gate node of the P-channel MOS drive transistor 12 can be charged to the voltage EXT. VCC-Vtp during the precharge cycle, and if the internal power supply voltage INT. VCC level ratio With the reference HEVREF low, the P-channel MOS drive transistor 12 can be turned on quickly by perceiving the situation described above. The Ministry of Economic Affairs Centralized Shrimp Consumption Consumer Cooperative is printed in the traditional power supply and power supply waist conversion circuit. After the start of the active cycle, this problem / that is, the noise generated by the internal frost source supply electricity calendar The internal power supply voltage drop caused by 50ns (nano-second) can be changed (moved) to embody the stable operation of the circuit. In the third figure, if the critical electrical calendars of the P-channel M0S transistor 24 and the P-channel M0S drive crystal 12 are the same as each other, the leakage current of the micro-dong can be supplied from the external power supply to the electric boat EXT. VCC flows through the P-channel The MOS transistor 2 supplies the voltage INT.VCC to the internal power supply. If the leakage current is greater than the backup current lost in the internal power supply voltage node, it is possible to increase by 11 during the pre-charging operation. This paper standard uses the Chinese National Standard (CNS) A4 specification (210X297 mm). A7 B7 printed by the Beigong Consumer Cooperatives of the Bureau of Vulnerability. V. Description of invention P) The level of the internal power supply voltage iNT.VCC. In order to solve this problem, it is worthwhile to set the threshold voltage of the P-channel MOS transistor 24 lower than that of the P-channel MOS driving transistor 12, further, because the P-channel MOS transistor 24 draws a source voltage (drain -source Voltage) Vds is only at the threshold voltage. Therefore, the threshold voltage of the P-channel MDS transistor 24 can be set lower than the threshold voltage of other normal P-channel MOS transistors. The method of controlling the critical charge of the P-channel MOS transistor 24 and the P-channel MOS driving transistor 12 is conventionally achieved by distinguishing the channel length of each transistor or one ion implantation method. In the case of adjusting the channel length of each transistor, if the channel length of the P-channel MOS transistor 24 is shorter than the channel length of the P-channel MOS driving transistor 12, the critical voltage of the P-channel MOS transistor 24 is low The P-channel MOS drives the critical current of the transistor 12E. In addition, the adjustment of the one-time ion implantation method can be achieved by using a photomask process. As described above, the power supply voltage conversion circuit strip according to the present invention can quickly set the internal source power supply to a predetermined demand level, so as to convert the external power supply history to become the internal power supply response. In particular, the power supply switch can prevent the internal power supply from being affected by the noise of the internal power supply calendar and reduce its voltage, and quickly establish a between the external power supply voltage and the internal power supply voltage. Current path. — 12 — This paper scale is applicable to China National Standards (CNS) A4 (210X297mm) (please read the precautions on the back before filling this page)