302510 五、發明说明（/ ) ' (一) 技腿域 . >本發明揭露了i種關於積體電路之金屬蝕刻的方法，-特 另ίί是一種關於防止金屬腐蝕並去除「金屬側壁高分子」的金 屬蝕刻方法》 (二) 發明背景 在積體電路製造技術領域，圖案轉移（Pattern Transfer)扮演一個非常重要的角色，而『圖案轉移』是藉 由微影技術和蝕刻技術來執行（Lithography and Etching Technology)。微影技術將絡光罩（Chrome Mask)的電路 圖案轉移到光阻圖案，蝕刻技術再將光阻圖案轉移到薄膜， 以完成積體電路所需的薄膜圖案（Film Pattern)。 積體電路常用的薄膜主要分爲金屬薄膜（Metal)和介 電薄膜（Dielectric) ‘，「金屬薄膜」主要有鋁合金 (Aluminum Alloy)、駄（Ti)、鎢（W)、氮化鈦（TiN) 和鎢化鈦（TiW)等，這些金屬薄膜是用來做爲連線 (Interconnection )以聯接金氧半場效電晶體 (M0SFET)、電容器（Capacitor)和電阻器（Resistor) 等電性元件。「介電薄膜」主要有二氧化矽層和氮化矽，這 些「介電薄膜」是用來隔絕所述『金屬薄膜』，並在所述 「介電薄膜」形成接觸窗（Contact Hole)，使得所述「金 屬薄膜」能透過「接觸窗」跟其它導電體作電性接觸。而無 論是「金屬薄膜」或『介電薄膜』的蝕刻，通常是利用磁場 增強式活性離子式電獎触刻技術（MERIE)或電子迴旋共振電 漿蝕刻技術（ECR)或傳統的活性離子式電漿蝕刻技術 ⑽）來進行。 >紙張尺度違用家樣m : CNS ) A4規格t ϋ10·,<；：97公釐·： 一 {請先《讀背面之注意*項再填寫太莧 .装. Τ___ -*· i i玉、.脊明説明（2) ί 以鋁合金之鈾刻爲例，其電槳反應氣體是CC14、C12、 BC13、CF4和chf3_等氣體，其蝕刻步驟分爲主要蝕刻步驟 (Main-Etch)、過度蝕刻步驟（Over-Etch)和氟覆蓋步驟 (Fluorine Passivation)。所述「過度ΙΦ刻步驟」是保證 能完全的將鋁合金飩刻乾淨；所述「氟覆蓋步驟」則是形成 CF4或CHF3氣體電獎使矽晶圓曝露在充滿氟的環境中，使 氟覆蓋住氯元素以防止金屬腐蝕。 請參考圖一。問題是，在自動對準接觸窗製程（Self-Aligned Contact ; SAC) ， 由於接觸窗之尺寸大於金屬線之 尺寸，也由於複晶矽在cc〖4、Cl2、BC13、cf4或chf3氣體 電漿中的蝕刻率非常高，因此，吾人無法進行太長的「過度 蝕刻步驟」，也無法使用cf4或chf3氣體電樂使矽晶圓曝 露在充滿氟的環境中以防止金屬腐蝕，否則，接觸窗底部之 | 複晶政線條將會被蝕刻而斷線（Disconnection)，如圖一 所示’其中’ 2是矽半導體基板，4是複晶矽連線，6是二 氧化矽介電層，8是接觸窗，10是鋁合金，12是光阻圖 案。請注意複晶矽連線4因「過度蝕刻步驟」而斷線之圖 不0 I 請參考圖二。爲了避免利用CC14、Cl2、bci3、cf4或 g chf3氣體電漿之「過度触刻步驟」造成接觸窗底部之複晶政 |-| 線條斷線，傳統方法利用濕蝕刻來執行「過度蝕刻步驟」以 ^ I 去除銘合金金屬弦14 (Metal Stringer)，以保證能完全 言 的將銘口金蝕刻乾淨’但這依然無法去除氯元素15，因此無 S 法防止金屬腐蝕’也無法去除金屬側壁的高分子’如圖二所 ^ 示，其中’ 2是矽半導體基板，4是複晶矽連線，6是二氧302510 Fifth, the description of the invention (/) '(1) Technical leg area. ≫ The present invention discloses i kinds of methods for metal etching of integrated circuits,-special another is about preventing metal corrosion and removing "metal side wall high "Metal" Metal Etching Method "(2) Background of the Invention In the field of integrated circuit manufacturing technology, pattern transfer plays a very important role, and" pattern transfer "is performed by photolithography technology and etching technology ( Lithography and Etching Technology). The lithography technology transfers the circuit pattern of the Chrome Mask to the photoresist pattern, and the etching technology transfers the photoresist pattern to the film to complete the film pattern required by the integrated circuit. The films commonly used in integrated circuits are mainly divided into metal films (Metal) and dielectric films (Dielectric). "Metal films" mainly include aluminum alloys, aluminum alloys (Ti), tungsten (W), and titanium nitride ( TiN) and titanium tungsten (TiW), etc. These metal films are used as connections (Interconnection) to connect electrical components such as metal oxide semi-field effect transistors (M0SFET), capacitors (Capacitor) and resistors (Resistor) . The "dielectric film" mainly includes a silicon dioxide layer and silicon nitride. These "dielectric films" are used to isolate the "metal film" and form a contact hole in the "dielectric film". This allows the "metal film" to make electrical contact with other conductors through the "contact window". Regardless of whether it is "metal film" or "dielectric film" etching, it is usually the use of magnetic field enhanced active ion electro-reward etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or traditional active ion type Plasma etching technology ⑽). > Paper size violation user sample m: CNS) A4 specification t ϋ10 ·, <;: 97mm ·: 1 {Please first read the "Notes on the back side * item and then fill in the amaranth. installed. Τ ___-* · ii Description of jade and ridge Ming (2) ί Take the uranium engraving of aluminum alloy as an example, the propeller reaction gas is CC14, C12, BC13, CF4 and chf3_ etc. The etching steps are divided into main etching steps (Main-Etch ), Over-etching step (Over-Etch) and fluorine covering step (Fluorine Passivation). The "excess ΙΦ engraving step" is to ensure that the aluminum alloy can be completely engraved; the "fluorine covering step" is to form a CF4 or CHF3 gas electric award to expose the silicon wafer to an environment full of fluorine, so that fluorine Cover elemental chlorine to prevent metal corrosion. Please refer to Figure 1. The problem is that in the Self-Aligned Contact (SAC) process, because the size of the contact window is larger than the size of the metal wire, and also because the polycrystalline silicon is in cc 〖4, Cl2, BC13, cf4 or chf3 gas plasma The etching rate in the medium is very high, therefore, we cannot carry out too long "over-etching steps", nor can we use cf4 or chf3 gas galvanic instruments to expose silicon wafers to a fluorine-filled environment to prevent metal corrosion, otherwise, the contact window Bottom | The polycrystalline line will be etched and disconnected (Disconnection), as shown in Figure 1 'where' 2 is a silicon semiconductor substrate, 4 is a polycrystalline silicon connection, 6 is a silicon dioxide dielectric layer, 8 It is a contact window, 10 is an aluminum alloy, and 12 is a photoresist pattern. Please note that the polycrystalline silicon connection 4 is disconnected due to the "over-etching step". No 0 I Please refer to Figure 2. In order to avoid the "over-etching step" of the gas plasma of CC14, Cl2, bci3, cf4 or g chf3 causing the double crystal at the bottom of the contact window |-| line breakage, the traditional method uses wet etching to perform the "over-etching step" Remove metal stringer 14 (Metal Stringer) with ^ I, to ensure that the gold of the nameplate can be completely etched clean, but this still cannot remove the chlorine element 15, so there is no S method to prevent metal corrosion. The molecule 'is shown in Figure 2 ^, where 2 is the silicon semiconductor substrate, 4 is the polycrystalline silicon connection, and 6 is the dioxygen
本.紙艾遴用m家揉康：CNSA4现格[:l〇x:97公董. 五、發明説明（>) 化矽介電層’ 8是接觸窗，10是錦合金，12是光阻圖案， 14是銘合金金屬弦v15是素。— ·, (三) 發明的簡要說明 本發明的主要目的是提供一種積體電路之金屬蝕刻的方 法。 本發明&另一個目的是提供一種防止鋁合金腐蝕並去除 r'鋁合金側壁高分子」的蝕刻方法。 在金屬触刻反應室（Metal Etching Chamber)進行 「主要触刻步驟」和「過度蝕刻步驟」之後，接著進行一個 问步氧氣電漿處理步驟（In-Situ Oxygen Plasma Treatment) ’所述「同步氧氣電漿處理步驟」能有效的去 除一部份的光阻和氯元素以達到防止金屬腐蝕的目地。另一 方面’所述「同步氧氣電漿處理步驟」也改變了金屬側壁之 高分子的特性，使得在後續化學溶劑中能輕易去除所述「側 壁局分子」’防止砂團（Silicon Nodule)陷在所述「高分 子」內。 (四） 圖示的簡要說明 · 圖一是金屬蝕刻先前技藝之電漿過度飽刻之製程剖面示意 圖。 圖二是金屬蝕刻先前技藝之濕蝕刻之製程剖面示意圖。_ 圖三到圖六是本發明實施例之製程剖面示意圖。 (五) 發明的詳細說明Ben. Paper Ai Lin uses m home rubbing: CNSA4 present style [: l〇x: 97 公 董. V. Description of the invention (>) Siliconized dielectric layer '8 is the contact window, 10 is Jin alloy, 12 is Photoresist pattern, 14 is Ming alloy metal string v15 is prime. — ·, (3) Brief description of the invention The main purpose of the present invention is to provide a method for metal etching of integrated circuits. The present invention & another object is to provide an etching method for preventing corrosion of aluminum alloy and removing r ′ aluminum alloy sidewall polymer. After performing the "main etching step" and the "over-etching step" in the Metal Etching Chamber, proceed with an In-Situ Oxygen Plasma Treatment '"Synchronized Oxygen" The "plasma treatment step" can effectively remove a part of the photoresist and chlorine elements to achieve the purpose of preventing metal corrosion. On the other hand, the "Synchronous Oxygen Plasma Treatment Step" also changed the characteristics of the polymer on the metal side wall, so that the "side wall local molecule" can be easily removed in the subsequent chemical solvent. Within the "polymer". (4) Brief description of the diagram · Figure 1 is a schematic diagram of the process cross section of the over-saturated plasma of the prior art of metal etching. Figure 2 is a schematic cross-sectional view of a wet etching process prior to metal etching. _ FIGS. 3 to 6 are schematic cross-sectional views of the manufacturing process according to an embodiment of the invention. (5) Detailed description of the invention
本發明揭露之體電路之金靥蝕刻的方法’能延伸應用到 任何積體電路技術領域，例如，雙載子元件積體電路 (Bipolar 1C)與金氧半場效電晶體積體電路（M0SFET (請先M讀背面之注意事項乓填寫Λ4Ι ) -装- 本··我張尺度邋用’灌钃家揉Λ : CNS ) A4規格(公釐） 302510 五、發明説明（4) 、 1C)。以下利用金氧半場效電晶體積體電路作爲實施例，說 明本發明之方法。’ * 先參考圖三。首先，以傳統標準製程在P型矽半導體基 板50上形成閘氧化層（Gate Oxide)，利用低壓化學氣相 沉積法（LPCVD)形成複晶矽，其厚度介於1〇〇〇到3000 埃之間，然後，利用微影技術與電漿蝕刻技術蝕去所述「複 晶矽」以形成金氧半場效電晶體（M0SFET)之閛極（Gate Electrode)和複晶矽連線52，最後，形成N+源極/汲極 (Source/Drain)以完成所述金氧半場效電晶體的製造。 請注意，所述閘氧化層、閘極和N+源極/汲極均未顯示於圖 不0 所述「閘氧化層」是熱氧化所述「P型矽半導體基板 50」表面之矽原子而成，其厚度介於50到200埃之間。 所述「N+源極/汲極」是利用離子佈値技術（Ion Implantation)形成，其離子種類是砷原子（As75) ’其離 子佈値劑量介於1E15到5E16原子/平方公分之間’離子 佈値能量則介於30到100 kev之間，視所需要之接面深 度（Junction Depth)而究。 再參考圖三。完成所述『金氧半場效電晶體』的製造 後，接著形成一層介電層54 (Dielectric)，並對所述 「介電層54」進行平坦化處理，所述「介電層54」通常是 利用大氣壓化學氣相沉積法（APCVD)形成之「携雜硼憐的二 氧化矽」（BPSG)，其厚度介於4000到8000埃之間。然 後，利用微影技術與電獎触刻技術飽去所述「介電層54」以 形成接觸窗55 (Contact Hole)。未來，金屬連線將透過 (请先》讀背面之注意H.項具填寫夂育> -装- .The method for etching gold in the body circuit disclosed in the present invention can be extended to any integrated circuit technology field, for example, bipolar device integrated circuit (Bipolar 1C) and metal oxide half field effect transistor volume body circuit (M0SFET ( Please read the precautions on the back of the table and fill in Λ4Ι) -Installation- This-I will use the 'Guanjiajia rubbing Λ: CNS) A4 specification (mm) 302510 V. Description of the invention (4), 1C). The method of the present invention will be described below by using a metal oxide half field effect volume circuit as an example. ’* Refer to Figure 3 first. First, a gate oxide layer (Gate Oxide) is formed on the P-type silicon semiconductor substrate 50 by a conventional standard process, and polycrystalline silicon is formed by low-pressure chemical vapor deposition (LPCVD), with a thickness ranging from 1000 to 3000 Angstroms Then, the lithography and plasma etching techniques are used to etch the "polycrystalline silicon" to form the gate electrode (Gate Electrode) of the MOSFET and the polycrystalline silicon connection 52. Finally, An N + source / drain is formed to complete the fabrication of the metal oxide half field effect transistor. Please note that none of the gate oxide layer, gate, and N + source / drain are shown in Figure 0. The "gate oxide layer" thermally oxidizes silicon atoms on the surface of the "P-type silicon semiconductor substrate 50" The thickness is between 50 and 200 angstroms. The "N + source / drain" is formed by ion implantation technology (Ion Implantation), and its ion type is arsenic atom (As75). The ion implantation dose is between 1E15 and 5E16 atoms / cm2. The cloth energy is between 30 and 100 kev, depending on the required junction depth (Junction Depth). Refer to Figure 3 again. After the manufacturing of the "gold oxide half field effect transistor" is completed, a dielectric layer 54 (Dielectric) is formed, and the "dielectric layer 54" is planarized. The "dielectric layer 54" is usually It is formed by "atmospheric pressure chemical vapor deposition (APCVD)" of "boron-bearing silicon dioxide" (BPSG), and its thickness is between 4000 and 8000 angstroms. Then, the "dielectric layer 54" is filled up by using the lithography technology and the electrical award contact etching technology to form a contact hole 55 (Contact Hole). In the future, the metal connection will be through (please read "Notes on the back" H. Item fill in education> -install-.
五、發明説明（5 ) 所述「接觸窗55」跟所述複晶矽連線52作電性接觸。 現在參考圖四。/然後，利甩灘鍍技術形成欽（Ti )—、氣 化鈦（TiN)與鋁合金（Aluminum Alloy)，所述鈦、氮化 鈦與鋁合金之三層結構組成了金屬56 ( Metal Interconnection)，所述「金屬56」並跨過所述「接觸窗 55」跟所述複晶矽連線52作電性接觸。接著，利用微影技 術在所述「金屬56」表面形成光阻圖案58 (Photoresist Pattern)，如圖四所示。 * 現在參考圖五。然後，以所述『光阻圖案58』作爲飩刻 保護罩（Etch-Protection Mask)，利用電漿蝕刻技術在金 屬蝕刻反應室（Metal Etching Chamber)內進行所述「金 屬56」的蝕刻，蝕去被所述『光阻圖案』覆蓋區域以外之所 述「金屬56」以形成「金屬連線56」，這時，到處充斥著 氯元素60，如圖五所示。對所述「金屬56」之蝕刻可分爲 兩個蝕刻步驟，一個是主要蝕刻步驟（Main-Etch Step)， 一個是過度蝕刻步驟（Over-Etch Step) ’先施行「主要蝕 刻步驟」再施行『過度蝕刻步驟』，而『過度鈾刻步驟』之 時間約「主要鈾刻步驟」的10%。臺灣積體電路製造公司 (Taiwan Semiconductor Manufacturing Corporation ； tsmc)目前所使用的金屬蝕刻反應室之「主要蝕刻步驟」之 配方是射頻功率2300 watts、反應室壓力25 mili-torr、 Cl2氣體流量10 scan、BC13氣體流量150 seem。「罕 度蝕刻步驟」之配方則是射頻功率2300 watts、反應室壓 力30 mili-torr、Cl2氣體流量65 seem、BC13氣體流量 150 seem、0卩4氣體流量 10 seem。 木舐佚尺度適用_篱躪家揉率：CNS ) A4规格ί' 21K97公釐1 (請先Μ讀背面之注意事項再填寫夂夏)5. Description of the Invention (5) The "contact window 55" makes electrical contact with the polycrystalline silicon connection 52. Refer now to Figure 4. / Then, Li Shaotan plating technology formed Ti (Ti)-, vaporized titanium (TiN) and aluminum alloy (Aluminum Alloy), the three-layer structure of titanium, titanium nitride and aluminum alloy composed of metal 56 (Metal Interconnection ), The "metal 56" makes electrical contact with the polycrystalline silicon connection 52 across the "contact window 55". Next, a photoresist pattern 58 (Photoresist Pattern) is formed on the surface of the "metal 56" using lithography technology, as shown in FIG. * Now refer to Figure 5. Then, using the "photoresist pattern 58" as an etching protection mask (Etch-Protection Mask), using plasma etching technology in the metal etching reaction chamber (Metal Etching Chamber) in the "metal 56" etching, etching To remove the "metal 56" outside the area covered by the "photoresist pattern" to form a "metal connection 56", at this time, chlorine element 60 is everywhere, as shown in Figure 5. The etching of the "metal 56" can be divided into two etching steps, one is the main etching step (Main-Etch Step), and the other is the over-etching step (Over-Etch Step). "Over-etching step", and "over-uranium engraving step" time is about 10% of "main uranium engraving step". The formula of the "main etching step" of the metal etching reaction chamber currently used by Taiwan Semiconductor Manufacturing Corporation (Tsmc) is RF power 2300 watts, reaction chamber pressure 25 mili-torr, Cl2 gas flow 10 scan, BC13 gas flow is 150 seem. The recipe for the "rare etching step" is RF power 2300 watts, chamber pressure 30 mili-torr, Cl2 gas flow 65 seem, BC13 gas flow 150 seem, 0 4 gas flow 10 seem. Applicable to the scale of the wooden squash_Lifu home rubbing rate: CNS) A4 specification ί 21K97mm 1 (please read the precautions on the back before filling in the summer)
五、發明説明（b) 現在參考圖六。完成所述「過度蝕刻步驟」後，接著在 所述金屬蝕刻反應室施行1個同步氧氣電漿處理步驟88 (In-si tu Oxygen Plasma Treatment)，以臺灣積體電路 製造公司目前開發的「同步氧氣電漿處理步驟88」配方爲 例，其射頻功率是800 watts、反應室壓力是150 mili-torr、02氣體流量80 seem，處理時間約300秒。所述 「同步氧氣電漿處理步驟88」能去除氯元素60，如圖六所 示，以達到防止金屬腐蝕的目地。另一方面，所述「同步氧 氣電漿處理步驟88」也改變了金屬側壁之高分子（Metal Sidewall Polymer)的特性，使得在後續化學溶劑中能輕易 去除所述「側壁高分子」，防止矽團（Silicon Nodule)陷 在所述「高分子」內。 完成所述「同步氧氣電衆處理步驟88」後，接著將所述 「P型矽半導體基板50」移出所述金屬蝕刻反應室，置入 化學槽進行傳統的金屬濕蝕刻，約浸泡30秒，然後去除所 述「光阻圖案58」。 以上係以最佳實施例來閫述本發明，而非限制本發明， 並且，熟知半導體技藝之人士皆能明瞭，適當而作些微的改 變及調整，仍將不失本發明之要義所在，亦不脫離本發明之 精神和範圍。 !V. Description of the invention (b) Reference is now made to Figure VI. After completing the "over-etching step", then perform a simultaneous oxygen plasma treatment step 88 (In-si tu Oxygen Plasma Treatment) in the metal etching reaction chamber, using the "synchronization" currently developed by Taiwan Semiconductor Manufacturing Co., Ltd. For example, the recipe of Oxygen Plasma Treatment Step 88 has an RF power of 800 watts, a reaction chamber pressure of 150 mili-torr, a 02 gas flow rate of 80 seem, and a processing time of about 300 seconds. The "Synchronous Oxygen Plasma Treatment Step 88" can remove the element 60 of chlorine, as shown in Figure 6, in order to achieve the purpose of preventing metal corrosion. On the other hand, the "Synchronous Oxygen Plasma Treatment Step 88" also changes the characteristics of the metal side wall polymer (Metal Sidewall Polymer), so that the "side wall polymer" can be easily removed in subsequent chemical solvents to prevent silicon Silicon Nodule is trapped in the "polymer". After completing the "Synchronous Oxygen Mass Processing Step 88", the "P-type silicon semiconductor substrate 50" is then removed from the metal etching reaction chamber and placed in a chemical tank for conventional metal wet etching, soaking for about 30 seconds. Then, the "photoresist pattern 58" is removed. The above is a description of the present invention using the preferred embodiments, rather than limiting the present invention, and those skilled in the art of semiconductors can understand that appropriate and slight changes and adjustments will still lose the gist of the present invention. Without departing from the spirit and scope of the present invention. !
衣紙浪尺度4用家埭A : CNS ) A4規格公釐；Yizhilang Standard 4 User Dai A: CNS) A4 specification mm;