TW312871B - - Google Patents

Download PDF

Info

Publication number
TW312871B
TW312871B TW085107831A TW85107831A TW312871B TW 312871 B TW312871 B TW 312871B TW 085107831 A TW085107831 A TW 085107831A TW 85107831 A TW85107831 A TW 85107831A TW 312871 B TW312871 B TW 312871B
Authority
TW
Taiwan
Prior art keywords
circuit
clock
output
phase
latch
Prior art date
Application number
TW085107831A
Other languages
English (en)
Chinese (zh)
Original Assignee
Nippon Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co filed Critical Nippon Electric Co
Application granted granted Critical
Publication of TW312871B publication Critical patent/TW312871B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW085107831A 1995-06-29 1996-06-28 TW312871B (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7164257A JP2982659B2 (ja) 1995-06-29 1995-06-29 位相検出回路

Publications (1)

Publication Number Publication Date
TW312871B true TW312871B (fr) 1997-08-11

Family

ID=15789663

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085107831A TW312871B (fr) 1995-06-29 1996-06-28

Country Status (3)

Country Link
JP (1) JP2982659B2 (fr)
KR (1) KR970003242A (fr)
TW (1) TW312871B (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3039464B2 (ja) * 1997-07-31 2000-05-08 日本電気株式会社 クロック発生回路
JP2000183172A (ja) 1998-12-16 2000-06-30 Oki Micro Design Co Ltd 半導体装置
KR100303781B1 (ko) 1998-12-30 2001-09-24 박종섭 레지스터 제어 디지털 디디엘에 있어서의 언록 문제를 해결하기위한 언록 보상회로를 갖는 디디엘 클럭 발생기
JP4446070B2 (ja) * 2000-04-11 2010-04-07 エルピーダメモリ株式会社 Dll回路、それを使用する半導体装置及び遅延制御方法
JP4392678B2 (ja) 2000-04-18 2010-01-06 エルピーダメモリ株式会社 Dll回路
JP4573007B2 (ja) 2000-07-13 2010-11-04 エルピーダメモリ株式会社 Dll回路、及び、dll制御方法
KR100422572B1 (ko) 2001-06-30 2004-03-12 주식회사 하이닉스반도체 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자
JP4558458B2 (ja) * 2004-11-25 2010-10-06 三菱電機株式会社 位相同期回路
JP5641697B2 (ja) * 2009-02-12 2014-12-17 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. クロック制御回路及びこれを備える半導体装置
US9069652B2 (en) * 2013-03-01 2015-06-30 Arm Limited Integrated level shifting latch circuit and method of operation of such a latch circuit

Also Published As

Publication number Publication date
JPH0917179A (ja) 1997-01-17
JP2982659B2 (ja) 1999-11-29
KR970003242A (ko) 1997-01-28

Similar Documents

Publication Publication Date Title
CN102946248B (zh) 多相位时钟信号产生器及产生方法、信号相位调整回路
US6958634B2 (en) Programmable direct interpolating delay locked loop
US6212127B1 (en) Semiconductor device and timing control circuit
TW432670B (en) Clock generating circuit having high resolution of delay time between external clock signal and internal clock signal
TW312871B (fr)
US7891868B2 (en) Temperature sensor and semiconductor memory device using the same
KR100512935B1 (ko) 내부 클럭신호 발생회로 및 방법
TW518828B (en) Digital-to-time conversion based flip-flop circuit and comparator
US4984216A (en) Operation mode setting circuit for dram
TW312761B (fr)
US9118308B1 (en) Duty cycle corrector
US10636461B2 (en) Apparatuses and methods for providing multiphase clock signals
TW442956B (en) Semiconductor device with dummy interface circuit
KR20170091286A (ko) 지터감지회로 및 이를 이용한 반도체시스템
US20050122832A1 (en) On-die detection of the system operation frequency in a DRAM to adjust DRAM operations
TW421915B (en) Semiconductor circuit device and its using method
KR100258418B1 (ko) 동기식의 dram 반도체메모리의 플립플롭을 사용한 데이터래치회로장치
US6987825B1 (en) Digital synchronous circuit for stably generating output clock synchronized with input data
JPH0763135B2 (ja) 半導体集積論理回路
US10921846B1 (en) Clock generation circuit of semiconductor device
TW459442B (en) Input buffer
KR20030014358A (ko) 동기식 메모리를 비동기식으로 동작시키는 방법 및 장치
US7336554B2 (en) Semiconductor memory device having a reduced number of pins
US20250183881A1 (en) Method of and apparatus for controlling clock signal
US6998896B1 (en) Dynamic gain adjustment systems and methods for metastability resistance

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees