經濟部中央梂準局貝工消費合作社印裝 317018 A7 B7 五、發明説明（） : 1. 發明之技術領域 本發明是關於積體電路之動態隨機存取記億體之電容器的的製造方法，特別是 關於堆疊式動態隨機存取記憶體之電容器的的製造方法。 2. 發明背景 典型的動態隨機存取記憶體是在砂半導體晶圓上製造一個金氧半場效電晶體與 電容器，所述金氧半場效電晶體是作爲轉移閘電晶體（transferred gate transistor)， 並利用所述轉移閘電晶體的源極來連接電容器的下層電極以形成動態隨機存取記憶 體的記憶元。數目龐大的記憶元聚集成爲記憶元陣列。其中，所述轉移閘電晶體的 源¥跟電容器作電性接觸，數位資訊儲存在電容器內，並藉著所述轉移閘電晶體、 位元線和字語線陣列來取得儲存在電容器內的數位資訊。另一方面，在記憶元陣列 的附近則有其它電路圍繞，例如感測放大器等電路，這些外部電路，稱爲琴邊電路 區域（peripheral circuit) 〇因此’要達到動態隨機存取記憶體之高積集密度的目的， 必需縮小記憶體之記憶元的尺寸，然而電容器尺寸的縮小會降低電容値，使得記億 體電路的訊號/雜訊（SignalNoise ; S/N)比例降低，造成電路誤判或電路不穩定等 缺點。職是之故，爲了達成高積集密度的動態隨機存取記憶體，必需尋找更尖端的 製程技術，以在降低記憶元之平面電路佈局面積之同時，能夠維持或增加電容器之 電容値。 電容的公式是C= εΑ/Τ，其中，ε是電容器介電層（capacitor dielectric)之介 電常數，A是電容器下層電極之表面積，T是電容器下層電極之厚度，因此，要增加 電容器之電容可以從兩個方向著手，第一個方向是採用高介電常數的材料作爲電容 器介電層，f如，Ta2〇5、Ti02和SrTi03材料都具有非常高的介電常數，可惜， 由於這些高^亀常數的材料之薄膜品質不佳，存在有絕緣層的奔潰電壓等可靠性問 題，因此到目前爲止還無法應用到動態隨機存取記憶體。 使用高介電常數的電容器介電層既然不甚可行，吾人由電容的公式C= εΑΑΓ 可知電容的大小跟電容器下層電極之表面積成正比，因此，增加電容器下層電極之 表面積是增加電容器之電容的另一個方向，而目前最普遍的是所謂三度空間電容器 (3-D capacitor )。所述三度空間電容器是在所述轉移閘電晶體之上方或下方的第三 度空間形成電容器，以在有限的平面電路佈局面積內增加電容器之電容値。電容器 製造在所述轉移閘電晶體之上方時，稱爲堆疊式電容器（stackcapacitor)，而電容 器製造在所述轉移閘電晶體之下’方時稱爲凹溝式電容器（trenchcapacitor)。目前， 動態隨機存取記憶體工業主要是使用堆叠式電容器結構，例如，日本和韓國的半導 體公司主要是採用堆疊式電容器結構。Printed by the Central Bureau of Economics, Ministry of Economic Affairs, Beigong Consumer Cooperatives 317018 A7 B7 V. Description of the invention (): 1. Technical Field of the Invention The present invention relates to a method for manufacturing capacitors with dynamic random access memory for integrated circuits, In particular, it relates to a method for manufacturing a capacitor of a stacked dynamic random access memory. 2. BACKGROUND OF THE INVENTION A typical dynamic random access memory is to fabricate a gold oxide half field effect transistor and a capacitor on a sand semiconductor wafer. The gold oxide half field effect transistor is used as a transferred gate transistor. The source of the transfer gate transistor is used to connect the lower electrode of the capacitor to form a memory cell of the dynamic random access memory. A large number of memory cells are gathered into a memory cell array. Among them, the source of the transfer gate transistor makes electrical contact with the capacitor, the digital information is stored in the capacitor, and the stored in the capacitor is obtained by the array of the transfer gate transistor, bit line and word line Digital information. On the other hand, there are other circuits around the memory cell array, such as sense amplifiers and other circuits. These external circuits are called the peripheral circuit area. Therefore, the height of the dynamic random access memory must be reached. For the purpose of accumulation density, it is necessary to reduce the size of the memory cell of the memory. However, the reduction in the size of the capacitor will reduce the capacitance value, so that the signal / noise (S / N) ratio of the memory circuit is reduced, causing the circuit to misjudge or Disadvantages such as unstable circuits. For this reason, in order to achieve a high accumulation density of dynamic random access memory, it is necessary to look for more advanced process technology to reduce or maintain the area of the planar circuit layout of the memory cell while maintaining or increasing the capacitance value of the capacitor. The formula for capacitance is C = εΑ / Τ, where ε is the dielectric constant of the capacitor dielectric layer, A is the surface area of the lower electrode of the capacitor, and T is the thickness of the lower electrode of the capacitor, therefore, the capacitance of the capacitor should be increased You can start from two directions. The first direction is to use high dielectric constant materials as the capacitor dielectric layer. For example, Ta205, Ti02 and SrTi03 materials have very high dielectric constants. Unfortunately, due to these high ^ The film quality of the constant material is not good, and there are reliability problems such as the breakdown voltage of the insulating layer, so it has not been applied to dynamic random access memory so far. Since the use of a high dielectric constant capacitor dielectric layer is not feasible, we can see from the formula of capacitance C = εΑΑΓ that the size of the capacitor is proportional to the surface area of the lower electrode of the capacitor. Therefore, increasing the surface area of the lower electrode of the capacitor increases the capacitance of the capacitor In the other direction, the most common at present is the so-called 3-D capacitor. The three-dimensional space capacitor forms a capacitor in the third-degree space above or below the transfer gate transistor to increase the capacitance value of the capacitor within a limited planar circuit layout area. When the capacitor is fabricated above the transfer gate transistor, it is called a stack capacitor, and when the capacitor is fabricated below the transfer gate transistor, it is called a trench capacitor. At present, the dynamic random access memory industry mainly uses stacked capacitor structures. For example, semiconductor companies in Japan and South Korea mainly use stacked capacitor structures.
Watanabe 等人於 IEDM 1988 年第 600 頁所發表之「stacked capacitor cells for high density dynamic RAMs」與 Wakamiya 等人於 VLSI Technology 1989 第 69 頁所發表之 「novel stacked capacitor cell for 64 Mb DRAM」均揭露了堆疊式電容器結構。S. Kimura等人的美國專利第4742018號和T.Ema美國專利4977102號亦揭露堆疊式電 2 本紙張尺度適用中國國家榡準（CNS ) A4规格（210X 297公釐） ------I---裝---I 订 I 線 (请先閱讀背面之注^^項再填寫本頁) 317GJ8 A7 B7 經濟部中央搮準局貞工消费合作社印策 五、發明説明（） 容器以增加電容器電容。日本富士通公司的Masao Taguchi等人在美國專利第 5021357號更揭露了改良的堆疊式電容器結構，稱爲鰭型電容器結構（fin capacitor)，大幅增加電容器電容，提高動態隨機存取記憶體之集積密度。日本 Hitachi公司的T. Kaga等人更在1994年IEDM第927頁之一篇題目爲「A 0.29 um2 ΜΙΜ-CROWN cell and process technology fori-Gigabit DRAMs」的論文，揭露了一種 更爲先進的稱爲「ΜΙΜ-CROWN結構」的堆疊式電容器，這些電容器結構均能大幅 增加電容器的電容値，提高動態隨機存取記憶體元件之集積密度。 本發明揭露了一種利用矽晶粒和氧離子佈植技術形成動態隨機存取記憶體之堆 疊式電容器，能大幅增加電容器的電容値，提高動態隨機存取記憶體元件之集積密 度，適用於0.25微米、集積密度六仟四佰萬位元之動態隨機存取記憶體的製造。 3.發明之簡要說明 本發明的主要目的是提供一種具備高電容之堆疊式電容器的製造方法。 本發明的另一個目的是提供一種具有大的表面積之電容器下層電極之的製造方 法。 本發明的另一個目的是提供一種高集積密度之堆叠式動態隨機存取記憶體的製 造方法。 茲簡述本發明之主要方法如下。首先，以標準製程在矽半導體晶圓上形成隔離 金氧半場效電晶體所需要的場氧化層，接著，形成金氧半場效電晶體和字語線 (wordline )_。接著，沈積一層第一介電層與第二介電層，並利用化學機械式琢磨技 術平坦化所1¾二介電層。接著，利用微影技術與電漿蝕刻技術蝕刻所述第一介電 層與第二介電層以露出所述金氧半場效電晶體之源極，以形成記憶元接觸窗（node contact) 〇 、 接著，沈積一層第一複晶矽和點狀的複晶矽半球型晶粒。接著，利用離子佈植 技術進行「斜向的」氧離子佈植（oblique oxygen implantation)以將氧離子植入所述 點狀的複晶矽半球型晶粒，將所述點狀的複晶矽半球型晶粒變成含氧區域。接著， 在高溫環境中對所述含氧區域進行回火製程（annealing)，以將所述含氧區域轉化 成氧化砂（siliconoxide)。 接著，以所述氧化矽作爲電漿蝕刻保護罩，利用電漿蝕刻技術蝕刻所述第一複 晶矽，使所述窠二複晶矽產至是增加所述第一複晶矽的表面積。 然後，利用微影技術在電容器區域上方形成光阻圖案，然後，利用電漿蝕刻技術對 所述第一複晶矽進行蝕刻，以形成電容器之下層電極。接著，在所述電容器的下層 電極表面形成一層電容器介電層，接著，形成一層第二複晶矽。最後，利用微影技 術與蝕刻技術蝕刻所述電容器介電層和第二複晶矽，以形成電容器的上層電極（top electrode)種具備高集積密度之堆疊式動態隨機存取記憶體於焉完成。 3 (請先閲讀背面之注意事項再填寫本頁) 裝_"Stacked capacitor cells for high density dynamic RAMs" published by Watanabe et al. On page 600 in IEDM 1988 and "novel stacked capacitor cells for 64 Mb DRAM" published by Wakamiya et al. On page 69 of VLSI Technology 1989 Stacked capacitor structure. U.S. Patent No. 4742018 of S. Kimura et al. And U.S. Patent No. 4977102 of T.Ema also disclose that the stacked paper 2 is suitable for the Chinese National Standard (CNS) A4 specification (210X 297 mm) ------ I --- install --- I order I line (please read the note ^^ on the back and then fill out this page) 317GJ8 A7 B7 Ministry of Economic Affairs Central Bureau of Industry and Commerce Consumer Cooperative Institution 5. Policy of invention () Increase the capacitor capacitance. Masao Taguchi and others of Fujitsu Corporation of Japan disclosed an improved stacked capacitor structure in US Patent No. 5021357, called a fin capacitor structure, which greatly increases the capacitor capacitance and improves the accumulation density of dynamic random access memory. . T. Kaga of Hitachi, Japan and others published a paper titled "A 0.29 um2 ΜΙΜ-CROWN cell and process technology fori-Gigabit DRAMs" on page 927 of IEDM in 1994. "MIM-CROWN structure" stacked capacitors, these capacitor structures can greatly increase the capacitance value of the capacitor and improve the accumulation density of dynamic random access memory devices. The invention discloses a stacked capacitor that uses silicon die and oxygen ion implantation technology to form a dynamic random access memory, which can greatly increase the capacitance value of the capacitor and improve the accumulation density of the dynamic random access memory device, which is suitable for 0.25 Manufacture of dynamic random access memory with a micron and an accumulation density of 64 million bits. 3. Brief description of the invention The main object of the present invention is to provide a method for manufacturing a stacked capacitor with high capacitance. Another object of the present invention is to provide a method for manufacturing a lower electrode of a capacitor having a large surface area. Another object of the present invention is to provide a method for manufacturing a stacked dynamic random access memory with high packing density. The main method of the present invention is briefly described as follows. First, a standard process is used to form the field oxide layer required to isolate the metal oxide semi-field transistor on the silicon semiconductor wafer, and then, the metal oxide semi-field transistor and the wordline are formed. Next, a first dielectric layer and a second dielectric layer are deposited, and the two dielectric layers are planarized using chemical mechanical polishing technology. Next, the first dielectric layer and the second dielectric layer are etched using photolithography technology and plasma etching technology to expose the source electrode of the metal oxide semi-field effect transistor to form a memory cell contact (node contact). Next, deposit a layer of first polycrystalline silicon and dot-shaped polycrystalline silicon hemispherical grains. Next, "oblique oxygen implantation" is performed using ion implantation technology to implant oxygen ions into the dotted polycrystalline silicon hemispherical crystal grains, and the dotted polycrystalline silicon Hemispherical grains become oxygen-containing regions. Next, an annealing process is performed on the oxygen-containing region in a high-temperature environment to convert the oxygen-containing region into silicon oxide. Next, the silicon oxide is used as a plasma etching protection cover, and the first polycrystalline silicon is etched using a plasma etching technique to increase the surface area of the first polycrystalline silicon. Then, a photolithography technique is used to form a photoresist pattern over the capacitor area, and then the first polycrystalline silicon is etched using a plasma etching technique to form an underlying electrode of the capacitor. Next, a capacitor dielectric layer is formed on the surface of the lower electrode of the capacitor, and then a second polycrystalline silicon layer is formed. Finally, the lithography and etching techniques are used to etch the capacitor dielectric layer and the second polycrystalline silicon to form the top electrode of the capacitor. A stacked dynamic random access memory with high accumulation density is completed. . 3 (Please read the precautions on the back before filling out this page)
.IT 線 本紙張尺度適用中國國家橾毕（CNS } A4規格（210X297公釐） 317018 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（） . 4. 圖不的簡要說明 圖一到圖十六是本發明之實施例的製程剖面示意圖。 圖一是在矽半導體晶圓上形成轉移閘電晶體和字語線後的製程剖面示意圖； 圖二是沈積一層第一介電層與第二介電層，並平坦化所述第二介電層後的製程剖面 示意圖； 圖三是利用微影技術與電漿蝕刻技術蝕刻所述第一介電層與第二介電層以以形成記 憶元接觸窗（node contact)後的製程剖面示意圖； 圖四是去除光阻圖案後的製程剖面示意圖； ' 圖五是沈積一層第一複晶矽後的製程剖面示意圖； .圖六是形成點狀的複晶矽半球型晶粒後的製程剖面示意圖； 圖七是利用離子佈植技術進行斜向的氧離子佈植（oblique oxygen implantation)以 將氧離子植入所述複晶矽半球型晶粒，將所述複晶矽半球型晶粒變成「含氧 區域」後的製程剖面示意圖； ' 圖八是在高溫環境中對所述含氧區域進行回火製程，以形成氧化矽（siliconoxide) 後的製程剖面示意圖； 圖九是以所述氧化矽作爲蝕刻護罩，利用電漿蝕刻技術蝕刻所述第一複晶矽，以形 成具有凹溝的第一複晶矽後的製程剖面示意圖； 圖十是去除所述氧化矽後的製程剖面示意圖； 圖十一是利用微影技術在所述記憶元接觸窗上方形成光阻圖案後的製程剖面示意 1 C3.1 · 圖， 、 圖十二是利用電漿蝕刻技術對所述第一複晶矽進行蝕刻，以定義電容器之下層電極 的圖案後的製程剖面示意圖； ' 圖十三是#所述光阻圖案後的製程剖面示意圖； 圖十四是吞>斤述電容器的下層電極表面形成一層電容器介電層後的製程剖面示意 圖； 圖十五是形成一層第二複晶矽後的製程剖面示意圖； 圖十六是利用微影技術與磁場增強式活性離子式電漿蝕刻技術蝕刻所述薄的電容器 介電層和第二複晶矽，以形成電容器的上層電極（topelectrode)後的製程剖 面示意圖。 5. 發明之實施例 現在請參考圖一。首先，在電阻値約2.5 ohm-cm、晶格方向（100)之P型矽 半導體基板10上形成場氧化層I2，所述場氧化層I2通常是利用熱氧化技術氧化 所述P型矽半導體基板10而形成，其厚度介於3500埃到6500埃之間，作爲隔 離金氧半場效電晶體之用。當然，也可以利用傳統的淺凹溝隔離技術（Shallow Trench Isolation ; STI)來形成隔離金氧半場效電晶體所需之場氧化層12。然後，在 所述P型矽半導體基板10之表面形成金氧半場效電晶體，所述金氧半場效電晶體 包含有閘氧化層14、閘極16A、覆蓋氧化層18 (cappedoxide)、N-淡摻雜源極/ ----^---：----^— (請先閲讀背面之注^'項再填寫本頁) 訂 線 本紙浪尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） s17〇ls A7 B7 五、發明説明（） ^ 汲極20A/20B、二氧化矽側壁子22和N+源極/汲極24A/24B，如圖一所示。另 外，在形成閘極16A之同時也形成字語線16B，如圖一所示。_ 請再參考圖一。所述閘氧化層Μ是在含乾氧的高溫環境中熱氧化所述P型矽 半導體基板1〇之表面之矽原子而成，_其氧化溫度介於850到1000 °C之間’其厚 度介於50到200埃之間。所述閘極16A則一般是由低壓化學氣相沉積法 (LPCVD)形成之複晶矽16或鎢複晶矽化物所構成，若由複晶矽構成，其厚度介 於2000到4000埃之間，若由鎢複晶矽化物構成，則下層複晶矽之厚度介於1〇〇〇 到2000埃之間，上層矽化鎢之厚度介於1000到2000埃之間，其總厚度也是介 於2000到4000埃之間。所述覆蓋氧化層18是利用低壓化學氣相沉積法形成之無 摻雜的二氧化砂，其厚度介於800到1600埃之間。然後，利用微影技術與電漿蝕 刻技術蝕刻所述覆蓋氧化層18和複晶矽16或鎢複晶矽化物，以形成所述轉移閘電 晶體之閘極結構（gatestructure)，如圖一所示。 形成所述複晶矽16之反應溫度介於500到700 °C之間，而形成之複晶矽16 可以未經摻雜，然後再利用離子佈植技術予以摻雜使具導電性，其離子佈植劑量介 於1E13到1E16原子/平方公分之間，離子佈植能量則介於30到80 Kev之間，以 完成對所述複晶矽16之摻雜。當然，也能利用同步磷離子攙雜方法（in-situ doped)以完成對所述複晶矽16之摻雜，其反應氣體是PH3、SiH4與N2的混合氣 體或AsH3、SiH4與N2的混合氣體，最後的磷離子濃度介於1E20到1E21原子/立 方公分之間，而較理想的磷離子濃度是5E20原子/立方公分之間。對所述複晶矽18 之電漿蝕刻，其反應氣體則是由SF6、Cl2和H'Br組成之混合氣體，能提供效果相 當理想的單向性餓刻、飽刻率和蝕刻均句度，所述複晶矽16對所述閘氧化層14之 蝕刻選擇率也非常高。 ’ (請先閱讀背面之注項再填寫本頁) 裝- 訂 經濟部中失樣準局員工消费合作社印焚 請再參考圖一。接著，利用磷離子佈植技術來形成所述轉移閘電晶體之N-淡 摻雜源極/汲極20A/20B，其離子佈植劑量介於1E13到3E14原子/平方公分之 間，離子佈植能量則介於20到50 Kev之間，如圖一所示，所述N-淡摻雜源極/汲 極20A/20B是爲了降低熱載子效應，以提高所述轉移閘電晶體之可靠性。接著，沉 積一層二氧化矽22，並利用磁場增強式活性離子式電漿蝕刻技術對所述二氧化矽 22進行垂直單向性的回蝕刻，以在所述閘極16之二側形成二氧化矽側壁子22。 而所述二氧化矽22通常是利用低壓化學氣相沉積法形成之無攙雜的二氧化矽，其反 應氣體是矽甲烷或四已基矽酸鹽（Si(C2H50)4)和氧氣，反應溫度介於600到800 °C之間，反應壓力介於0.2到0.4托爾之間，厚度介於500到1500埃之間。最 後，利用離子砷佈植技術形成N+源極24A/汲極24B，其離子佈植劑量介於1E15到 5E16原子/平方公分之間，離子佈植能量則介於30到80 Kev之間，以提供良好的歐 姆接觸，如圖一所示。 現在請參考圖二、圖三與圖四。完成所述轉移閘電晶體和字語線16B的製造 後，接著，沈積一層第一介電層26與第二介電層28，並利用化學機械式琢磨技術 (Chemical Mechanical Polishing ; CMP )平坦化所述第二介電層28，如圖二所示。 5 本紙张尺度適用中國國家梂準（cns ) A4说格（210X297公釐） : 線 Α7 Β7 經濟部中央棣牟局貝工消费合作社印製 五、發明説明（） : 接著’利用微影技術在記憶元接觸窗區域上方形成光阻圖案29，再利用電漿鈾刻技 術蝕刻所述N+源極24A上方之所述第一介電層26與第二介電層28以露出所述 N+'源極24A ’以在所述N+源極24A區域形成記憶元接觸窗30 (nodecontact)， 如圖三所示’未來’堆疊式電容器之下層電極將透過所述記憶元接觸窗30跟所述 轉移閘電晶體之N+源極24A作電性接觸。利用氧氣電漿和硫酸去除所述光阻圖案 29後’如圖四所示。 —所述第一介電層26可以是利用低壓化學氣相沉積法（LPCVD)形成之無攙雜 的二氧化矽，其反應溫度介於330到370。(：之間，其反應氣體是四已基矽酸鹽 (TE0S)與氧化氮（N2〇)或甲烷（silane)與氧化氮（N20)，其厚度介於_ 埃到1600埃之間。所述第二介電層28則是利用大氣壓化學氣相沉積法 (APCVD)或次大氣壓化學氣相沉積法（SACVD)形成之硼磷摻雜二氧化矽 (BPSG)或磷摻雜二氧化砍（PSG)，其反應氣體是TMB、TMP與氧化氮，其厚 度介於3000到8000埃之間。對所述第一介電層26與第二介電層28.之電漿蝕刻 以形成所述記億元接觸窗30，可以利用磁場增強式活性離子式電漿蝕刻技術 (MERIE)或電子迴旋共振電漿蝕刻技術（ECR)或傳統的活性離子式電漿蝕刻技 術（RIE)，而通常是利用磁場增強式活性離子式電漿蝕刻技術，其電漿反應氣體是 三氟氫化碳和氬氣，例如，日本電氣公司（TEL)所製造型號TEL8500之蝕刻機或 美國應用材料公司（appliedmaterials)所製造型號PR5000E之独刻機，其触刻原理 均屬於磁場增強式活性離子式電娥触刻技術，能提供效果相當理想的單向性蝕刻、 蝕刻率和蝕刻均勻度，且所述對P型矽半導體基板10之蝕刻選擇率也非常高。 現在請參考圖五與圖六。然後，沈積一層第一複晶矽32，所述第一複晶矽32 塡滿所述記憶元接觸窗30，如圖五所示。接著，利用低壓化學氣相沉積法形成點狀 的複晶砂半球型晶粒34 (dotHemi-SphericalGrain ; dotHSG)，如圖六所示。另 外，也可以利用低壓化學氣相沉積法形成複晶矽半球型晶粒（HSG)之後再利用電 漿蝕刻技術對複晶矽半球型晶粒進行回蝕刻以形成點狀的複晶矽半球型晶粒34。 所述第一複晶矽32通常是利用同步攙雜之低壓也學氣相沉積法形成，其反應 氣體是PH3、SiH4與N2或AsH3、SiH4與N2的混合氣體，攙雜有磷和砷等雜質 原子，其反應溫度介於500到650 °C之間，其厚度介於2000到6000埃之間，以塡 滿所述記憶元接觸窗30作考慮。所述第一複晶矽32必需具備導電性，其雜質離子 濃度介於1E20到1E21原子/立方公分之間，而較理想的濃度是5E20原子/立方公 分。形成所述複晶矽半球型晶粒.34之反應溫度介於500到750 °C之間，其直徑介 於50到500埃之間。 f 現在請參考圖七與圖八。接著，利用離子佈植技術進行斜向的氧離子佈植35 / (oblique oxygen implantation)以將氧離子植入所述複晶砍半球型晶粒34，將所述 /複晶矽半球型晶粒34變成含氧區域34a，如圖七所示。接著」高溫環罕 !中對所沭含氣區域34a谁行冋*製稈40 (annealing上~，以將所述含氧區藏 ^成氧,ϋ八^示7斜向的氧離子佈植35之斜向離子入 6 (請先閲讀背面之注^'項再填寫本育) •裝· 訂 本紙張尺度適用中國國家梂準（CNS ) Α4規格（2丨0Χ 297公釐） 3!7〇ί8 Α7 Β7 經濟部中央標準局員工消费合作杜印裝 五、發明説明（） ： 射角度介於〇。到50。之間’並且，一邊進行斜向的氧離子佈植35時’同時一邊轉 動所述P型矽半導體基板1Q。 現在請參考圖九與圖十。接著’以所述氳乍爲電费帥，刻保護罩’利用 磁場增強式活性離子式電漿蝕刻技術蝕刻所述第一複晶矽32，使所^第一複晶矽 32產生凹槽，使所述第一複晶矽32成爲第一複晶矽32a ’如圖九所示’凹槽之功 用是增加所述第一複晶矽32的表面積。然後，利用電漿蝕刻或稀釋®氟酸溶液或蒸 氣氫氟酸（vapor HF)去除所述氧化矽34b，如圖十所示。對所述第一複晶矽32之 磁場增強式活性離子式電漿蝕刻，其電漿反應氣體是六氟化硫、氧氣和溴化氫之混 合氣體，能提供效果相當理想的蝕刻率和餓刻均勻度，並且’所述第一複晶矽32 對所述氧化矽34b之蝕刻選擇率非常高’介於20到5〇之間。 現在請參考圖十一'圖十二與圖十三。然後，利用微影技術在電容器區域上方 形成光阻圖案44 ’如圖^一所示’所述光阻圖秦44是正光阻’其厚度介於.8000到 12000埃之間。然後，利用磁場增強式活性離子式電漿蝕刻技術對所述第一複晶矽 32a進行蝕刻，使成爲第一複晶矽32b，以定義電容器之下層電極的圖案’如圖十 二所示。利用氧氣電漿和硫酸去除所述光阻圖案44後’所述第一複晶矽32b構成 了電容器的下層電極3¾，並且，所述下層電極32b透過所述記憶元接觸窗30跟 所述轉移閘電晶體之N+源極24A作電性接觸，如圖十三所示。同樣的，對所述第 一複晶矽32a之電漿蝕刻以形成電容器的下層電極32b，磁場增強式活性離子式電 漿蝕刻技術，其電漿反應氣體是六氟化硫'氧氣和溴化氫之混合氣體’能提供效果 相當理想的蝕刻率和蝕刻均勻度，並且，所述第一複晶矽32a對光阻圖案44之蝕 刻選擇率非常高，介於10到20之間。請注意，由所述第一複晶矽32b構成之電容 器的下層電極32b具有凹溝，故能大幅增加電容器電容’縮小電路佈局面積’提高 動態隨機存取15憶體之集積密度。 - 現在請參考圖十四、圖十五與圖十六。接著，以標準製程在所述電容器的下層 電極32b表面形成一層厚度極薄的電容器介電層46，如圖十四所示，接著，形成 一層第二複晶矽48，如圖十五所示。最後，利用微影枝術與磁場增強式活性離子式 電漿蝕刻技術蝕亥卩所述薄的電容器介電層46和第二複晶矽48，以形成電容器的上 層電極（top electrode)，如圖十六所示，一種具備高集積密度之堆疊式動態隨機存 取記憶體於焉完成。 所述電容器介電層46通常是由氧化氮化砂（Oxynitride)、氮化砂（Nitride) 和二氧化矽（Oxide)藉由下述方法形成。首先，在溫度介於800°C到950°C之間時 熱氧化由複晶矽構成之所述下層電極32b，以形成厚度介於40埃到200埃之間的 氧化矽。接著，在溫度介於650bC到750°C之間時以低壓化學氣相沉積法形成厚度 介於4〇埃到60埃之間的氮化砂。最後，在溫度介於800°C到950°C之間時氧化所 述氮化矽，以形成厚度介於20埃到50埃之間的氧化氮化矽。自然，所述電容器介 電層46亦可由其它高介電常數材料組成，例如五氧二钽（Ta2〇5 )，或由Ti02 和SrTi03等高介電常數材料所組成。 7 (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 本紙張尺度適用中國國家橾準（CNS ) Α4说格（210Χ297公釐） 五、發明説明（） A7 B7 所述第二複晶矽48之形成方法跟第一複晶矽32 —樣，.是利用同步攙雜之低 壓化學氣相沉積法形成’其反應氣體是PH3 ' SiH4與N2或AsH3、SiH4與N2的 混合氣體，攙雜有磷和砷等雜質原子’其反應溫度介於500到650 °C之間’其厚度 介於1000到2000埃之間，所述第二複晶矽48也必需具備導電性，其雜質離子濃 度介於1E20到1E21原子/立方公分之間，而較理想的濃度是5E20原子/立方公分。 而形成電容器的上層電極48之電漿蝕刻，可以利用磁場增強式活性離子式電漿蝕刻 技術（MERIE)，其電漿反應氣體是六氟化硫、氧氣和溴化氫之混合氣體。 以上係以最佳實施例來闡述本發明，而非限制本發明，並且，熟知半導體技藝 之人士皆能明瞭’適當而作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 (请先閲讀背面之注項再填寫本頁) -裝_ 訂 r -線 經濟部中央樣準局貝工消費合作社印裝.IT line copy paper standard is applicable to China National Standard (CNS} A4 specification (210X297mm) 317018 A7 B7 Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (). 4. Brief description of figure 1 16 is a schematic cross-sectional process diagram of an embodiment of the present invention. FIG. 1 is a schematic cross-sectional process diagram after forming a transfer gate transistor and word lines on a silicon semiconductor wafer; FIG. 2 is a deposition of a first dielectric layer and The second dielectric layer, and a schematic cross-sectional view of the process after planarizing the second dielectric layer; FIG. 3 is the etching of the first dielectric layer and the second dielectric layer using lithography and plasma etching Figure 4 is a schematic cross-sectional view of the process after the formation of a memory cell contact (node contact); Figure 4 is a schematic cross-sectional view of the process after removing the photoresist pattern; Figure 5 is a schematic cross-sectional view of the process after depositing a layer of first polycrystalline silicon; Figure 6 is the formation A schematic cross-sectional view of the process after the dot-shaped polycrystalline silicon hemispherical crystal grains; FIG. 7 is an oblique oxygen implantation using ion implantation technology to implant oxygen ions into the polycrystal Hemispherical grains, a schematic cross-sectional view of the process after the polycrystalline silicon hemispherical grains are changed into "oxygen-containing regions"; FIG. 8 is a tempering process for the oxygen-containing regions in a high-temperature environment to form silicon oxide (Siliconoxide) cross-sectional schematic diagram of the process; FIG. 9 uses the silicon oxide as an etching shield to etch the first polycrystalline silicon using plasma etching technology to form the first polycrystalline silicon with recesses Figure 10 is a schematic cross-sectional view of the process after removing the silicon oxide; Figure 11 is a schematic cross-sectional view of the process after forming a photoresist pattern on the memory cell contact window using lithography technology. FIG. 12 is a schematic cross-sectional view of the process after the first polycrystalline silicon is etched using plasma etching technology to define the pattern of the underlying electrode of the capacitor; FIG. 13 is a schematic cross-sectional view of the process after the photoresist pattern Figure 14 is a schematic cross-sectional view of the process after forming a capacitor dielectric layer on the lower electrode surface of the capacitor; Figure 15 is a cross-sectional view of the process after forming a second polycrystalline silicon layer; Figure; Figure 16 is a cross-sectional view of the process after etching the thin capacitor dielectric layer and the second polysilicon to form the top electrode of the capacitor using lithography and magnetic field enhanced active ion plasma etching technology Schematic diagram. 5. Embodiments of the invention now refer to FIG. 1. First, a field oxide layer I2 is formed on a P-type silicon semiconductor substrate 10 having a resistance value of about 2.5 ohm-cm and a lattice direction (100), the field oxide layer I2 is usually formed by oxidizing the P-type silicon semiconductor substrate 10 by thermal oxidation technology, and its thickness is between 3500 Angstroms and 6500 Angstroms. It is used to isolate the metal oxide half-field effect transistor. The trench isolation technology (Shallow Trench Isolation; STI) is used to form the field oxide layer 12 required for isolating the metal oxide half field effect transistor. Then, a metal oxide half field effect transistor is formed on the surface of the P-type silicon semiconductor substrate 10, the metal oxide half field effect transistor includes a gate oxide layer 14, a gate electrode 16A, a capped oxide layer 18 (cappedoxide), N- Lightly doped source / ---- ^ ---: ---- ^ — (please read the note ^ 'on the back before filling in this page) The paper size of the line book is applicable to the Chinese National Standard (CNS) A4 Specifications (210X297mm) s17〇ls A7 B7 V. Description of the invention () ^ Drain 20A / 20B, silicon dioxide sidewall 22 and N + source / drain 24A / 24B, as shown in Figure 1. In addition, the word line 16B is formed at the same time as the gate electrode 16A is formed, as shown in FIG. _ Please refer to Figure 1 again. The gate oxide layer M is formed by thermally oxidizing silicon atoms on the surface of the P-type silicon semiconductor substrate 10 in a high-temperature environment containing dry oxygen, whose oxidation temperature is between 850 and 1000 ° C and its thickness Between 50 and 200 Angstroms. The gate electrode 16A is generally composed of polycrystalline silicon 16 or tungsten polycrystalline silicide formed by low pressure chemical vapor deposition (LPCVD). If it is composed of polycrystalline silicon, its thickness is between 2000 and 4000 angstroms If made of tungsten polycrystalline silicide, the thickness of the lower polycrystalline silicon is between 1000 and 2000 angstroms, the thickness of the upper tungsten silicide is between 1000 and 2000 angstroms, and the total thickness is also between 2000 To 4000 Angstroms. The cover oxide layer 18 is undoped sand dioxide formed by low-pressure chemical vapor deposition and has a thickness between 800 and 1600 angstroms. Then, the photolithography technique and the plasma etching technique are used to etch the cover oxide layer 18 and the polycrystalline silicon 16 or tungsten polycrystalline silicide to form the gate structure of the transfer gate transistor, as shown in FIG. 1 Show. The reaction temperature for forming the polycrystalline silicon 16 is between 500 and 700 ° C, and the formed polycrystalline silicon 16 can be undoped, and then doped using ion implantation technology to make it conductive, and its ions The implantation dose is between 1E13 and 1E16 atoms / cm 2, and the ion implantation energy is between 30 and 80 Kev to complete the doping of the polycrystalline silicon 16. Of course, the in-situ doped method can also be used to dope the polycrystalline silicon 16, the reaction gas is a mixed gas of PH3, SiH4 and N2 or a mixed gas of AsH3, SiH4 and N2 The final phosphorus ion concentration is between 1E20 and 1E21 atoms / cm3, while the ideal phosphorus ion concentration is between 5E20 atoms / cm3. For the plasma etching of the polycrystalline silicon 18, the reaction gas is a mixed gas composed of SF6, Cl2 and H'Br, which can provide the ideal unidirectional hungry etching, saturation rate and etching uniformity The etching selectivity of the polysilicon 16 to the gate oxide layer 14 is also very high. ’(Please read the notes on the back and then fill out this page) Binding-Bookmark Printing and Burning by the Consumer Consumer Cooperative of the Bureau of Loss and Accuracy of the Ministry of Economy Please refer to Figure 1 again. Next, phosphorus ion implantation technology is used to form the N-lightly doped source / drain 20A / 20B of the transfer gate transistor. The ion implantation dose is between 1E13 and 3E14 atoms / cm2. The plant energy is between 20 and 50 Kev. As shown in Fig. 1, the N-lightly doped source / drain 20A / 20B is to reduce the hot carrier effect and improve the transfer gate transistor reliability. Next, a layer of silicon dioxide 22 is deposited, and the magnetic field enhanced active ion plasma etching technique is used to vertically etch back the silicon dioxide 22 unidirectionally to form dioxide on both sides of the gate 16 Silicon side wall 22. The silicon dioxide 22 is usually an impurity-free silicon dioxide formed by low-pressure chemical vapor deposition. The reaction gas is silicon methane or tetrahexyl silicate (Si (C2H50) 4) and oxygen. The reaction temperature Between 600 and 800 ° C, the reaction pressure is between 0.2 and 0.4 Torr, and the thickness is between 500 and 1500 Angstroms. Finally, the ion implantation technology is used to form the N + source 24A / drain 24B. The ion implantation dose is between 1E15 and 5E16 atoms / cm2, and the ion implantation energy is between 30 and 80 Kev. Provide good ohmic contact, as shown in Figure 1. Now please refer to Figure 2, Figure 3 and Figure 4. After the manufacture of the transfer gate transistor and the word line 16B is completed, a first dielectric layer 26 and a second dielectric layer 28 are deposited and planarized using chemical mechanical polishing (CMP) The second dielectric layer 28 is shown in FIG. 2. 5 This paper scale is applicable to the Chinese National Standard (cns) A4 format (210X297mm): Line A7 Β7 Printed by the Beigong Consumer Cooperative of the Central Dimu Bureau of the Ministry of Economy V. Description of invention (): Then use the lithography technology in A photoresist pattern 29 is formed over the memory cell contact window area, and then the first dielectric layer 26 and the second dielectric layer 28 above the N + source electrode 24A are etched using plasma uranium etching technology to expose the N + 'source Electrode 24A 'to form a memory cell contact window 30 (node contact) in the area of the N + source electrode 24A, as shown in FIG. 3, the underlying electrode of the "future" stacked capacitor will follow the transfer gate through the memory cell contact window 30 The N + source 24A of the transistor makes electrical contact. After removing the photoresist pattern 29 with oxygen plasma and sulfuric acid, as shown in FIG. 4. -The first dielectric layer 26 may be a doped silicon dioxide formed by low pressure chemical vapor deposition (LPCVD) with a reaction temperature ranging from 330 to 370. (: Between, the reaction gas is tetrahexyl silicate (TEOS) and nitrogen oxide (N2〇) or methane (silane) and nitrogen oxide (N20), and its thickness is between _ Angstrom and 1600 Angstrom. The second dielectric layer 28 is a boron-phosphorus doped silicon dioxide (BPSG) or phosphorus-doped silicon dioxide (APSG) formed by atmospheric pressure chemical vapor deposition (APCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) ( PSG), the reaction gases are TMB, TMP and nitrogen oxide, and the thickness is between 3000 and 8000 angstroms. The plasma of the first dielectric layer 26 and the second dielectric layer 28 is etched to form the The billion yuan contact window 30 can use the magnetic field enhanced active ion plasma etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or the traditional active ion plasma etching technology (RIE), which is usually Using magnetic field-enhanced active ion plasma etching technology, the plasma reaction gas is trifluorohydrocarbon and argon, for example, the etching machine of TEL8500 manufactured by Japan Electric Company (TEL) or the American Applied Materials (appliedmaterials) The unique engraving machine of the model PR5000E, whose touch engraving principles belong to Magnetic-field-enhanced active ion electro-etching technology can provide highly ideal unidirectional etching, etching rate and etching uniformity, and the etching selectivity of the P-type silicon semiconductor substrate 10 is also very high. Now please Refer to FIGS. 5 and 6. Then, a layer of first polycrystalline silicon 32 is deposited, and the first polycrystalline silicon 32 fills the memory cell contact window 30, as shown in FIG. 5. Then, low pressure chemical vapor deposition is used Method to form dot-shaped polycrystalline sand hemispherical grains 34 (dotHemi-SphericalGrain; dotHSG), as shown in Figure 6. In addition, low-pressure chemical vapor deposition can also be used to form polycrystalline silicon hemispherical grains (HSG) Then, plasma etching technology is used to etch back the polycrystalline silicon hemispherical crystal grains to form dot-shaped polycrystalline silicon hemispherical crystal grains 34. The first polycrystalline silicon 32 is usually synchronously doped with low pressure to learn gas phase. Formed by deposition method, the reaction gas is a mixed gas of PH3, SiH4 and N2 or AsH3, SiH4 and N2, doped with impurity atoms such as phosphorus and arsenic, the reaction temperature is between 500 and 650 ° C, and the thickness is between 2000 Between 6000 Angstroms, with the notes filled The yin contact window 30 is considered. The first polycrystalline silicon 32 must have conductivity, and its impurity ion concentration is between 1E20 and 1E21 atoms / cubic centimeter, and the ideal concentration is 5E20 atoms / cubic centimeter. The reaction temperature of the polycrystalline silicon hemispherical grain .34 is between 500 and 750 ° C, and its diameter is between 50 and 500 angstroms. F Now refer to Figures 7 and 8. Next, use ion cloth The implantation technology performs oblique oxygen implantation 35 / (oblique oxygen implantation) to implant oxygen ions into the polycrystal and cut the hemispherical crystal grains 34, so that the / polycrystalline silicon hemispherical crystal grains 34 become oxygen-containing regions 34a, as shown in Figure 7. Then, "High temperature is rare! Who will do the stalks 40 (annealing up ~ to the oxygen-containing area 34a of the Shushu? 35 oblique ion input 6 (please read the note ^ 'on the back and fill in this education) • The size of the paper for binding and binding is applicable to China National Standards (CNS) Α4 specifications (2 丨 0Χ 297mm) 3! 7 〇ί8 Α7 Β7 Ministry of Economic Affairs Central Standards Bureau employee consumption cooperation du printed version V. Invention description (): The shooting angle is between 0. to 50. 'And, while performing oblique oxygen ion implantation at 35 hours' at the same time Rotate the P-type silicon semiconductor substrate 1Q. Now please refer to Figure 9 and Figure 10. Then 'use the 揲 Cha as the electricity charge handsome, engraved protective cover' using magnetic field enhanced active ion plasma etching technology to etch the first A polycrystalline silicon 32, so that the first polycrystalline silicon 32 produces a groove, so that the first polycrystalline silicon 32 becomes the first polycrystalline silicon 32a 'as shown in Figure 9' the function of the groove is to increase the The surface area of the first polycrystalline silicon 32. Then, the plasma etching or dilution ® hydrofluoric acid solution or vapor hydrofluoric acid (vapor HF) is used to remove the surface Silicon oxide 34b, as shown in Figure 10. The magnetic field enhanced active ion plasma etching of the first polycrystalline silicon 32, the plasma reaction gas is a mixed gas of sulfur hexafluoride, oxygen and hydrogen bromide, It can provide an ideal etching rate and etching uniformity, and the etching selectivity of the first polycrystalline silicon 32 to the silicon oxide 34b is very high, ranging from 20 to 50. Please refer to the figure now Eleven 'Figures twelve and thirteen. Then, using photolithography technology to form a photoresist pattern 44 above the capacitor region' as shown in Figure ^ 1 'The photoresist Qin 44 is a positive photoresist' whose thickness is between. Between 8000 and 12000 angstroms. Then, the first polycrystalline silicon 32a is etched using a magnetic field enhanced active ion plasma etching technique to become the first polycrystalline silicon 32b to define the pattern of the underlying electrode of the capacitor ' As shown in Fig. 12. After removing the photoresist pattern 44 with oxygen plasma and sulfuric acid, the first polycrystalline silicon 32b constitutes the lower electrode 32 of the capacitor, and the lower electrode 32b passes through the memory cell Contact window 30 and the N + source of the transfer gate transistor 24A is used for electrical contact, as shown in FIG. 13. Similarly, the plasma of the first polycrystalline silicon 32a is etched to form the lower electrode 32b of the capacitor. The magnetic field enhanced active ion plasma etching technology The slurry reaction gas is sulfur hexafluoride 'a mixed gas of oxygen gas and hydrogen bromide', which can provide an ideal etching rate and etching uniformity, and the etching selectivity of the first polycrystalline silicon 32a to the photoresist pattern 44 Very high, between 10 and 20. Please note that the lower electrode 32b of the capacitor composed of the first polycrystalline silicon 32b has a concave groove, so it can greatly increase the capacitor capacitance, "reducing the circuit layout area" and improving dynamic random access. Take the accumulation density of 15 memories. -Now please refer to Figure 14, Figure 15 and Figure 16. Next, a standard process is used to form a very thin capacitor dielectric layer 46 on the surface of the lower electrode 32b of the capacitor, as shown in FIG. 14, and then, a second layer of polycrystalline silicon 48 is formed, as shown in FIG. 15 . Finally, the thin capacitor dielectric layer 46 and the second polycrystalline silicon 48 are etched by photolithography and magnetic field enhanced active ion plasma etching technology to form the top electrode of the capacitor, such as As shown in Figure 16, a stacked dynamic random access memory with high accumulation density is completed in Yan. The capacitor dielectric layer 46 is generally formed of Oxynitride, Nitrid and Oxide by the following method. First, the lower electrode 32b composed of polycrystalline silicon is thermally oxidized at a temperature between 800 ° C and 950 ° C to form silicon oxide with a thickness between 40 angstroms and 200 angstroms. Next, at a temperature between 650bC and 750 ° C, nitrided sand with a thickness between 40 Angstroms and 60 Angstroms is formed by low-pressure chemical vapor deposition. Finally, the silicon nitride is oxidized at a temperature between 800 ° C and 950 ° C to form a silicon oxide nitride with a thickness between 20 Angstroms and 50 Angstroms. Naturally, the capacitor dielectric layer 46 may also be composed of other high dielectric constant materials, such as tantalum pentoxide (Ta205), or high dielectric constant materials such as Ti02 and SrTi03. 7 (Please read the precautions on the back before filling in this page)-Packing. The size of the bound paper is applicable to the Chinese National Standard (CNS) Α4 format (210Χ297mm) 5. Description of the invention () A7 B7 The second complex The formation method of crystalline silicon 48 is the same as that of the first polycrystalline silicon 32. It is formed by the low-pressure chemical vapor deposition method of simultaneous doping. The reaction gas is PH3. The mixed gas of SiH4 and N2 or AsH3, SiH4 and N2 is mixed. There are impurity atoms such as phosphorus and arsenic 'the reaction temperature is between 500 and 650 ° C' and the thickness is between 1000 and 2000 angstroms, the second polycrystalline silicon 48 must also have conductivity, and the concentration of impurity ions Between 1E20 and 1E21 atoms / cubic centimeter, and the ideal concentration is 5E20 atoms / cubic centimeter. For plasma etching of the upper electrode 48 forming the capacitor, magnetic field enhanced active ion plasma etching technology (MERIE) can be used, and the plasma reaction gas is a mixed gas of sulfur hexafluoride, oxygen, and hydrogen bromide. The above is a description of the present invention with the preferred embodiments, rather than limiting the present invention, and those skilled in the art of semiconductors can understand that 'appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor Departs from the spirit and scope of the present invention. (Please read the notes on the back before filling in this page) -Installation_ Order r -Line Printed by the Beige Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs