TW331635B - Memory device for semiconductor. - Google Patents

Memory device for semiconductor.

Info

Publication number
TW331635B
TW331635B TW086105623A TW86105623A TW331635B TW 331635 B TW331635 B TW 331635B TW 086105623 A TW086105623 A TW 086105623A TW 86105623 A TW86105623 A TW 86105623A TW 331635 B TW331635 B TW 331635B
Authority
TW
Taiwan
Prior art keywords
voltage
memory device
low
bit line
memory cell
Prior art date
Application number
TW086105623A
Other languages
English (en)
Inventor
Shinji Tanaka
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW331635B publication Critical patent/TW331635B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
TW086105623A 1997-01-31 1997-04-29 Memory device for semiconductor. TW331635B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9019081A JPH10214497A (ja) 1997-01-31 1997-01-31 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW331635B true TW331635B (en) 1998-05-11

Family

ID=11989504

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086105623A TW331635B (en) 1997-01-31 1997-04-29 Memory device for semiconductor.

Country Status (6)

Country Link
US (1) US5825699A (zh)
EP (1) EP0895160B1 (zh)
JP (1) JPH10214497A (zh)
KR (1) KR100284150B1 (zh)
DE (1) DE69719319T2 (zh)
TW (1) TW331635B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292416B1 (en) * 1998-02-11 2001-09-18 Alliance Semiconductor Corporation Apparatus and method of reducing the pre-charge time of bit lines in a random access memory
JP3204200B2 (ja) * 1998-02-25 2001-09-04 日本電気株式会社 半導体メモリ装置
DE19963502B4 (de) * 1999-12-28 2008-01-03 Infineon Technologies Ag Schaltungsanordnung für einen integrierten Halbleiterspeicher mit Spaltenzugriff
JP3911440B2 (ja) * 2002-05-13 2007-05-09 松下電器産業株式会社 半導体記憶装置
KR100761381B1 (ko) * 2006-09-06 2007-09-27 주식회사 하이닉스반도체 비트라인 센스앰프 미스매치판단이 가능한 메모리장치.

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074237A (en) * 1976-03-08 1978-02-14 International Business Machines Corporation Word line clamping circuit and decoder
US5255228A (en) * 1989-01-10 1993-10-19 Matsushita Electronics Corporation Semiconductor memory device with redundancy circuits
JPH0378199A (ja) * 1989-08-18 1991-04-03 Mitsubishi Electric Corp 不揮発性半導体メモリ
JP2617617B2 (ja) * 1990-11-16 1997-06-04 九州日本電気株式会社 半導体メモリ
JP3115623B2 (ja) * 1991-02-25 2000-12-11 株式会社日立製作所 スタティック型ｒａｍ
JP3226579B2 (ja) * 1991-12-24 2001-11-05 沖電気工業株式会社 半導体記憶装置
JPH0877776A (ja) * 1994-09-06 1996-03-22 Mitsubishi Electric Corp 半導体記憶装置
JP3100849B2 (ja) * 1994-11-11 2000-10-23 株式会社東芝 半導体記憶装置
JP3542649B2 (ja) * 1994-12-28 2004-07-14 株式会社ルネサステクノロジ 半導体記憶装置およびその動作方法

Also Published As

Publication number Publication date
JPH10214497A (ja) 1998-08-11
US5825699A (en) 1998-10-20
KR100284150B1 (ko) 2001-03-02
DE69719319D1 (de) 2003-04-03
EP0895160A1 (en) 1999-02-03
KR19980069831A (ko) 1998-10-26
EP0895160B1 (en) 2003-02-26
DE69719319T2 (de) 2003-10-16

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