TW362194B - Method and apparatus for decreasing thread switch latency in a multithread processor - Google Patents

Method and apparatus for decreasing thread switch latency in a multithread processor

Info

Publication number
TW362194B
TW362194B TW086117440A TW86117440A TW362194B TW 362194 B TW362194 B TW 362194B TW 086117440 A TW086117440 A TW 086117440A TW 86117440 A TW86117440 A TW 86117440A TW 362194 B TW362194 B TW 362194B
Authority
TW
Taiwan
Prior art keywords
thread
instruction queue
instructions
multithread processor
thread switch
Prior art date
Application number
TW086117440A
Other languages
English (en)
Chinese (zh)
Inventor
William Thomas Flynn
Philip Rogers Hiller Iii
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW362194B publication Critical patent/TW362194B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW086117440A 1997-03-28 1997-11-21 Method and apparatus for decreasing thread switch latency in a multithread processor TW362194B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/829,518 US5907702A (en) 1997-03-28 1997-03-28 Method and apparatus for decreasing thread switch latency in a multithread processor

Publications (1)

Publication Number Publication Date
TW362194B true TW362194B (en) 1999-06-21

Family

ID=25254763

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086117440A TW362194B (en) 1997-03-28 1997-11-21 Method and apparatus for decreasing thread switch latency in a multithread processor

Country Status (7)

Country Link
US (1) US5907702A (ja)
JP (1) JP3573943B2 (ja)
KR (1) KR100274268B1 (ja)
CN (1) CN1092360C (ja)
GB (1) GB2324392B (ja)
SG (1) SG63818A1 (ja)
TW (1) TW362194B (ja)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5835705A (en) * 1997-03-11 1998-11-10 International Business Machines Corporation Method and system for performance per-thread monitoring in a multithreaded processor
US6018759A (en) * 1997-12-22 2000-01-25 International Business Machines Corporation Thread switch tuning tool for optimal performance in a computer processor
US6044447A (en) * 1998-01-30 2000-03-28 International Business Machines Corporation Method and apparatus for communicating translation command information in a multithreaded environment
US6457064B1 (en) * 1998-04-27 2002-09-24 Sun Microsystems, Inc. Method and apparatus for detecting input directed to a thread in a multi-threaded process
US20010032307A1 (en) * 1998-12-30 2001-10-18 Joseph Rohlman Micro-instruction queue for a microprocessor instruction pipeline
HK1046049A1 (zh) * 1999-09-01 2002-12-20 Intel Corporation 用於多线程处理器的分支指令
KR100678930B1 (ko) * 1999-10-11 2007-02-07 삼성전자주식회사 디지털 시그널 프로세서를 위한 실시간 제어 시스템
US6629236B1 (en) 1999-11-12 2003-09-30 International Business Machines Corporation Master-slave latch circuit for multithreaded processing
US6931641B1 (en) 2000-04-04 2005-08-16 International Business Machines Corporation Controller for multiple instruction thread processors
US7093109B1 (en) 2000-04-04 2006-08-15 International Business Machines Corporation Network processor which makes thread execution control decisions based on latency event lengths
US20030188141A1 (en) * 2002-03-29 2003-10-02 Shailender Chaudhry Time-multiplexed speculative multi-threading to support single-threaded applications
US7139898B1 (en) * 2000-11-03 2006-11-21 Mips Technologies, Inc. Fetch and dispatch disassociation apparatus for multistreaming processors
US7234139B1 (en) * 2000-11-24 2007-06-19 Catharon Productions, Inc. Computer multi-tasking via virtual threading using an interpreter
US8762581B2 (en) * 2000-12-22 2014-06-24 Avaya Inc. Multi-thread packet processor
US7149880B2 (en) * 2000-12-29 2006-12-12 Intel Corporation Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor
US7320065B2 (en) 2001-04-26 2008-01-15 Eleven Engineering Incorporated Multithread embedded processor with input/output capability
US6965982B2 (en) * 2001-06-29 2005-11-15 International Business Machines Corporation Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread
CN100449478C (zh) * 2002-05-31 2009-01-07 德拉华州大学 用于实时多线程处理的方法和装置
US7275247B2 (en) * 2002-09-19 2007-09-25 International Business Machines Corporation Method and apparatus for handling threads in a data processing system
US7062606B2 (en) * 2002-11-01 2006-06-13 Infineon Technologies Ag Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events
US7076616B2 (en) 2003-03-24 2006-07-11 Sony Corporation Application pre-launch to reduce user interface latency
US7496915B2 (en) * 2003-04-24 2009-02-24 International Business Machines Corporation Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes
US20040226011A1 (en) * 2003-05-08 2004-11-11 International Business Machines Corporation Multi-threaded microprocessor with queue flushing
US7653904B2 (en) * 2003-09-26 2010-01-26 Intel Corporation System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detected
US8140829B2 (en) * 2003-11-20 2012-03-20 International Business Machines Corporation Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution
US7430737B2 (en) * 2003-12-04 2008-09-30 Sun Microsystems, Inc. Processor and method for supporting compiler directed multithreading management
US7441101B1 (en) * 2003-12-10 2008-10-21 Cisco Technology, Inc. Thread-aware instruction fetching in a multithreaded embedded processor
US7360064B1 (en) 2003-12-10 2008-04-15 Cisco Technology, Inc. Thread interleaving in a multithreaded embedded processor
US7617499B2 (en) * 2003-12-18 2009-11-10 International Business Machines Corporation Context switch instruction prefetching in multithreaded computer
US7493621B2 (en) * 2003-12-18 2009-02-17 International Business Machines Corporation Context switch data prefetching in multithreaded computer
US7206922B1 (en) 2003-12-30 2007-04-17 Cisco Systems, Inc. Instruction memory hierarchy for an embedded processor
US8074051B2 (en) * 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
US20050246461A1 (en) * 2004-04-29 2005-11-03 International Business Machines Corporation Scheduling threads in a multi-processor computer
US20050270297A1 (en) * 2004-06-08 2005-12-08 Sony Corporation And Sony Electronics Inc. Time sliced architecture for graphics display system
US8099533B2 (en) * 2004-08-03 2012-01-17 Nxp B.V. Controller and a method for controlling the communication between a processor and external peripheral device
US7487503B2 (en) 2004-08-12 2009-02-03 International Business Machines Corporation Scheduling threads in a multiprocessor computer
US20060112208A1 (en) * 2004-11-22 2006-05-25 International Business Machines Corporation Interrupt thresholding for SMT and multi processor systems
GB0516474D0 (en) * 2005-08-10 2005-09-14 Symbian Software Ltd Pre-emptible context switching in a computing device
US7913255B2 (en) * 2005-10-20 2011-03-22 Qualcomm Incorporated Background thread processing in a multithread digital signal processor
US7873816B2 (en) * 2008-11-20 2011-01-18 International Business Machines Corporation Pre-loading context states by inactive hardware thread in advance of context switch
CN102426553B (zh) * 2011-11-11 2014-05-28 中国科学技术大学 基于双缓存预读的向用户传输数据的方法和装置
CN104081343B (zh) * 2012-01-31 2016-08-17 国际商业机器公司 事务存储器的主分支指令
US9170968B2 (en) * 2012-09-27 2015-10-27 Intel Corporation Device, system and method of multi-channel processing
JP2015106167A (ja) * 2013-11-28 2015-06-08 ソニー株式会社 情報処理装置、情報処理方法および記憶媒体
US20160283233A1 (en) * 2015-03-24 2016-09-29 Freescale Semiconductor, Inc. Computer systems and methods for context switching
JP7298624B2 (ja) 2018-12-11 2023-06-27 サンケン電気株式会社 プロセッサ及びパイプライン処理方法
KR102874947B1 (ko) * 2025-05-23 2025-10-23 주식회사 블루타일랩 영상 처리 초기 지연 방지를 위한 지능형 웜업 시스템 및 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US4926323A (en) * 1988-03-03 1990-05-15 Advanced Micro Devices, Inc. Streamlined instruction processor
EP0381655A3 (en) * 1989-01-31 1992-12-02 International Business Machines Corporation Method for synchronizing the dispatching of tasks among multitasking operating systems
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
US5179702A (en) * 1989-12-29 1993-01-12 Supercomputer Systems Limited Partnership System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5109512A (en) * 1990-05-31 1992-04-28 International Business Machines Corporation Process for dispatching tasks among multiple information processors
US5452452A (en) * 1990-06-11 1995-09-19 Cray Research, Inc. System having integrated dispatcher for self scheduling processors to execute multiple types of processes
DE69130138T2 (de) * 1990-06-29 1999-05-06 Digital Equipment Corp., Maynard, Mass. Sprungvorhersageeinheit für hochleistungsfähigen Prozessor
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5515538A (en) * 1992-05-29 1996-05-07 Sun Microsystems, Inc. Apparatus and method for interrupt handling in a multi-threaded operating system kernel
US5442756A (en) * 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
US5490272A (en) * 1994-01-28 1996-02-06 International Business Machines Corporation Method and apparatus for creating multithreaded time slices in a multitasking operating system

Also Published As

Publication number Publication date
HK1011567A1 (en) 1999-07-16
KR19980079506A (ko) 1998-11-25
GB2324392A (en) 1998-10-21
JPH10283203A (ja) 1998-10-23
SG63818A1 (en) 1999-03-30
JP3573943B2 (ja) 2004-10-06
CN1092360C (zh) 2002-10-09
CN1195135A (zh) 1998-10-07
GB2324392B (en) 2001-09-05
US5907702A (en) 1999-05-25
KR100274268B1 (ko) 2000-12-15
GB9803618D0 (en) 1998-04-15

Similar Documents

Publication Publication Date Title
TW362194B (en) Method and apparatus for decreasing thread switch latency in a multithread processor
WO2002067116A3 (en) Control of priority and instruction rates on a multithreaded processor
TW556093B (en) A data processing apparatus and method for saving return state
WO2000068781A3 (en) Switching method in a multi-threaded processor
DE59408653D1 (de) Multiprozessorsystem
EP1531390A3 (en) Method and apparatus for controlling the execution of multiple threads in a parallel processor
CA2103988A1 (en) Method and Apparatus for Processing Interruption
WO2004036354A3 (en) Method and apparatus for high speed cross-thread interrupts in a multithreaded processor
TW200502847A (en) Control device and method for reducing number of interrupts in a processor
EP2339454A3 (en) Method and apparatus for resolving instruction starvation in a multithreaded processor
AU2003298240A1 (en) Method and apparatus for switching between processes
EP1359501A3 (en) A processing device for executing virtual machine instructions
EP0137191A3 (en) Virtual machine system controller
WO2005026928A3 (en) Power saving operation of an apparatus with a cache memory
GB2344668A (en) Method for improved interrupt handling within a microprocessor
TW200622877A (en) Method and apparatus to provide a source operand for an instruction in a processor
US20120239915A1 (en) Interrupt Handling
WO2004061663A3 (en) System and method for providing hardware-assisted task scheduling
AU2335700A (en) Processor and method of executing instructions from several instruction sources
JPS578849A (en) Adjusting system for instruction execution speed
JPS55137360A (en) Controller for automobile
TW200703106A (en) Processor
WO1996008948A3 (en) Method and apparatus for fast microcontroller context switching
JPS5392636A (en) Interrupt control system of communication control processing unit
JPS57212551A (en) Operation controller

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees