TW366563B - Double damascene structure and the manufacturing method - Google Patents

Double damascene structure and the manufacturing method

Info

Publication number
TW366563B
TW366563B TW087101688A TW87101688A TW366563B TW 366563 B TW366563 B TW 366563B TW 087101688 A TW087101688 A TW 087101688A TW 87101688 A TW87101688 A TW 87101688A TW 366563 B TW366563 B TW 366563B
Authority
TW
Taiwan
Prior art keywords
damascene structure
double damascene
manufacturing
trench
etching
Prior art date
Application number
TW087101688A
Other languages
Chinese (zh)
Inventor
zhi-ren Li
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW087101688A priority Critical patent/TW366563B/en
Priority to JP10131822A priority patent/JP2000243829A/en
Priority to DE19826546A priority patent/DE19826546A1/en
Priority to FR9807632A priority patent/FR2774808A1/en
Priority to US09/113,879 priority patent/US5933761A/en
Application granted granted Critical
Publication of TW366563B publication Critical patent/TW366563B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H10P30/209—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

Double damascene structure and the manufacturing method by means of forming two insulation layers in the dielectric layer for non-equidistance etching and dielectric cavity and trench, plus stuffing of conductive layer for a double damascene structure. The present invention provides solutions to the known issue of hard determination of etching end and having the opening wall for trench mask of self alignment, without suffering poor alignment of the multiple masks in known practices.
TW087101688A 1998-02-09 1998-02-09 Double damascene structure and the manufacturing method TW366563B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW087101688A TW366563B (en) 1998-02-09 1998-02-09 Double damascene structure and the manufacturing method
JP10131822A JP2000243829A (en) 1998-02-09 1998-05-14 Dual damascene structure and method of manufacturing the same
DE19826546A DE19826546A1 (en) 1998-02-09 1998-06-15 Dual damascene structure with improved control of the etching stop
FR9807632A FR2774808A1 (en) 1998-02-09 1998-06-17 DOUBLE-DAMASCAN STRUCTURE AND MANUFACTURING METHOD THEREOF
US09/113,879 US5933761A (en) 1998-02-09 1998-07-10 Dual damascene structure and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087101688A TW366563B (en) 1998-02-09 1998-02-09 Double damascene structure and the manufacturing method

Publications (1)

Publication Number Publication Date
TW366563B true TW366563B (en) 1999-08-11

Family

ID=21629471

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087101688A TW366563B (en) 1998-02-09 1998-02-09 Double damascene structure and the manufacturing method

Country Status (4)

Country Link
JP (1) JP2000243829A (en)
DE (1) DE19826546A1 (en)
FR (1) FR2774808A1 (en)
TW (1) TW366563B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004055213B4 (en) * 2004-11-16 2009-04-09 Atmel Germany Gmbh Method for producing an integrated circuit on a semiconductor chip
US7514365B2 (en) 2005-11-16 2009-04-07 United Microelectronics Corp. Method of fabricating opening and plug
CN100527363C (en) * 2005-12-01 2009-08-12 联华电子股份有限公司 How to make the opening
JP2008210893A (en) 2007-02-23 2008-09-11 Fujitsu Ltd Semiconductor device and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01143231A (en) * 1987-11-27 1989-06-05 Nec Corp Manufacture of semiconductor device
JP2934353B2 (en) * 1992-06-24 1999-08-16 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US5741626A (en) * 1996-04-15 1998-04-21 Motorola, Inc. Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
US5741741A (en) * 1996-05-23 1998-04-21 Vanguard International Semiconductor Corporation Method for making planar metal interconnections and metal plugs on semiconductor substrates

Also Published As

Publication number Publication date
DE19826546A1 (en) 1999-08-19
JP2000243829A (en) 2000-09-08
FR2774808A1 (en) 1999-08-13

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