TW376351B - Polishing barrier structure of chemical mechanical polishing - Google Patents
Polishing barrier structure of chemical mechanical polishingInfo
- Publication number
- TW376351B TW376351B TW087103893A TW87103893A TW376351B TW 376351 B TW376351 B TW 376351B TW 087103893 A TW087103893 A TW 087103893A TW 87103893 A TW87103893 A TW 87103893A TW 376351 B TW376351 B TW 376351B
- Authority
- TW
- Taiwan
- Prior art keywords
- polishing
- chemical mechanical
- mechanical polishing
- barrier structure
- barrier layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
- H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW087103893A TW376351B (en) | 1998-03-17 | 1998-03-17 | Polishing barrier structure of chemical mechanical polishing |
| US09/073,157 US6160314A (en) | 1998-03-17 | 1998-05-05 | Polishing stop structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW087103893A TW376351B (en) | 1998-03-17 | 1998-03-17 | Polishing barrier structure of chemical mechanical polishing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW376351B true TW376351B (en) | 1999-12-11 |
Family
ID=21629696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW087103893A TW376351B (en) | 1998-03-17 | 1998-03-17 | Polishing barrier structure of chemical mechanical polishing |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6160314A (zh) |
| TW (1) | TW376351B (zh) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7045454B1 (en) * | 1999-05-11 | 2006-05-16 | Micron Technology, Inc. | Chemical mechanical planarization of conductive material |
| US6391768B1 (en) * | 2000-10-30 | 2002-05-21 | Lsi Logic Corporation | Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure |
| KR100386034B1 (ko) * | 2000-12-06 | 2003-06-02 | 에이에스엠 마이크로케미스트리 리미티드 | 확산 방지막의 결정립계를 금속산화물로 충진한 구리 배선구조의 반도체 소자 제조 방법 |
| JP2005538544A (ja) * | 2002-09-04 | 2005-12-15 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 埋め込み金属インターコネクタの製造方法 |
| US7906359B2 (en) * | 2002-12-03 | 2011-03-15 | Analog Devices, Inc. | Method of forming a surface micromachined MEMS device |
| US9209066B2 (en) * | 2013-03-01 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure of semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
| JP2934353B2 (ja) * | 1992-06-24 | 1999-08-16 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| JP3297220B2 (ja) * | 1993-10-29 | 2002-07-02 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
| US5534462A (en) * | 1995-02-24 | 1996-07-09 | Motorola, Inc. | Method for forming a plug and semiconductor device having the same |
| US5741626A (en) * | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
| US5891799A (en) * | 1997-08-18 | 1999-04-06 | Industrial Technology Research Institute | Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates |
-
1998
- 1998-03-17 TW TW087103893A patent/TW376351B/zh not_active IP Right Cessation
- 1998-05-05 US US09/073,157 patent/US6160314A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US6160314A (en) | 2000-12-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |