TW392223B - Bulk and strained silicon on insulator using local selective oxidation - Google Patents

Bulk and strained silicon on insulator using local selective oxidation Download PDF

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TW392223B
TW392223B TW087115828A TW87115828A TW392223B TW 392223 B TW392223 B TW 392223B TW 087115828 A TW087115828 A TW 087115828A TW 87115828 A TW87115828 A TW 87115828A TW 392223 B TW392223 B TW 392223B
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Jack Oon Chu
Khalid Ezzeldin Ismail
Kim-Yang Lee
John Albrecht Ott
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Description

五 '發明說明（l) 發明範圍 本發明係關於在相鄰於絕緣體或在絕緣體上形成大量或 應變Si/SiGe層狀區’且更特定言之，係關於用以在如互 補金屬-氧化物-半導體（CMOS)場效應電晶體（FEΤ’ s)、調 制-摻雜場效應電晶體（MODFET’ s)、動態隨機存取記憶體 (DRAM，s)、混合Μ AM和CMOS、靜態隨機存取記憶體 (SRAM’s)、BiCMOS與rf之元件應用之半導體區下形成絕緣 區之SiGe區域選擇性氧化。 發明背景 在矽半導體技術中，唯一達到絕緣基材之方法係依靠絕 緣體矽（SOI)、藍寶石矽（SOS)抑或回蝕及回接合以達成 SOI。在CMOS及高速FET’ S中使用絕緣基材之主要優點係 低寄生結電容及短通道效應’而因此增加元件之速度^ 性。所有以上方法之一主要問題為絕緣體覆蓋於整個晶 上，且因而整個元件區包括在下FET之歐姆接觸及通道s曰。 既然相對於通道，半導體基材係懸浮著，故而在整、曰° 上内埋氧化物造成熟知之’浮體，問題。此問題 ：： 控制及電路操作具有逆影響。以上解決方案之其餘 其，一般大量矽基材為昂貴許多。此外，沒有可得二 較高電子及電洞傳遞性質之應變的絕緣體矽之 ]、有 發明摘要 β 法。 根艨本發 〜仰心 從阳Μ在一早晶半導體厗 犯 内埋氧化物區之方法，其包括選擇一單晶矽基材、7 第一氧化速率之基材上表面上形成固定或分級的
五、發明說明（2) 一蠢晶層之步驟。此層可為應變的或鬆弛的S i Ge或晶格匹 配的S i G e C。然後在具有比第一氧化速率小之第二氧化速 率之第一層上形成含矽之第二磊晶層、在第二層上形成罩 幕、將罩幕圖案化以在罩幕中形成開口及透過罩幕開口氧 化第二層及第一層，因而形成具有在第二層下取代部份或 所有第一層之氧化區。 · 本發明更提供在第一層之殘留部份上第二層中形成含其 通道之FET’ s。 圖形簡述 本發明之這些及其餘特色、目的與優點當連同圖形閱 讀、研究下列本發明之詳細描述而會變得顯而易見，其 中： 圖1及2係說明實踐本發明步驟之層狀結構之橫斯面視 圖。 圖3係在說明本發明之一具體實施例之氧化步驟後、沿 圖2之線3-3之橫斷面視圖。 圖4係在不同溫度及環境下矽氧化速率對硼濃度之圖 形。 。圖5係圖3中所示具體實施例之製造樣品之TEM及 圖6係說明許多FET’ s之本發明第二具體施例之橫斷面視 圖。 圖7係說明移除在氧化步驟期間所形成氧化物之附加步.:, •驟之層狀結構之橫斷面視圖。 叫8係說明一氧化附加步驟之橫斷面視圖。
C:\Program Files\Patent\55033.ptd 第6頁 五 '發明說明（3) 、較佳具體實施例說明 f考圖1 ’咸顯示層狀結構12之橫斷面視圖以說明起始 理步,。首先，選擇可為Si、slGe等之單晶半導體基 材14。？者’在基材14之上表面15上形成固定或分級的 1 x ex〆SUe^Cha之蟲晶層η。對於用以成長含石夕膜 之UHV-CVD方法之描述係參考由B s梅爾森（B S.
Meyerson)於西元1 994年3月29日公佈、標題為,，用於晶矽 層之低溫、低壓化學氣相沉積之方法與裝置,，之美國專利 5:29 8,45 2，其併於本文供參考。磊晶層16可具有以含量χ 範圍從0· 15至0.25。磊晶層16在一特定溫度及環境下具有 第一熱氧化速率。該環境可包括氧、水蒸汽及/或ΗΠ。咸 ，要=定或分級的磊晶層1 6組成而既使層丨4及丨6具有不同 晶格常數也能磊晶地成長，又選擇固定或分級的磊晶層1 6 組成以具有第一熱氧化速率。咸調整磊晶層16厚度於臨界 厚度以下或以上以分別地提供一應變或鬆弛層。對於形成 SiGe鬆他層之描述係參考由FK.雷高俄斯（FK. [^⑽以） 及B.S.梅爾森（B,s. Meyerson)於西元1 9 9 7年8月19曰公 佈、標題為’’低缺陷密度/任一晶格常數之異質蟲晶層,，之 美國專利5,6 5 9, 1 8 7，其併於本文供參考。 S曰 接著，在磊晶層16之上表面17上形成si或Si NYGeY之磊晶 層20。磊晶層20可具有一固定或分級的以含量γ，而γ係小 於X及可為零。咸選擇層20組成以使層2〇具有比層16之氧 化速率小之第二氧化速率及具有需要的電氣性質。 接者’罩幕24係形成於層20之上表面21上。罩幕24可為
C:\Program Files\Patent\55033.ptd
五、發明說明（5) 元1996年）由瑞士（Switzerland)塞迪克出版社（Scitec Publications)發行之固態現象（s〇lid State Phen〇mena) 第47-48冊第17-32頁、由U.柯寧（U. K on ig)及J.赫森能 (J. Hersener)耆、標題為ns.iGe技術中低熱預算處理之需 求''之刊物。 圖3係透過圖2所示開口 26在罩幕29之邊緣四周之磊晶層 16及20氧化之後、沿圖2之線3-3之橫斷面視圖。如圖3所 示’蟲晶層20 ’除了在罩幕形狀29之下，係完全為氧化物 區33及34消耗。磊晶層丨6在開口 26下係幾乎或完全消耗及 在層20’下之層16橫側地延伸。所形成氧化物係Sijes〇2， 而r與s具有一與為厚度函數之層16中Ge含量有關及與氧化 條件有關、範圍從大於〇至2之數值。 氧化物33及34係在層2〇，下之層丨6延伸，而層ι6，具有比 層20之氧化速'率為大之氧化速率，若Ge或硼任何一者存 在的話，則氧化速率受Si GetGe分級及受硼摻雜分佈曲線 控制。硼係可摻雜最多至原子/立方公分以提升^以之 氧化。鍺量係提供氧化速率上相當的增加。硼量係提供如 圖4所示之氧化速率上相當的增加。在圖4中，縱座標代表 氧化速率（埃/分）及橫座標代表硼濃度（公分-3)。曲線41表 不在1大_虱壓於氧中7〇〇。(：下矽氧化速率為硼濃,度函數。曲 ，42表不在也習知為高壓氧化（ΗΙρ〇χ)之丨〇大氣壓於氧及 洛汽中6 0 0 C下矽氧化速率為硼濃度函數。曲線43表示在 1 0大氣壓於氧及蒸汽中70〇它下矽氧化速率為硼濃度函 數。HIP0X可發生於壓力範圍從1至2〇大氣壓，而典型地在
C:\Program Files\Patent\55033. ptd 第9頁 五 '發明說明（6) =境之12大氣壓。Ge及B兩者存在係提供氧化速率上 本積的增加。因此層16 *SiGe内以組成之三次元分佈曲 及層14、16與20中蝴濃度之三次元分佈曲線能分別提供一 預定/刀佈曲線為氧化物33及34之外圍表面或 μ 時間函數。箭頭3⑽表示在罩幕形狀29：^;=; 3:及=別長度11及12。層2〇’相對於罩幕形狀29也受氧 化，但由於較低的氧化速率而在罩幕 又礼 隨著Si與SiGe層之氧化，所得氧化材 ^較'。 增加（非比例）。 < 厚度如圖3所不 藉著繼續在一個或更多溫度下為時間函數之 可決定或控制對層16及20生長平面中固〜 乳化乂驟， 度1及12。由箭頭39所示之間隙d同樣可K 2相等之長 d容許與層16’及基材14歐姆接觸以控制^二工制。間隙 之場效應電晶體實體之電壓，而因此二 中所形成 體效應。典型地，間隙d應較FET之閘 *累積電荷之浮 隙d為零之例子，氧化物33及34可結人^長度為短。對於間 2 0 ’應與基材14電隔離。 ° 〇在—起，此例中層 圖5為圖3具體實施例之製造檨$夕珠 (ΤΕΜ)。圖5表示圖3視圖之編應透在射電:顯微鏡 約0 _ 1 7微米。間隙d為約〇 ! 5糌半。罟甘圖5中，h及h為 U微米。在圖5中，相同參5^號有寬度 入相對於圖3所描述之相同材料。 ；圖3中裝置及置 圖δ為FET ε 52及53之橫斷面視圖。 編號係用於圖3所示之相同結構元件。圖6中，相同參考 將可為氮化矽之罩
C:\Program Files\Patent\55033. ptd
五、發明說明（7) 幕2 9 (未顯示出）移除。對於電晶體5 2及5 3，如二氧化石夕之 閘極介電質56係可分別形成於層20,上。多晶矽層係可形 成於閘極介電質56上且將其圖案化以分別形成電晶體52>及 53用之閘極電極57。使用閘極電極57，源極區6〇與>及極區 61可藉離子植入形成，且歐姆接觸植入可形成而延伸至氧 化=32、33及34之上表面。在形成自我排列歐姆接觸植入 之诎，閘極侧壁間隔物係可形成於閘極電極5 7之側壁（未 顯示出）。隨著歐姆接觸延伸至氧化物32、33及34表面， 因為除了無p-n結外，與Si相比低三倍的氧化物介電常 數、’，故而降低層1 6 ’之寄生結電容。對於一通道寬度為工3 ，米源極60與汲極61之寄生結電容可比〇. 〇2毫微&微法拉 第/平方微米小。藉在源極6 0與汲極6丨下擺入氧化物3 2、 33及34，當增加汲極偏壓時，短通道效應因防止空乏區延 伸入通道而降低短通道效應。FET 52可為卜型及”？ Μ可 為P-型以形成CMOS電路。每一個FET源極與汲極可在離子 植入期間藉將保留作為相對摻雜劑之其餘fet去罩幕而摻 雜適當的摻雜劑。在本技藝中熟知一CM〇s電路為一fet之 =經過引線66與其餘FET之源極麵合以形成一輸出。問 =電極係經過引線67•合在一起以形成一輪入。將接地及 電壓㈣引'_及69與個別m’s之剩餘源極與 圖7係與圖3所示之類似結 之層狀結構7 0之橫斷面視圖 HF蝕刻之蝕刻方式移除。 構但具有將氧化物3 3及3 4移除 。氧化物33及34可藉如用缓衝
孔化物33及34之移除，曝露的層14、16，及2〇，係可 :露氧化環境以再繼續層16’之氧化及層14及2〇,氧化 輕程度’其與氧化速率有關。氧化物33及34可作為 “，或減緩層16’之氧化。因此氧化物33及34之移除加速 禮u之氧化。 圖8係在基材丨4及層1 6，與2 〇 ’如氧化物區7 7及7 8所示之 ^ 步氧i化之後之層狀結構7 4之橫斷面視圖。 。氧化物移除及在一氧化環境中層狀結構之氧化之步驟係 /重覆數-人。在已形成所需結構之後，如氧化石夕之介電質 係可用於填充因氧化物移除所形成之空洞。為了更進一步 處理以形成有用的半導體元件，咸可使用化學機械方法形 成一平坦上表面。 在圖7及8 ’相同參考編號係用於對應於圖3之裝置之結 構〇 當頃描述及說明一種用於在與基材歐姆接觸、為在應變 下或秦·他之單晶半導體層區及一具有如CM〇s、MODFET，s、 DRAM’ s、SRAM’ s、rf ' BiCMOS 及混合DRAM 與CMOS 之元件和 電路應用之次微米通道長度之FET結構下形成内埋氧化物 區時，應完全受限於本文所附之申請專利範圍而不偏離本 發明廣泛領域之可能的修改與變更對於熟諳本技藝者係將 顯而易見。 "

Claims (1)

  1. 六、申請專利範圍 1. 一種用於在一單晶半導體層區下形成内埋氧化物區之 方法包括： 選擇一單晶；ε夕基材； 在該基材之上表面上形成一選自包括SUe,及 (SiuyGe^Ch之第一磊晶層，該第一層具有第一氧化速 率； 在該第一層上形成一含矽之第二磊晶層，該第二層具 有比該第一氧化速率為小之第二氧化速率； 喪該第二層上形成一罩幕；s 將' 該罩幕圖案化以在該罩幕中形成開口；以及 透過該罩幕開口氧化該第二層及該第一層，因而一氧 化物區形成於含有部份該氧化物區在該第二層下取代部份 該第一層之該第一及第二層之步驟。 2. 如申請專利範圍第1項之方法，其中該氧化步驟係持 '續一段時間以形成含在該第二層下延伸一預定距離之該氧 化物區之該部份之該氧化物區。 3. 如申請專利範圍第2項之方法，更包括將兩個罩幕開 口位置分離以在該第二層下提供兩個以一預定距離間隔開 之該氧化物區之個別部份之步驟。 4. 如申請專利範圍第1項之方法，其中該.開口之一係沿 —路徑延伸以形成一罩幕形狀。 5. 如申請專利範圍第4項之方法〃其中該罩-幕形狀係選 自包括長方形、正方形及圓形。 6. 如申請專利範圍第1項之方法，其中該開口係分別相.
    C:\Program Files\Patent\55033.ptd 第13頁 六、申請專利範圍 對應於有效MOS元件之尺寸形成許多該罩幕外之長方形。 7. 如申請專利範圍第6項之方法，其中該許多該罩幕外 之長方形係1微米X1微采或更小。 8. 如申請專利範圍第6項之方法，其中該氧化步驟係持 續一段時間以在該長方形中央.留下一該第一蟲晶層未受氧 化之有限區。 9. 如申請專利範圍第8項之方法，更包括在該第二層形 成源極與汲極區以在該第一磊晶層之該有限區上兩極之間 定義出一通道以避免FET之浮體效應之步驟。 10. 如申請專利範圍第9項之方法，更包括在該通道上形 成一閘極介電質及一閘極電極以形成一 F E T之步驟。 11. 如申請專利範圍第8項之方法，更包括在該氧化物區 上該源極與汲極區中形成歐姆接觸離子植入、因而降低寄 生結電容之步驟。 1 2.如申請專利範圍第1項之方法，其中該氧化步驟係包 括在範圍從7 0 0 °C至8 0 0 °C之一溫度下溼熱氧化。 1 3.如申請專利範圍第1項之方法，其中該氧化步驟包括 在範圍從6 5 0 °C至8 0 0 °C之一溫度下高壓氧化（HIPOX)。 1 4.却申請專利範圍第1項之方法，更包括移—除由該氧化 步驟形成之部份該氧化物之步驟。 15.如申請專利範圍第14項之方法，更包括實際移除由 該氧化步驟形成之所有該氧化物之步驟。 1 6.如申請專利範圍第1 4項之方法，更包括在該移除步 驟之後繼續該氧化步驟之步驟。、
    C:\Program Files\Patent\55033.ptd 第14頁 六、申請專利範圍 1 7,如申請專利範圍第1 6項之方法，更包括重覆該移除 及氧化步驟數次之步驟。 18.如申請專利範圍第1項之方法，其中形成一罩幕之該 步驟係包括形成一氮化矽層之步驟。 1 9.如申請專利範圍第1項之方法，其中形成該第一磊晶 層之該步驟係包括形成一分級組成層。 2 0.如申請專利範圍第19項之方法，其中形成該第一磊 晶層之該步驟係包括形成一具有含比該第二層之晶格係數 • .... ........... ' . 為大之晶格係數之上表面之層以在該第二層提供j宄拉應 變。 21. 如申請專利範圍第1項之方法，其中形成該第一磊晶 層之該步驟係包括成長該第一磊晶層直至其鬆弛至一比將 形成之該弟二遙晶層之晶格常數為大之晶格常數、因而當 形成之該第二磊晶層會在抗拉.應變之下以具有高電子及電 洞移動率之步驟。 22. 如申請專利範圍第1項之方法，其中該氧化步驟係持 續一段時間以向下至.該基材中而形成該氧化物區。 23. 如申請專利範圍第1項之方法，更包括用硼摻雜該第 一層區以提升氧化速率之步驟。 2 4.如申請專利範圍第1項之方法，其中該第一層在Ge組 成上係分級的以提升氧化速率。 2·5, —種用以形成一電子元件之結構，其中包括： —早晶$夕基材， 一在該基材之上表面上、選自包括Si^Ge、及、
    C:\Program Files\Patent\55033.ptd 第15頁 六、 申請專利範圍 (S i(i- x)Gex)aCi__a之弟一蠢晶層， 一在該第一層上含石夕之第二單晶 層；以及 間隔開之第一層及第；氧化物區 ，該等第一 及第」 二氧 化 物 區每一個延伸至在該第二層下之 該第一區中 0 26. 如申請專利範圍第25項之結構， 其中誇第一 及第 二 氧 化 物區係形成於該第一磊晶層及該 第二單晶層 中。 27. 如申請專利範圍第25項之結構， 其中該第一 及第 二 氧 化 物區係在該第一層中間隔開範圍 從0. 01 至0. 5 微米 0 28. 如申請專利範圍第25項之結構， 其中該第一 及第 — 氧 化 物區係包圍部份該第一層。 29. 如申請專利範圍第28.項之結構， 其中該第一 層之 該 包 圍 部份係在其上表面上形成一選自 包括長方形 、正方形 及 圓 形之形狀。 30. 如申請專利範圍第2 9項之結構， 更包1括許多 該第 -- 層 之 包圍部份，每一個該第.一層之包 圍部份係小於1微 米 xl 微 米。 31. 如申請專利範圍第2 8項之結構， 其电_在該第 一及 第 二 氧 化物區之間之該第二層係在該第 一層之讓包 圍部份 下 並與其接觸。 32. 如申請專利範圍第25項之結構 其中該第一 ^ 曰 .日日 層 係 包 括一 G e分級的組成層。 33. 如申請專利範圍第25項之結構 其中該第一 石 曰 曰日 層 係 包 括硼摻雜。 34. 如申請專利範圍第25項之鼓..構， 其中該第二 單晶 層
    C:\Program Files\Patent\55033.ptd 第16頁 、申請專利範圍 係由於該第一層上表面之s 35. 如申請專利範念而在應變之下 氧化物區係經該第-層延伸至該基材中，36. 如申凊專利範圍第25項之結構，更包括在該第/廣 内間隔開之源極與及極區向下延伸至該第一及第二氧化物 區之Ί表由面主’ /分別在該第一層中定、義出一通道。 37·Λ Λ /範圍第36項之結構，更九括在該通道上 介電質上之-閑極電極以形Η 38. 如申請專利範圍第37嘴.任 m二4 μ广構，更包括與延伸至該 區之該-源極與汲極、歐姆揍觸。 39. 如"月專利範圍第37項之 該通 40:如申請專利範圍第37項之結構，其 一Ge分級組成以晶格應變至該第一層中之該通、首―。層具有 41.如申請專利範圍第3?項之結 ^ k。 弛的。 - 〜中該弟—層係鬆 4 2Γ如申请專利範圍第3 7項之結構 __該第一層相稱的。 43. 如申清專利範圍第.37項之結構 及ρ型之場效應電晶體。 44. 如申請專利範圍第43項之結構，更包括 好 形成互補金屬氧化物半導體（CMOS)電路。匕 ~接線以 其中該第 及 第 層係與 更包括許多分別為η
    C:\ProgramFiles\Patent\55033.ptd 第 17 頁
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