經濟部智慧財產局員工消費合作社印製 4486twf.doc/002 pj __406355 B7___ 五、發明說明（I ) 本發明是有關於一種半導體元件結構及其製造方法， 且特別是有關於一種結合淺溝渠隔離（Shallow TrenchPrinted by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4486twf.doc / 002 pj __406355 B7___ V. Description of the Invention (I) The present invention relates to a semiconductor element structure and a method for manufacturing the same, and in particular, to a method for combining shallow trench isolation ( Shallow Trench
Isolation ’ STI)與絕緣層上有砂(Silicon On insuiator , SOI) 之結構及其製造方法，並可降低在淺溝渠隔離結構上之應 力。 在積體電路蓬勃發展的今日，元件縮小化與積集化是 必然之趨勢，也是各界積極發展的重要課題。當元件尺寸 逐漸縮小’積集度（Integration)逐漸提高，元件間的隔離結 構也必須縮小，因此元件隔離技術困難度也逐漸增高。 習知之兀件隔離有利用區域氣化法（Local Oxidation， LOCOS)來形成的場氧化層(Field Oxide)，然而由於場氧化 層受限於其外型之鳥嘴(Bird’s Beak)特性，要縮小其尺寸 實有困難。有鑒於此，已有其他元件隔離方法持續被發展 出來，其中以淺溝渠隔離（Shallow Trench Isolation，STI) 最被看好，目前已被廣泛應用在深次微米（Sub-half Micron) 的積體電路製程中。 淺溝渠隔離（STI)是一種在基底上形成圖案化之硬罩幕 層，利用非等向性蝕刻方法在半導體基底中形成溝渠，然 後在溝渠中塡入氧化物，以形成元件之隔離區，之後再去 除硬罩幕層的技術。由於STI所形成之場隔離區具有可調 整大小（Scaleable)的優點，因此對於深次微米製程中的互 補式金氧半導體（CMOS)而言，是一種較爲理想與的元件 隔離技術。 另外，在元件與基底之隔離技術中，絕緣層上有矽 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --,----Γ----— II - I----I I 訂----Γ l· I H I · (請先閱讀背面之注意事ί填寫本頁) - 4486twf.doc/002 A7 4486twf.doc/002 A7 經濟部智慧財產局員工消費合作社印製 ▲n b7_ 五、發明說明（之） (Silicon On Insulator，SOI)是一種在砂基底中埋入一層氧 化矽絕緣層，以在CMOS元件底下形成隔離區的技術。其 具有可降低接面漏電流（Junction leakage)與電容 (Capacitance)等等之優點。並且由於CMOS電晶體不與矽 基底相連，因此由"源極與基底"和"井區與基底”連接所造 成的CMOS電晶體閉鎖(Latch-up)問題，將因爲中間這層 絕緣層隔離而消失。 目前SOI的製造方式約有三種： 1. 在一矽基底中，利用離子植入法植入氧於基底中， 深度約2微米（micron)，然後利用熱製程使植入之氧與矽 基底反應形成一氧化矽層於基底中。 2. 在一矽基底上先形成一氧化矽層，再與另一矽基底 接合而形成一絕緣層上有矽之基底。 3. 在一砂基底上先形成一氧化砂層，在利用幕晶的方 法在氧化较層上形成砂層。Isolation ’STI) and insulation on sand (Silicon On insuiator) structure and its manufacturing method, and can reduce the stress on the shallow trench isolation structure. In today's booming development of integrated circuits, component downsizing and integration are an inevitable trend and an important issue for the active development of all sectors. When the component size is gradually reduced, the integration degree is gradually increased, and the isolation structure between components must be reduced, so the difficulty of component isolation technology is gradually increasing. The conventional element isolation has a field oxide layer (LOX) formed by the Local Oxidation (LOCOS) method. However, because the field oxide layer is limited by its bird's beak characteristics, it must be reduced. Its size is really difficult. In view of this, other component isolation methods have been continuously developed. Among them, Shallow Trench Isolation (STI) is the most promising. It has been widely used in sub-half micron integrated circuits. In the process. Shallow trench isolation (STI) is a patterned hard mask layer formed on a substrate. An anisotropic etching method is used to form a trench in a semiconductor substrate, and then an oxide is implanted in the trench to form an isolation region of the device. Then remove the hard cover curtain technology. Because the field isolation region formed by STI has the advantage of being scalable, it is an ideal device isolation technology for complementary metal-oxide-semiconductor (CMOS) in deep sub-micron processes. In addition, in the component and substrate isolation technology, there is a silicon paper on the insulating layer. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)-, ---- Γ ------ II- I ---- II Order ---- Γ l · IHI · (Please read the note on the back first to fill in this page)-4486twf.doc / 002 A7 4486twf.doc / 002 A7 Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed ▲ n b7_ 5. Description of the Invention (Silicon On Insulator, SOI) is a technology of burying a silicon oxide insulating layer in a sand substrate to form an isolation region under a CMOS device. It has the advantages of reducing junction leakage and capacitance. And because the CMOS transistor is not connected to the silicon substrate, the CMOS transistor latch-up problem caused by the "source and substrate" and "well area and substrate" connection will be isolated by the middle layer. The layer is isolated and disappears. At present, there are about three manufacturing methods of SOI: 1. In a silicon substrate, oxygen is implanted into the substrate by ion implantation to a depth of about 2 microns (micron), and then it is implanted by a thermal process. Oxygen reacts with the silicon substrate to form a silicon oxide layer in the substrate. 2. A silicon oxide layer is formed on a silicon substrate and then bonded to another silicon substrate to form a substrate with silicon on an insulating layer. An oxide sand layer is formed on the sand substrate first, and a sand layer is formed on the oxide layer by using a curtain crystal method.
儘管SOI的結構具有諸多優點，但由於目前形成SOI 的製作成本昂貴，且均在整片基底上製作形成，其製程與 CMOS製程難以結合。而且SOI製作技術較爲複雜，並不 適合於量產。 由上可知，若能提供區域性(Local)的SOI製作技術， 再結合STI結構’將此二種絕緣方法相結合，共同運用於 半導體元件之製造，則可兼具兩者之優點，使元件之設計 更加彈性與靈活。 例如，可應用在一種動態隨機存取記憶體(DRAM)中所 4 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） — — — I — — 1 · I I I I I I e * J (請先閱讀背面之注意事Ϊ填寫本頁) - 經濟部智慧財產局員工消費合作社印製 4486twf.d〇c/〇〇2 A7 _______ 406355 B7_—___ 五、發明說明（>) 使用的開關電晶體(Pass transistor)之結構。其中，開關電 晶體建構於SOI上較佳，可減少漏電流的問題。 基於上述之觀點，本發明提供一種結合淺溝渠隔離與 絕緣層上有矽之結構與其製造方法，不僅可具有兩者之優 點’並且不需使用硬罩幕層，可解決以傳統方法製造淺溝 渠隔離所產生的應力問題。 本發明提供一種結合淺溝渠隔離與絕緣層上有矽之結 構與其製造方法。包括提供一基底，基底至少包括一淺溝 渠隔離區域與一絕緣層上有矽區域。然後在絕緣層上有矽 區域之基底中形成第一開口，用以製作絕緣層上有矽結 構。接著在基底與第一開口之表面依序形成共形之第一襯 氧化層與第一氧化矽層。然後在氧化矽層上形成一非晶矽 層’且塡滿第一開口。之後以化學機械硏磨法進行平坦化， 去除第一氧化矽層上的非晶矽層，以留下部分之非晶矽層 塡滿第一開口。接著利用微影蝕刻的方法，在淺溝渠隔離 區域之基底中’形成第二開口，用以製作淺溝渠隔離結構。 然後在第二開口之內表面形成一共形之第二襯氧化層。接 著在基底上形成一第二氧化矽層，且塡滿第二開口。然後 執行一高溫緻密化製程，使第二氧化矽層緻密化，同時使 非晶矽層轉變成一單晶矽層。再以化學機械硏磨法進行平 坦化，去除單晶砂層上之第二氧化砂層，直到暴露出單晶 矽層時終止。接著在單晶矽層表面形成犧牲氧化層，以去 除單晶矽層表面的雜質。之後視製程需要（如形成井區）決 定是否進行摻雜。然後剝除基底與單晶矽層表面暴露之氧 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --^-------—I— -------— —訂·！丨 l·—— — * * < (請先閱讀背面之注意事t填寫本頁) - 4486twt'.doc/002 A7 4486twt'.doc/002 A7 經濟部智慧財產局員工消費合作社印製 40·5 B7 五、發明說明（/) 化矽層’以暴露出基底與單晶矽層。最後在基底與單晶矽 層上形成閘極氧化層與閘極，並接著進行元件的製作。 由於以光阻層作爲定義第二開口時的罩幕層，且使用 單晶矽層作爲平坦化製程的終止層，因此可避免傳統使用 硬罩幕層形成淺溝渠隔離結構所產生的應力問題。另外， 在形成第一開口時，可使用虛擬圖案(Dummy pattern)，增 加單晶矽層的面積，藉以在平坦化第二氧化矽層時，增進 終點偵測的靈敏度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式’作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1F圖是繪示依照本發明一較佳實施例之 製程剖面示意圖。 圖式之標記說明： 100 :基底 102 :淺溝渠隔離區域 104 :絕緣層上有矽區域 1 10 :第一開口 112 :第一襯氧化層 114 :第一氧化砂層 I 16、116a :非晶砂層 116b :單晶矽層 II 8 :第二開口 6 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — —Γ---------! Μ, -------訂----— — — ——線-------——IJ---- - w i (請先鬩讀背面之注意事Ϊ填寫本頁) - 經濟部智慧財產局員工消費合作社印製 4486twt.d〇c/002 406355 at ___B7______ 五、發明說明（f ) 120 :第二襯氧化層 122 :氧化矽層 124 :第二氧化矽層 126 :犧牲氧化層 128 :閘極氧化層 130 :閘極層 較佳實施例 請參照第1A圖，提供一矽基底100 ’矽基底100至少 包括一淺溝渠隔離（STI)區域102與一絕緣層上有矽（SOI) 區域104。然後在絕緣層上有矽（SOI)區域之矽基底1〇〇 中’預定製作絕緣層上有矽之位置’形成一第一開口 Π0， 其形成的方法比如以傳統的微影和蝕刻方式進行。接著在 基底100與開口 110之表面依序形成共形(Conformal)之第 一襯氧化層112與第一氧化矽層114，其形成之方法比如 襯氧化層112是以熱氧化法形成，而氧化矽層1 14比如是 以化學氣相沉積法（CVD)沉積而成，厚度約1〇〇〇埃左右。 接著在氧化砂層114上形成一非摻雜(undoped)之非晶砍層 (amorphous silicon)116且塡滿開口 11〇 ,其形成的方法比 如是以CVD所沉積而成。 請參照第1B圖，進行一平坦化製程，比如使用化學 機械硏磨法（CMP)，以去除氧化矽層ι14上的部分非晶矽 層Π6’留下部分之非晶砂層116a塡滿開口丨1〇。接著在 淺溝渠隔離（STI)區域之基底100中，預定製作淺溝渠隔離 的位置’形成一第二開口 118。其形成的方法比如以傳統 7 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） L·1— 丨 ΓΙ — 丨丨丨 1 _ I I I 丨 I _ 訂 i I ί I I · (請先閲讀背面之注意事^1<填寫本頁) 4486twf.doc/002 A7 __B7_____ 五、發明說明（6) (請先閱讀背面之注意事ί填寫本頁) 的微影和餓刻方式進行，在基底100上形成一圖案化的光 阻層代替傳統製程所使用之墊氧化層（Pad oxide)與氮化矽 硬罩幕層(Hard mask)，然後以光阻層爲罩幕，進行非等向 性蝕刻以形成所需要的開口 118，之後再去除光阻層。 請爹照第1C圖，在開口 118之內表面形成一第二襯 氧化層12〇，形成襯氧化層120之方法比如以熱氧化法進 行。由於熱氧化之關係，會在非晶矽層116a之表面形成 一層氧化矽層122。接著在基底100上形成一第二氧化矽 層124且塡滿開口 118，形成氧化矽層124的方法比如是 以CVD沉積而成。接著對氧化矽層124進行一緻密化 (DensiHcation)步驟，比如在溫度約攝氏1〇〇〇度左右進行 回火，以使氧化砂層124變得緻密。在此同時，非晶砂層 116a將因爲高溫而再結晶，轉變成一單晶矽(single crystal silicon)層 1 16b。 經濟部智慧財產局員工消費合作社印製 請參照第ID圖，進行一平坦化製程，去除單晶矽層116b 上的氧化矽層124與122，比如使用CMP進行硏磨，直到 暴露出非晶矽層116b時停止，在此單晶矽層116b即作爲 CMP之終止層。此外，可在形成開口 110時，使用虛擬圖 案（dummy pattern)，也就是在其他區域形成多個開口，並 在其中形成單晶矽層，以增加單晶矽層H6b的形成位置’ 增進CMP對硏磨終點的感測能力，可藉此增進CMP的均 勻度。接著在單晶矽層116b表面形成一犧牲氧化層126， 藉以去除雜質，確保SOI表面結構的品質。若需要對基底 1〇〇進行摻雜時，比如形成井區（Well)，可在此時進行摻 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486twf.d〇e/〇〇2 486twf.d〇e/〇〇2 經濟部智慧財產局員工消費合作社印製 406355 五、發明說明（1 ) 雜’比如是以離子植入法進行。由於本發明，在CMP製 程中係以單晶矽層作爲硏磨終止層’且在製作開口 n8時， 係以傳統微影蝕刻方法中的光阻層作爲蝕刻罩幕，並不需 要使用傳統的氮化矽硬罩幕層，因此在製作淺溝渠隔離的 過程中，不會發生傳統使用氮化矽硬罩幕層所產生的應力 (Stress)問題。 請參照第1E圖，去除基底100與單晶矽層ii6b表面 暴露之氧化矽層，比如以氫氟酸（HF)溶液作濕式浸漬（Wet dip)去除氧化矽層Π4、襯氧化層112與犧牲氧化層126， 以及部分氧化矽層124。但濕式浸漬僅去除在基底100與 單晶矽層116b表面暴露之氧化矽層，在單晶矽層116b底 下與週緣之氧化矽層114與襯氧化層112則未被去除。由 單晶矽層116b以及其下的氧化矽層114和襯氧化層112 組成絕緣層上有矽（SOI)之結構。在形成SOI之製造過程 中，可藉由控制第一開口 110之深度，以及第一襯氧化層 112、第一氧化矽層114、第二襯氧化層120、氧化矽層122 與犧牲氧化層126之厚度，來控制單晶矽層U6b形成的 厚度，藉以使CMOS元件具有較佳之性能與較低之漏電 流。比如形成單晶矽層116b的厚度約500埃左右。 請參照第1F圖，進行半導體元件之製作。比如以熱氧 化法在基底100與單晶矽層116b上形成閘極氧化層128 ° 接著比如在閘極氧化層128上以CVD沉積摻雜的多晶矽 (doped polysilicon)以形成閘極層130。然後再進行後_兀 件製作的製程，在此不再贅述。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -I J— I I 1 I---I--裝 -------訂·--I- I I---線 (請先閱讀背面之注意事t填寫本頁) - 4486twf.doc/002 406355 A7 B7 五、發明說明（名） 由上述本發明較佳實施例可知，應用本發明可同時提 供淺溝渠隔離與絕緣層上有矽二種結構，使得在積體電路 設計時可以有更大的彈性，並且在製作過程中以光阻層作 爲罩幕層，且以單晶矽層作爲平坦化時的終止層，可避免 傳統使用硬罩幕層製作淺溝渠隔離時所造成的應力問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 -----I---------------訂-------r--- • * (請先閱讀背面之注意事ί填寫本頁) - 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Although the structure of SOI has many advantages, it is difficult to combine the process with CMOS process because the current SOI is expensive to manufacture and is formed on the entire substrate. Moreover, the SOI production technology is relatively complicated and is not suitable for mass production. It can be seen from the above that if local SOI manufacturing technology can be provided, and combined with the STI structure, these two insulation methods can be used together in the manufacture of semiconductor components, which can combine the advantages of both and make the components The design is more flexible and flexible. For example, it can be used in a dynamic random access memory (DRAM). The paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) — — — I — — 1 · IIIIII e * J (Please read the notes on the back first and fill in this page)-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4486twf.d〇c / 〇〇2 A7 _______ 406355 B7 _—___ V. Description of the switch (>) The structure of a transistor. Among them, the switching transistor is better constructed on the SOI, which can reduce the problem of leakage current. Based on the above point of view, the present invention provides a structure and a manufacturing method that combine shallow trench isolation with silicon on the insulating layer, which not only has the advantages of both, and also does not require the use of a hard cover curtain layer, which can solve the traditional method of manufacturing shallow trenches. Isolate stress problems. The invention provides a structure combining a shallow trench isolation with silicon on an insulating layer and a manufacturing method thereof. The method includes providing a substrate. The substrate includes at least a shallow trench isolation region and a silicon region on an insulating layer. Then, a first opening is formed in the substrate having a silicon region on the insulating layer to make a silicon structure on the insulating layer. Then, a conformal first liner oxide layer and a first silicon oxide layer are sequentially formed on the surface of the substrate and the first opening. An amorphous silicon layer 'is then formed on the silicon oxide layer and fills the first opening. After that, planarization is performed by a chemical mechanical honing method, and the amorphous silicon layer on the first silicon oxide layer is removed to leave a part of the amorphous silicon layer filling the first opening. Then, a lithographic etching method is used to form a second opening in the substrate of the shallow trench isolation region to form a shallow trench isolation structure. A conformal second lining oxide layer is then formed on the inner surface of the second opening. Then, a second silicon oxide layer is formed on the substrate, and the second opening is filled. Then, a high-temperature densification process is performed to densify the second silicon oxide layer, and at the same time, change the amorphous silicon layer into a single-crystal silicon layer. The chemical mechanical honing method was used for planarization to remove the second oxide sand layer on the single crystal sand layer until the single crystal silicon layer was exposed. A sacrificial oxide layer is then formed on the surface of the single crystal silicon layer to remove impurities on the surface of the single crystal silicon layer. Then, depending on the process needs (such as forming a well area), whether to doping is decided. Then strip the exposed oxygen from the surface of the substrate and the monocrystalline silicon layer. 5 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)-^ --------- I-- ---- ----- —Order ·!丨 l · —— — * * < (Please read the note on the back to fill out this page first)-4486twt'.doc / 002 A7 4486twt'.doc / 002 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 40 · 5 B7 V. Description of the Invention (/) Silicon layer is exposed to expose the substrate and single crystal silicon layer. Finally, a gate oxide layer and a gate are formed on the substrate and the single crystal silicon layer, and then the device is manufactured. Because the photoresist layer is used as the mask layer when defining the second opening, and the monocrystalline silicon layer is used as the termination layer of the planarization process, the stress problem caused by the traditional use of a hard mask layer to form a shallow trench isolation structure can be avoided. In addition, when forming the first opening, a dummy pattern can be used to increase the area of the single crystal silicon layer, thereby improving the sensitivity of endpoint detection when planarizing the second silicon oxide layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings' as follows: Brief description of the drawings: Figure 1A FIG. 1 to FIG. 1F are schematic cross-sectional views illustrating a manufacturing process according to a preferred embodiment of the present invention. Explanation of the marks of the drawings: 100: substrate 102: shallow trench isolation area 104: silicon area on the insulating layer 1 10: first opening 112: first liner oxide layer 114: first oxide sand layer I 16, 116a: amorphous sand layer 116b: Monocrystalline silicon layer II 8: Second opening 6 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) — —Γ ---------! Μ,- ----- Order ----—— — — ——Line -------—— IJ -----wi (Please read the notes on the back first and fill in this page)-Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau 4486twt.doc / 002 406355 at ___B7______ V. Description of the Invention (f) 120: Second liner oxide layer 122: Silicon oxide layer 124: Second silicon oxide layer 126: Sacrificial oxide layer 128: Gate oxide layer 130: For a preferred embodiment of the gate layer, please refer to FIG. 1A. A silicon substrate 100 is provided. The silicon substrate 100 includes at least a shallow trench isolation (STI) region 102 and a silicon-on-insulator (SOI) region. 104. Then, a first opening Π0 is formed in a silicon substrate 100 having a silicon (SOI) region on the insulating layer 'scheduled to produce silicon on the insulating layer', and the formation method is performed by, for example, traditional lithography and etching methods. . Then, a conformal first lining oxide layer 112 and a first silicon oxide layer 114 are sequentially formed on the surfaces of the substrate 100 and the opening 110. A method for forming the first lining oxide layer 112 and the first silicon oxide layer 114 is, for example, a thermal oxidation method, and oxidizing The silicon layer 114 is deposited by, for example, chemical vapor deposition (CVD), and has a thickness of about 1,000 angstroms. Next, an undoped amorphous silicon layer 116 is formed on the oxidized sand layer 114 and the opening 11 is filled. The method of forming the amorphous silicon layer 116 is, for example, CVD. Referring to FIG. 1B, a planarization process is performed, for example, a chemical mechanical honing method (CMP) is used to remove a part of the amorphous silicon layer Π6 ′ on the silicon oxide layer ι14, and a portion of the amorphous sand layer 116a left full of the opening. 1〇. Next, in the substrate 100 in the shallow trench isolation (STI) region, a second opening 118 is formed at a position where the shallow trench isolation is to be formed. The method of forming it is, for example, to apply the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm) with the traditional 7 paper sizes. L · 1— 丨 ΓΙ — 丨 丨 丨 1 _ III 丨 I _ order i I ί II · (Please read the notes on the back ^ 1 < Fill this page first) 4486twf.doc / 002 A7 __B7_____ V. Description of the invention (6) (Please read the notes on the back first and fill in this page) in lithography and hungry A patterned photoresist layer is formed on the substrate 100 instead of the pad oxide layer and the silicon nitride hard mask layer used in the traditional process, and the photoresist layer is used as a mask to perform non- Isotropic etching is performed to form the required openings 118, and then the photoresist layer is removed. Please refer to FIG. 1C to form a second liner oxide layer 120 on the inner surface of the opening 118, and the method of forming the liner oxide layer 120 is performed by, for example, a thermal oxidation method. Due to thermal oxidation, a silicon oxide layer 122 is formed on the surface of the amorphous silicon layer 116a. Next, a second silicon oxide layer 124 is formed on the substrate 100 and fills the opening 118. The method for forming the silicon oxide layer 124 is, for example, CVD deposition. Then, the silicon oxide layer 124 is subjected to a uniform densification (DensiHcation) step. For example, tempering is performed at a temperature of about 1000 ° C to make the oxide sand layer 124 dense. At the same time, the amorphous sand layer 116a will recrystallize due to the high temperature and transform into a single crystal silicon layer 116b. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure ID, and perform a planarization process to remove the silicon oxide layers 124 and 122 on the single crystal silicon layer 116b. For example, use CMP for honing until the amorphous silicon is exposed. The layer 116b stops when the single crystal silicon layer 116b is used as the termination layer of the CMP. In addition, when forming the opening 110, a dummy pattern can be used, that is, a plurality of openings are formed in other regions, and a single crystal silicon layer is formed therein to increase the formation position of the single crystal silicon layer H6b. The ability to sense the end of the honing can improve the uniformity of the CMP. A sacrificial oxide layer 126 is then formed on the surface of the single crystal silicon layer 116b to remove impurities and ensure the quality of the surface structure of the SOI. If the substrate 100 needs to be doped, such as forming a well area, it can be doped at this time. 8 Paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 486twf.d. e / 〇〇2 486twf.d〇e / 〇〇2 Intellectual Property Bureau of the Ministry of Economic Affairs, printed by employee consumer cooperatives 406355 V. Description of invention (1) Miscellaneous, for example, is performed by ion implantation. Due to the present invention, in the CMP process, a single-crystal silicon layer is used as a honing stop layer, and when the opening n8 is produced, a photoresist layer in a conventional lithographic etching method is used as an etching mask, and the traditional The silicon nitride hard cover curtain layer, therefore, during the process of manufacturing shallow trench isolation, the stress problem caused by the traditional use of the silicon nitride hard cover curtain layer does not occur. Please refer to Fig. 1E. Remove the exposed silicon oxide layer on the surface of the substrate 100 and the single crystal silicon layer ii6b. For example, use hydrofluoric acid (HF) solution as wet dip (Wet dip) to remove the silicon oxide layer Π4, the oxide layer 112 and The sacrificial oxide layer 126 and a part of the silicon oxide layer 124. However, the wet dip only removes the silicon oxide layer exposed on the surface of the substrate 100 and the single crystal silicon layer 116b, and the silicon oxide layer 114 and the liner oxide layer 112 under and around the single crystal silicon layer 116b are not removed. The single-crystal silicon layer 116b, the silicon oxide layer 114 and the liner oxide layer 112 below it constitute a structure with silicon (SOI) on the insulating layer. In the manufacturing process of forming the SOI, the depth of the first opening 110, and the first liner oxide layer 112, the first silicon oxide layer 114, the second liner oxide layer 120, the silicon oxide layer 122, and the sacrificial oxide layer 126 can be controlled. The thickness of the single crystal silicon layer U6b is controlled, so that the CMOS device has better performance and lower leakage current. For example, the thickness of the single crystal silicon layer 116b is about 500 angstroms. Please refer to FIG. 1F to fabricate a semiconductor device. For example, a gate oxide layer 128 is formed on the substrate 100 and the single crystal silicon layer 116b by a thermal oxidation method, and then a doped polysilicon is deposited on the gate oxide layer 128 by CVD to form the gate layer 130. Then, the manufacturing process of post-components will be carried out, which will not be repeated here. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -IJ— II 1 I --- I--installation ------- order --- I- I I --- Line (please read the note on the back first to fill in this page)-4486twf.doc / 002 406355 A7 B7 V. Description of the invention (name) From the above-mentioned preferred embodiments of the present invention, it can be seen that the application of the present invention can provide shallow trench isolation and isolation at the same time. There are two kinds of silicon structure on the insulation layer, which makes it more flexible in the design of the integrated circuit. In the manufacturing process, the photoresist layer is used as the cover layer, and the single crystal silicon layer is used as the termination layer during planarization. It can avoid the stress problem caused by the traditional use of hard cover curtain layer to make shallow trench isolation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ----- I --------------- Order ------- r --- • * (Please read the note on the back first to fill out this page)-Economy Printed by the Consumers' Cooperative of the Ministry of Intellectual Property Bureau of the People's Republic of China Paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)