TW406446B - Thermopile infrared sensor and manufacture method thereof - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
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Abstract
Description
406446 五、發明說明(1) 【發明之背景】 發明之領域 本發明係關於一種熱電堆紅外線感測器與其製造方 法。 習用技術之描述 近年來以熱電偶作為溫度量測是相當廣泛的技術,其 原理為藉由加熱兩導體接合處之一端,使其與兩導體之另 一端產生溫差而生成一擴散電流,一個相當的反向電動勢 可消去此電流而平衡,此熱電動勢便是赛貝克(Seedback) 電壓。藉由量測賽貝克電壓之大小,便可知道熱電偶兩端 之溫差而校正溫度。而賽貝克電壓的大小係由兩端的溫差 大小和此二導體的赛貝克係數之乘積決定《將複數對之熱 電偶串聯起來即成為熱電堆,因此,熱電堆的熱電動勢等 於單一熱電偶的賽貝克電壓值乘以串聯的熱電偶數。 以下將說明一種習知之熱電堆紅外線感測器之構造。 圖1 A顯示一種習知之熱電堆感測器之俯視圖。圖1 B為 沿著圖1 A之線L-L之剖視圖,圖1 C為圖1 A之佈線圖。參見 圖1 A與1 B,此熱電堆感測器包含:一矽基板1 ; 一第一介 電層2與一絕緣膜2 ’,分別位於矽基板1之正反面;複數之 多晶矽導體3,位於第一介電層2上;一第二介電層4,位 於第一介電層2與多晶矽導體3上,用以罩覆多晶矽導體 3 ;複數之金屬導體5,位於第二介電層4上;一第三介電 層6,位於第二介電層4與金屬導體5上,用以罩覆金屬導 體5 ; —黑體層7,位於該第三介電層6之中央區域,用以406446 V. Description of the invention (1) [Background of the invention] Field of the invention The present invention relates to a thermopile infrared sensor and a manufacturing method thereof. Description of conventional technology In recent years, thermocouples are widely used for temperature measurement. Its principle is to generate a diffusion current by heating one end of the junction of two conductors and causing a temperature difference between the other end of the two conductors. The back electromotive force can be balanced by eliminating this current, and this thermoelectromotive force is the Seedback voltage. By measuring the Seebeck voltage, you can know the temperature difference across the thermocouple and correct the temperature. The size of the Seebeck voltage is determined by the product of the temperature difference between the two ends and the Seebeck coefficient of the two conductors. Beck voltage value multiplied by the number of thermocouples in series. The structure of a conventional thermopile infrared sensor will be described below. FIG. 1A shows a top view of a conventional thermopile sensor. Fig. 1B is a sectional view taken along line L-L of Fig. 1A, and Fig. 1C is a wiring diagram of Fig. 1A. 1A and 1B, this thermopile sensor includes: a silicon substrate 1; a first dielectric layer 2 and an insulating film 2 ', which are respectively located on the front and back of the silicon substrate 1; a plurality of polycrystalline silicon conductors 3, On the first dielectric layer 2; a second dielectric layer 4 on the first dielectric layer 2 and the polycrystalline silicon conductor 3 for covering the polycrystalline silicon conductor 3; a plurality of metal conductors 5 on the second dielectric layer 4; a third dielectric layer 6 is located on the second dielectric layer 4 and the metal conductor 5 to cover the metal conductor 5; a black body layer 7 is located in the central region of the third dielectric layer 6 and To
第4頁 _406446_ 五、發明說明(2) 吸收熱量;以及一窪部8。 參見圖1A與1B,於此熱電堆感測器之結構中,依據熱 傳導之程度,可區分為位於窪部8以上部分之熱絕緣區9, 以及位於熱絕緣區9以外之熱汲體區1 0。其中,黑體層7所 吸收的熱量在熱絕緣區9無法散去,僅能沿著往熱汲體區 10的方向作固體熱傳導。 參見圖1B與1C,每一對多晶矽導體3與金屬導體5於熱 絕緣區9接觸於熱端Η,用以形成一熱電偶11,而複數之熱 電偶11係以串聯的方式接觸於熱汲體區10的冷端(未顯 示)。為提高熱電堆感測器之良率,通常每一個熱端Η或冷 端宜具有複數之接點1 2。相鄰兩熱電偶1 1之間距為1,以 下稱為設計規範。 以下,將說明另一種習知熱電堆感測器之構造。 圖2Α顯示一種習知之熱電堆感測器之俯視圖。圖2Β為 沿著圖2Α之線Μ-Μ之剖視圖,圖2C為圖2 Α之佈線圖。如圖 2 A與2 B所示,此種熱電堆感測器之構造大部分與圖1 A和1 B 類似,於此不再詳述。比較圖2 B與圖1 B,兩者之不同點 為:圖2 B之熱電堆感測器係由晶片正面進行異方性蝕刻所 造成的浮板(第一介電層2)以支撐複數之熱電偶11與黑體 層7等,而圖1 B之熱電堆感測器則由晶片背面進行異方性 姓刻所造成的薄膜(第一介電層2)以支撐複數之熱電偶11 與黑體層7等。 以下將說明熱電堆感測器之特性。 上述的熱電堆感測器之特性可以下列幾個量表示:感Page 4 _406446_ V. Description of the invention (2) Absorption of heat; and a depression 8. 1A and 1B, in the structure of this thermopile sensor, according to the degree of thermal conduction, it can be divided into a thermal insulation region 9 located above the depression 8 and a heat sink region 1 located outside the thermal insulation region 9 0. Among them, the heat absorbed by the black body layer 7 cannot be dissipated in the thermal insulation region 9, and solid heat conduction can be performed only in a direction toward the heat sink region 10. 1B and 1C, each pair of polycrystalline silicon conductor 3 and metal conductor 5 are in contact with a hot end at a thermal insulation region 9 to form a thermocouple 11, and a plurality of thermocouples 11 are connected to a heat sink in series. The cold end (not shown) of the body region 10. In order to improve the yield of thermopile sensors, usually each hot end or cold end should have multiple contacts 12. The distance between two adjacent thermocouples 1 is 1, which is hereinafter referred to as the design specification. Hereinafter, the structure of another conventional thermopile sensor will be described. FIG. 2A shows a top view of a conventional thermopile sensor. Fig. 2B is a cross-sectional view taken along the line M-M of Fig. 2A, and Fig. 2C is a wiring diagram of Fig. 2A. As shown in Figures 2A and 2B, the structure of this type of thermopile sensor is mostly similar to Figures 1A and 1B, and will not be described in detail here. Comparing FIG. 2B and FIG. 1B, the difference between the two is: The thermopile sensor of FIG. 2B is a floating plate (first dielectric layer 2) caused by anisotropic etching on the front side of the wafer to support the plurality The thermocouple 11 and the black body layer 7 and the like, and the thermopile sensor of FIG. 1B is a thin film (the first dielectric layer 2) formed by the anisotropic engraving on the back of the wafer to support the plurality of thermocouples 11 and Blackbody layer 7 and so on. The characteristics of the thermopile sensor will be described below. The characteristics of the above thermopile sensor can be expressed in the following quantities:
III11III11
第5頁 4〇fi446 五、發明說明(3) 測度Rv、詹森(Johnson)雜訊V】、等效 以及特Page 5 4〇fi446 V. Description of the invention (3) Measure Rv, Johnson noise V], equivalent and special
j τ从雜訊功垄NFPj τ from noise power NFP
定偵測率D*,其對應公式可表示為: 力半NbP Να 〇s+Gg+GrThe fixed detection rate D *, its corresponding formula can be expressed as: Force NbP Να 〇s + Gg + Gr
Vj =V4®47 D'Vj = V4®47 D '
κ 獨 ~mF (1)(2) ⑶(4) 式中N為串聯的熱電偶數目,α為由 數U/W。而Gs、Gg、Gr分別為元件的^貝克係 及輻射熱傳導。k為波茲曼常數,τ為感的固體、痛 (。1〇,R為串聯熱電偶的電阻值,△ f為瓶、之、邑對溫度 器面積。 ,、、、頸寬,而A為感測 氣體 對於這樣一個 熱電堆感測器,其優質量的定 高感測度1與特定彳貞測率D*,降低詹森雜 =· ^ 功率NEP。為了比較的歸一性,在固定的感測器專二f及訊頻 寬Δί之下’若感測器的NEP值越小,則其偻皙蔷勒古 即,NEP之倒數(Rv/ Vj)值越大越好。、Μ量越同’亦 近年來’利用半導體微影技術及微加工技術製作之熱 電堆,可參見以下附件: ^ (l).G.R.Lahiji and K.D.Wise, "A batch-fabricated silicon thermopile infrared detector", IEEE Trans. Electron Devices ED-29,κ ~ mF (1) (2) ⑶ (4) where N is the number of thermocouples connected in series, and α is the number U / W. Gs, Gg, and Gr are the element's Baker system and radiant heat conduction, respectively. k is the Boltzmann constant, τ is the sensed solid, pain (.10, R is the resistance value of the thermocouple in series, △ f is the area of the thermostat of the bottle, tube, and tube.,,, neck width, and A In order to sense the gas for such a thermopile sensor, its high-quality fixed height sensing degree 1 and the specific measurement rate D * reduce the Johnson Sensitivity = · ^ Power NEP. In order to compare the normality, in the fixed If the sensor ’s NEP value is smaller, the sensor ’s NLE value is smaller, ie, the larger the inverse value (Rv / Vj) of the NEP is, the better. Yuetong's 'Yearly' thermoelectric stacks made with semiconductor lithography and micromachining technologies can be found in the following attachment: ^ (l). GRLahiji and KDWise, " A batch-fabricated silicon thermopile infrared detector ", IEEE Trans. Electron Devices ED-29,
4〇ft446 五、發明說明(4) PP14-22, ( 1 982 )(附件一); . (2) . W.G. Baer, T.Hull, Kevin D. Wise, K.〇ft446 V. Description of the invention (4) PP14-22, (1 982) (Annex I);. (2). W.G. Baer, T. Hull, Kevin D. Wise, K.
Najafi and Kensall D. Wise, "A multiplexed silicon-infrared thermal imager" , Transducers 9.1, pp631-634, (1991)(附件二); (3) . R. Lenggenhager, H. B a 11 e s, J. Peer and M.Forster, "Thermoelectric infrared sensors by CMOS technology", IEEE Electron Device Letters 13, 4 5 4, ( 1 9 9 2 )(附件三);以及 (4) . E.Olgun, O.Akar, H.Kulah and T.Akin, "An integrated thermopile structure with high responsivity using any stndard CMOS process",Najafi and Kensall D. Wise, " A multiplexed silicon-infrared thermal imager ", Transducers 9.1, pp631-634, (1991) (Annex II); (3). R. Lenggenhager, H. B a 11 es, J. Peer and M. Forster, " Thermoelectric infrared sensors by CMOS technology ", IEEE Electron Device Letters 13, 4 5 4, (1 9 9 2) (Annex III); and (4). E. Olgun, O. Akar, H. Kulah and T. Akin, " An integrated thermopile structure with high responsivity using any stndard CMOS process ",
Trans、ducers’97, PP 1 2 6 3 - 1 2 6 6, ( 1 9 9 7 )(附件四)。 件(參丰所^ f =獻為例,由E. 〇 1 gun等人所提出的元 金屬以=二至較二以 賽貝克係數α所導致r α ^ 卞王一 J /、啕更円的 到)。然而此-感一結果可以由公式⑴推導得 為N型矽及P型矽相° 、J雜訊亦較其他感測器高,原因 導致整體感測器的R 其他金屬材料皆為高電阻值材料,、 件的製作必須配合^ ^值並無多大改變。再者,此一元 完成,增加了製程的複: 度蝴(P++)之蚀刻抑止方法 晶矽/金屬熱電堆感測雜陡t降低了量產的良率。雖然多 的1值較低,但其V:值也一樣較Trans, ducers’97, PP 1 2 6 3-1 2 6 6, (1 9 9 7) (Annex 4). (Shenfeng Institute ^ f = Dedicated as an example, the meta-metal proposed by E. 〇1 gun et al. = = 2 to 2 is caused by the Seebeck coefficient α r ^ 卞 王 一 J / 、 啕 更 啕To). However, this result can be deduced from the formula ⑴ as N-type silicon and P-type silicon phase, and J noise is higher than other sensors. The reason is that the overall sensor R and other metal materials have high resistance values. The production of materials and pieces must match the value of ^ ^ without much change. In addition, this one-dimensional completion is completed, which increases the complexity of the process: etch suppression method of P + + crystalline silicon / metal thermopile sensing stray t reduces the yield of mass production. Although the value of 1 is lower, the V: value is the same.
A06446 五、發明說明(5) 低。因此,多晶矽/金屬熱電堆感測器之Rv/ t與N型多晶. 矽/P型矽之感測器的1^/ V:值相差不多。 多晶矽/金屬熱電堆感測器之優點為製程簡單且量產-的良率高,因此,如何提升此一感測器的特性正是下面所 要要探,討的主題。 從公式(1 )可以發現提高感測度Rv值最直接的方法為 增加熱電偶數目N,或選擇高〇:係數的材料,然而N和α是 由製程的設計規範λ (熱電偶之間距)及材料決定。在選定 製程以後,便無法更改了。在此情況下,改善結構的熱傳 導值(05 + 08邝」是另一可行的方式。此乃因為降低熱傳導 值除了會增加感測器之1值外,根據公式(2 )亦可發現對 其V;並無影響,故其Rv/ V;值可以因此提高。而通常這類 感測器之結構的熱傳導值是由固體熱傳導值〇5所主導,此 乃因為大量之熱電偶數N加大了固體熱傳導值。因此,在 不改變元件製程下,有效降低熱電堆感測器的固體熱傳導 值正是本發明的目的。 以下將說明習知熱電堆感測器之製作佈局對其優質量 所造成的影響。 分析多晶矽/金屬熱電感測器可發現多晶矽材料主導 感測器的赛貝克係數(約為A 1 、Au金屬的5 0 - 2 0 0倍)及電阻 值(約為A1、Au金屬的1000-2000倍),而其固體熱傳導值 卻是由金屬所主導(一般感測器中,金屬之熱傳導值約為 多晶矽的3倍以上)。所以,若能降低金屬的熱傳導值則可 以有效增加1值。一般而言,降低熱傳導值的直覺方法即A06446 5. Description of the invention (5) Low. Therefore, the Rv / t of a polycrystalline silicon / metal thermopile sensor is similar to that of an N-type polysilicon. Silicon / P-type silicon sensor. Polycrystalline silicon / metal thermopile sensors have the advantages of simple manufacturing process and high yield. Therefore, how to improve the characteristics of this sensor is the subject to be explored and discussed below. From formula (1), it can be found that the most direct way to increase the Rv value of the sensor is to increase the number of thermocouples N, or choose a material with a high 0: coefficient. However, N and α are determined by the process design specification λ (distance between thermocouples) and Material decision. After the process is selected, it cannot be changed. In this case, improving the structure's heat conduction value (05 + 08 邝 "is another feasible way. This is because reducing the heat conduction value will not only increase the value of the sensor, but also according to formula (2) V; has no effect, so its Rv / V; value can be increased accordingly. Generally, the heat conduction value of the structure of this type of sensor is dominated by the solid heat conduction value 05, because a large number of thermocouples N has increased. Solid heat conduction value. Therefore, it is the object of the present invention to effectively reduce the solid heat conduction value of a thermopile sensor without changing the component manufacturing process. The following will explain the conventional thermopile sensor manufacturing layout caused by its high quality Analysis of the polycrystalline silicon / metal thermal sensor can find the Seebeck coefficient (about 50 to 2000 times of A 1 and Au metal) and resistance value (about A1, Au metal) 1000-2000 times), and its solid thermal conductivity value is dominated by metal (in general sensors, the thermal conductivity value of metal is about 3 times that of polycrystalline silicon). Therefore, it can be effective if the thermal conductivity value of metal can be reduced increase 1 value. In general, intuitive method of reducing thermal conductivity values, i.e.
_406446_ 五、發明說明(6) 是將熱傳輸的距離加大,對於傳統感測器之佈局方式即是 將構成熱電偶的條狀材料延長,此舉雖然可以有效降低熱 傳導值,卻伴隨了更多的缺點。首先是因為長度的增加而 加大了多晶矽之電阻值,導致L值增大,故而Rv/Vj值並無 明顯增加;其次為長度的增加使懸浮結構的機械特性更脆 弱,易導致薄膜破裂;最後因感測器的等效面積加大,降 低了單位面積的生產數目。因此,熱傳導值的降低必須同 時考量以上之問題。 圖3A顯示一種習知之熱電堆感測器之局部佈局示意 圖。參見圖3A,多晶梦導體3為多晶妙材料所組成’而金 屬導體5為金屬材料所組成,亦可以是金或與1C相容的的 鋁所組成。多晶矽導體3與金屬導體5,係分別位於第一介 電層2與第二介電層4上,僅在熱接觸區Η及冷接觸區作歐 姆接觸。基於上述的理由,對於此種結構之熱電堆感測器 而言,直接延長熱電偶之長度並不能獲得較佳之效果。 雖然感測器的佈局以為求得到最多熱電偶對數Ν為 佳,但是熱電偶之間距λ為其最小設計規範。若所選用之 材料及製程已決定,則感測器的特性也會被決定。誠如前 面所提過,熱電堆感測器的固體熱傳導值是由金屬材料所 組成的金屬導體5所決定,因此若能增加金屬導體5之有效 長度,就可有效的降低其熱傳導值。 圖3 Β顯示另一種習知之熱電堆感測器之局部佈局圖。 參見圖3 Β,多晶矽導體3與金屬導體5,亦分別位於第一介 電層2與第二介電層4上,僅在熱接觸區Η及冷接觸區作歐_406446_ V. Explanation of the invention (6) is to increase the distance of heat transmission. For the layout of traditional sensors, it is to extend the strip material constituting the thermocouple. Although this can effectively reduce the thermal conductivity value, it is accompanied by more Many disadvantages. Firstly, the resistance value of polycrystalline silicon is increased due to the increase in length, which causes the L value to increase, so the Rv / Vj value does not increase significantly; secondly, the increase in length makes the mechanical characteristics of the suspension structure more fragile, and easily causes the film to crack; Finally, because the equivalent area of the sensor is increased, the number of units per unit area is reduced. Therefore, it is necessary to consider the above problems while reducing the heat conduction value. Fig. 3A shows a schematic partial layout of a conventional thermopile sensor. Referring to Fig. 3A, the polycrystalline dream conductor 3 is composed of a polycrystalline material 'and the metal conductor 5 is composed of a metallic material, and may also be composed of gold or 1C-compatible aluminum. The polycrystalline silicon conductor 3 and the metal conductor 5 are located on the first dielectric layer 2 and the second dielectric layer 4, respectively, and make ohmic contact only in the hot contact area 冷 and the cold contact area. Based on the above reasons, for a thermopile sensor of this structure, directly extending the length of the thermocouple cannot obtain a better effect. Although the layout of the sensor is best to obtain the maximum number of thermocouple pairs N, the distance λ between the thermocouples is its minimum design specification. If the selected materials and processes have been determined, the characteristics of the sensor will also be determined. As mentioned earlier, the solid heat conduction value of a thermopile sensor is determined by the metal conductor 5 composed of a metal material. Therefore, if the effective length of the metal conductor 5 can be increased, its heat conduction value can be effectively reduced. Figure 3B shows a partial layout of another conventional thermopile sensor. Referring to FIG. 3B, the polycrystalline silicon conductor 3 and the metal conductor 5 are also located on the first dielectric layer 2 and the second dielectric layer 4, respectively, and are used only in the hot contact area Η and the cold contact area.
第9頁 406446 五、發明說明(7) 姆接觸。其特點在於:由金屬材料所組成之金屬導體5係 以彎曲狀之方式排列。在設計規範已經固定的狀況下,雖 然金屬導體5之有效長度增加了η倍(η>1),但是熱電偶11 - 之間距亦會增加約η λ。所以,在增加Rv上,亦不具有較 大之影響力。 以下,將說明習知熱電堆感測器之製造方法所面臨的 問題。 利用矽異方性蝕刻製作的熱電堆元件,在生產過程中 所面臨的主要問題有二:一為懸浮結構的殘餘應力所導致 的結構變形或破裂;二為在晶片切割分離時,因振動及冷 卻水沖刷所造成的懸浮結構破裂。一般而言,殘餘應力的 補償是可以利用I C製程中不同應力屬性的氧化矽及氮化矽 以完成。所以,因傳統鑽石刀晶片切割所造成的破壞係為 生產熱電堆感測器所面臨的一大問題。 一種解決的方法為在進行懸浮結構的矽異方性蝕刻 時,同時在切割道進行蝕刻,此一方法的缺點為切割道所 佔的有效面積太大,從而降低單位面積所產出的感測器數 目。因此,解決上述生產方式所面臨問題為本發明之另一-目的。 因此,本發明之目的如下:(一)提升熱電堆紅外線感 測器之特性,亦即,在不改變感測器面積、晶片大小及熱 電偶數目之情況下,降低多晶矽/金屬熱電堆紅外線感測 器之固體熱傳導值,以增加感測度且保持詹森雜訊不變; (二)提高生產之良率:利用高密度電漿活性離子蝕刻技術Page 9 406446 V. Description of the invention (7) Contact with Mu. It is characterized in that the metal conductors 5 composed of metal materials are arranged in a curved manner. Under the condition that the design specifications have been fixed, although the effective length of the metal conductor 5 is increased by η times (η > 1), the distance between the thermocouples 11-will also increase by about η λ. Therefore, it does not have much influence in increasing Rv. In the following, the problems faced by the conventional method of manufacturing a thermopile sensor will be described. The main problems faced in the production of thermopile elements using silicon anisotropic etching are two: one is the structural deformation or cracking caused by the residual stress of the floating structure; the other is the vibration and The suspension structure rupture caused by cooling water flushing. In general, residual stress compensation can be accomplished using silicon oxide and silicon nitride with different stress properties in the IC process. Therefore, the damage caused by the traditional diamond knife wafer cutting is a major problem facing the production of thermopile sensors. One solution is to etch on the scribe line while performing silicon anisotropic etching of the suspension structure. The disadvantage of this method is that the effective area occupied by the scribe line is too large, thereby reducing the sensing output per unit area.器 数。 Number of devices. Therefore, it is another object of the present invention to solve the problems faced by the above production methods. Therefore, the purpose of the present invention is as follows: (1) To improve the characteristics of a thermopile infrared sensor, that is, to reduce the polycrystalline silicon / metal thermopile infrared sensitivity without changing the sensor area, chip size, and number of thermocouples. The solid heat conduction value of the detector to increase the sensitivity and keep the Jansen noise unchanged; (2) Improve the production yield: use high-density plasma active ion etching technology
第10頁 406446 五、發明說明(8) 同時作為形成懸浮結構的異方性蝕刻和晶片分離技術,以 取代傳統的矽異方性蝕刻和晶片切割方式,以提高單位面 積的元件數量及增加生產的良率。 【發明之綜合說明】 因此,本發明之目的係提供一種熱電堆紅外線感測器 與其製造方法,俾能提升感測器之特性與提高生產之良 率。 依據本發明第一實施樣態,係關於一種熱電堆紅外線 感測器,包含:一矽基板;一第一介電層,位於上述矽基 板上;複數之多晶矽導體,位於第一介電層上;一第二介 電層,位於第一介電層與上述多晶矽導體上,用以罩覆上 述多晶矽導體;複數之金屬導體,位於第二介電層上;一 第三介電層,位於第二介電層與上述金屬導體上,用以罩 覆上述金屬導體;以及一黑體層,位於第三介電層之中央 區域,用以吸收熱量;其中,上述矽基板、第一至第三介 電層、金屬導體均包含一位於中央區域之熱絕緣區,與位 於中央區域以外之熱汲體區,且金屬導體係以串聯的方式 電連接,且於熱絕緣區接觸於複數之熱端,而於熱汲體區 接觸於複數之冷端;其特徵為: 上述熱電堆紅外線感測器更包含: 第四至第η介電層(η為大於等於4之正整數),依序介 設於第三介電層與上述黑體層之間,且第四介電層係與第 三介電層鄰接;且上述金屬導體係為迂迴彎曲狀,更包Page 10 406446 V. Description of the invention (8) Simultaneously used as anisotropic etching and wafer separation technology to form a suspended structure, to replace the traditional silicon anisotropic etching and wafer cutting methods to increase the number of components per unit area and increase production Yield. [Comprehensive description of the invention] Therefore, the object of the present invention is to provide a thermopile infrared sensor and a method for manufacturing the same, which can improve the characteristics of the sensor and increase the yield rate of production. According to a first aspect of the present invention, a thermopile infrared sensor includes: a silicon substrate; a first dielectric layer on the silicon substrate; and a plurality of polycrystalline silicon conductors on the first dielectric layer. A second dielectric layer on the first dielectric layer and the polycrystalline silicon conductor to cover the polycrystalline silicon conductor; a plurality of metal conductors on the second dielectric layer; a third dielectric layer on the first dielectric layer Two dielectric layers and the above-mentioned metal conductors are used to cover the above-mentioned metal conductors; and a blackbody layer is located in the central region of the third dielectric layer to absorb heat; wherein the silicon substrate, the first to third dielectrics, The electrical layer and the metal conductor each include a thermally insulated region located in the central region and a heat sink region located outside the central region, and the metal conducting system is electrically connected in series and in contact with the plurality of hot ends in the thermally insulated region. The heat sink body area is in contact with a plurality of cold ends; the above-mentioned thermopile infrared sensor further includes: a fourth to n-th dielectric layer (where η is a positive integer greater than or equal to 4) and sequentially arranged Yudi Between the three dielectric layers and the black body layer, and the fourth dielectric layer is adjacent to the third dielectric layer; and the metal conductive system is in a meandering shape, more inclusive
— 406446 五、發明說明(9) 含: 複數組之第一至第(n-2)金屬子導體,其中,第-金 屬子導體係介設於第二與第三介電層之間、第(n-2)金屬 子導體係介設於第(n-l)與第η介電層之間,且第k金屬子 導體(l<k<n-2,k為正整數)係分別介設於第(k + Ι)與第 (k + 2)介電層之間,而第一至第(n-2)金屬子導體之每—組 在投影至第二介電層後,係呈現第一至第(n-2)金屬子導 體之順序排列。 依 感測器 種低應 並於位 之後, 上以多 第一介 之切割 屬導體 據本發 之製造 力介電 於第一 於第一 晶矽形 電層上 道;於 ,第一 觸於熱端與冷 晶矽導 屬導體 第三介 二金屬 ,其中 一組多 第一金 道;於 體,第 於熱端 矽導體與第 方法, 材料, 介電層 介電層 成複數 以介電 第二介 金屬導 端,其 體與第 上堆積 電層上 子導體 所接觸 金屬子 包含以下 於上述石夕 反侧之上 上形成複 之多晶矽 材料堆積 電層上形 體分別與 中所接觸 —金屬導 ~第三介 形成适趣 分別與偶 形成的熱 導體所形 步驟:提供一破基板 基板上形成一第一介 述矽基板上形成一絕 教之切割道;於第— 導體;於上述多晶矽 第二介電層,並形 成适迴彎曲狀之複數 奇數對之上述多晶石夕 形成的熱端與冷端並 趙所形成;於第二介 電層,並形成複數之 贊曲狀之複數第二金 數%之上述多晶矽導 端與冷端並非由同一 成,且第二金屬子導 紅外線 、 以一 電層, 緣膜, 介電層 導體與 成複數 第一金 導體接 非由同 電層與 切割 屬子導 體接觸 組多晶 體係與— 406446 V. Description of the invention (9) Contains: the first to (n-2) metal sub-conductors of the complex array, wherein the-metal sub-conducting system is interposed between the second and third dielectric layers, the first (N-2) The metal subconducting system is interposed between the (nl) th and nth dielectric layers, and the kth metal subconductor (l < k < n-2, where k is a positive integer) is interposed respectively Between the (k + Ι) th and (k + 2) th dielectric layers, and each of the first to (n-2) th metal subconductors is projected onto the second dielectric layer, it presents the first Arranged in order to (n-2) th metal sub-conductor. According to the type of the sensor, the cutting should be in place, and the cutting conductor with multiple first dielectrics is dielectrically formed on the first and first crystalline silicon-shaped electrical layers according to the manufacturing force of the present invention; therefore, the first contact Hot junction and cold crystalline silicon are conductors of the third dielectric and two metals, one group of which is more than the first gold channel; in the body, the hot junction of silicon conductors and methods, materials, dielectric layers The second dielectric metal conductive end, the body and the metal conductor contacted by the sub-conductor on the first stacked electrical layer include the following polycrystalline silicon material on the opposite side of the above-mentioned Shi Xi formed on the stacked electrical layer upper body and the center respectively-metal conductive ~ The formation of the third medium is suitable for the formation of thermal conductors, and the steps are as follows: a broken substrate is formed on the first substrate to form a first intersecting scribe lane on the silicon substrate; the first-conductor; the second on the polycrystalline silicon The dielectric layer is formed by forming the hot end and the cold end of the above-mentioned polycrystalline stone formed by a plurality of odd-numbered pairs in a curved shape; and the second dielectric layer is formed by a plurality of singularities. % Of gold The polysilicon conducting end and the cold end are not formed by the same, and the second metal subconducts infrared rays, and an electrical layer, an edge film, a dielectric layer conductor are connected to a plurality of first gold conductors, but the same electrical layer and the cutting subconductor are not connected. Contact group polycrystalline system and
AM446 五、發明說明(10) 第一金屬導體在投影於第一 體係介設於相鄰之兩第一金 第二金屬子導體上堆積一第 道;於罩覆上述熱端之區域 緣膜上形成複數之姓刻窗口 罩覆於上述熱端之下,且上 準;於上述黑體層與第四介 料堆積形成一晶片固定層; 板進行高密度電漿活性離子 時經由上述切割窗口以乾式 程;以及於上述矽基板背面 去除上述晶片固定層,完成 因此,依據本發明之熱 狀多晶矽導體及彎曲狀金ί ^有效降低整體結構的熱傳 再者’本發明利用高密度電 的去除矽基板材料而留下的 $性钱刻技術完成晶片分離 式’以增加生產良率。 【圖示之簡單說明】 圖1Α顯示一種習知之熱 圖1Β為沿著圖U之線L-圖1C為圖1A之熱電堆感 圖2A顯示一種習知之熱 介電層上時’各第二金屬子導 屬導體之間;於第三介電層與 四介電層’並形成複數之切割-形成複數之黑體層;於上述絕 與切割窗口 ,上述蝕刻窗口係 述切割窗口係與上述切割道對 電層上’以一種高分子厚膜材 經由上述姓刻窗口對上述矽基 钱刻,以形成複數之窪部,同 異方性蝕刻進行晶片分離過 黏著一種晶片固定膠帶,然後 感測器的製造生產流程。 電堆紅外線感測器,利用直條 導體接合而成的熱電偶對,可 導特性,增加元件的感測度。 I活性離子蝕刻技術,選擇性 薄膜結構。同時,利用乾式異 ’取代傳統的鑽石刀切割方 電堆感測器之俯視圖。 L之剖視圖。 測器之佈線圖。 電堆感測器之俯視圖。 406446 五、發明說明(11) 圖2 B為沿著圖2 A之線Μ - Μ之剖視圖。 圖2 C為圖2 Α之熱電堆感測器之佈線圖。 圖3A為依據圖1A與2A之熱電堆感測器之立體佈線示意- 圖。 圖3B為另一種熱電堆感測器之立體佈線示意圖。 圖4A與4B分別示意表示依本發明較佳實施例之熱電堆 感測器在不同部分之剖面圖_。 圖4C為依據圖4A與4B之熱電堆感測器之立體佈線示意 圖。 圖5顯示依本發明之SMT結構與習知結構之熱電堆感測 器之輸入功率與輸出熱電動勢之關係圖。 圖6 A至6 Η係以某一剖面示意顯示依本發明之熱電堆感 測器之製造程序圖。 圖7 Α至7 Η係以另一剖面示意顯示依本發明之熱電堆感 測器之製造程序圖。 【符號之說明】 1 ~梦基板 2 ~第一介電層 3〜多晶矽導體 _ 4〜第二介電層 5〜金屬導體 5a〜第一金屬子導體 5b〜第二金屬子導體AM446 V. Description of the invention (10) The first metal conductor is projected on the first system and is arranged on two adjacent first gold and second metal sub-conductors; the first metal conductor is deposited on the edge film covering the hot end. A plurality of engraved window covers are formed under the hot end, and the upper part is accurate; the black body layer and the fourth dielectric material are stacked to form a wafer fixing layer; when the board performs high-density plasma active ions through the cutting window in a dry type And removing the wafer fixing layer on the back surface of the silicon substrate, so that the heat-like polycrystalline silicon conductor and the curved gold according to the present invention effectively reduce the heat transfer of the overall structure, and furthermore, the present invention uses high-density electricity to remove silicon. The substrate material and the left-over money engraving technology are used to complete the wafer separation type to increase the production yield. [Brief description of the diagram] Figure 1A shows a conventional heat map. Figure 1B is along the line L of Figure U. Figure 1C is the thermopile sense of Figure 1A. Figure 2A shows a conventional thermal dielectric layer. The metal subconductors belong to the conductor; a plurality of cuts are formed between the third dielectric layer and the four dielectric layers-to form a plurality of blackbody layers; the above-mentioned insulation window, the above-mentioned etching window, the above-mentioned etching window, and the above-mentioned cutting On the electrical layer, the silicon-based money is engraved with a polymer thick film material through the above-mentioned engraved window to form a plurality of depressions. The wafer is separated by anisotropic etching. A wafer fixing tape is adhered, and then the sensing is performed. Manufacturing process. The stack infrared sensor uses a pair of thermocouples joined by straight conductors, which can guide the characteristics and increase the sensitivity of the component. I active ion etching technology, selective thin film structure. At the same time, the top view of the traditional diamond knife-cutting square-stack sensor is replaced by a dry type. A sectional view of L. Wiring diagram of the tester. Top view of a stack sensor. 406446 V. Description of the invention (11) FIG. 2B is a cross-sectional view taken along the line M-M of FIG. 2A. FIG. 2C is a wiring diagram of the thermopile sensor of FIG. 2A. FIG. 3A is a schematic three-dimensional wiring diagram of the thermopile sensor according to FIGS. 1A and 2A. FIG. 3B is a three-dimensional wiring diagram of another thermopile sensor. 4A and 4B are schematic cross-sectional views of different parts of a thermopile sensor according to a preferred embodiment of the present invention. Fig. 4C is a schematic three-dimensional wiring diagram of the thermopile sensor according to Figs. 4A and 4B. Fig. 5 is a graph showing the relationship between the input power and the output thermoelectromotive force of a thermopile sensor with an SMT structure and a conventional structure according to the present invention. 6A to 6A are schematic diagrams showing a manufacturing process of a thermopile sensor according to the present invention in a cross section. Figs. 7A to 7A are schematic diagrams showing the manufacturing process of the thermopile sensor according to the present invention in another section. [Description of symbols] 1 ~ dream substrate 2 ~ first dielectric layer 3 ~ polycrystalline silicon conductor _4 ~ second dielectric layer 5 ~ metal conductor 5a ~ first metal sub-conductor 5b ~ second metal sub-conductor
第14頁 406446 五、發明說明(12) 6~第三介電層 7〜黑體層 8〜窪部 9〜熱絕緣區 1 0〜熱汲體區 1 1 ~熱電偶 1 2〜接點 1 3〜第四介電層 1 4〜切割道 1 5〜蝕刻窗口 1 6〜切割窗口 1 7 ~晶片固定層 18〜膠帶 【較佳實施例之說明】 為解決上述問題,本發明提出另一種多層彎曲狀金屬 方式(Serpentine Multi meTal ,以下稱為SMT)以達到降 低熱傳導值之目的。圖4 A與4 B係顯示本發明較佳實施例之 熱電堆感測器在不同部分之剖面圖,圖4 C顯示本發明較佳 實施例之熱電堆感測器之立體佈局示意圖。如圖4 A與4 B所 示,此熱電堆感測器包含:一石夕基板1 ; 一第一介電層2與 一絕緣膜2 ’,分別位於矽基板1之正反面;複數之多晶矽 導體3,位於第一介電層2上;一第二介電層4,位於第一 介電層2與多晶矽導體3上,用以罩覆多晶矽導體3 ;複數 之第一金屬子導體5a,位於第二介電層4上;一第三介電Page 14 406446 V. Description of the invention (12) 6 ~ Third dielectric layer 7 ~ Black body layer 8 ~ Depression 9 ~ Thermal insulation region 1 0 ~ Heat sink region 1 1 ~ Thermocouple 1 2 ~ Contact 1 3 ~ Fourth dielectric layer 1 4 ~ Cutting track 15 ~ Etching window 16 ~ Cutting window 17 ~ Wafer fixing layer 18 ~ Tape [Description of the preferred embodiment] In order to solve the above-mentioned problem, the present invention proposes another multilayer bending Metal-like method (Serpentine Multi meTal, hereinafter referred to as SMT) to achieve the purpose of reducing thermal conductivity. 4A and 4B are cross-sectional views of different parts of a thermopile sensor according to a preferred embodiment of the present invention, and FIG. 4C is a schematic three-dimensional layout diagram of the thermopile sensor according to a preferred embodiment of the present invention. As shown in FIGS. 4A and 4B, the thermopile sensor includes: a stone substrate 1; a first dielectric layer 2 and an insulating film 2 ', which are located on the front and back of the silicon substrate 1, respectively; and a plurality of polycrystalline silicon conductors 3, located on the first dielectric layer 2; a second dielectric layer 4, located on the first dielectric layer 2 and the polycrystalline silicon conductor 3, for covering the polycrystalline silicon conductor 3; a plurality of first metal sub-conductors 5a, located On the second dielectric layer 4; a third dielectric
第15頁 406446 五、發明說明(13) f 6 ?思於上二介電層4與第-金屬子導體5a上,用以“ ί;Ϊ6/,;複數之第二金屬子導體5b,位於Ϊ 介電層6上,一第四介電層13,位於第三介電層6與第二 屬子導體5b上,用以罩覆第二金屬子導體讣;一里:金 7,位於第四介電層13之中奂F祕μ m …、體層 及一蓬部8。層13之中央£域上’用以吸收熱量;以 參見圖4C,吾人可更清楚地了解本實施例之 測元件之佈局方式。將圖4C與圖3A作比較,本實施,感 點在於將圖3A之金屬導體5分成奇數對之特 5a與偶數對之第二金屬子導體5b。其中第第一金金屬子導體 5a與:-交屬子導體“係以兩道相同的金屬製程 ,: 成於第一;丨電層4與第三介電層6上。因 」形 5a與第二金屬子導體5b之間有第三介電層6 導體 離,所以在佈局時可以使SMT之第一與 ^ ^ 與5b在〒間上相互重疊而不會造成短、-’ 體' 最小設計規範又維持不變的情況下:=:匕舉可在 二金屬子導體5U5b之長度,從而以;增加第-與第 器之感測度。 θ力熱電堆紅外線感測 為了證明S Μ Τ的可行性,本發明八 之佈局方式而製作之懸臂式熱電堆刀1 士應於圖3Α及4〇 / 唐為兩道鋁,所對應的η值也約為2。兑,所使用的金屬 寬^!)//!!!,熱電偶數目Ν = 21,且其寸為長200"m、 及64.8kQ。關於本發明之SMT結 分別為64.2ΙίΩ 測器之輸入功率與輸出熱電壓之關係 Π結構之熱電堆感 ’係圖如圖5所示,可發 --406446_ 五、發明說明(14) 現採用SMT技術的熱電堆感測器在相同的輻射輪入 下,具有更高的輪出電壓,且呈倍數的增加。 是有效的降低熱傳導值所導致,㈤時也因為 阻值而不影響其1值。故而在製程上僅需增加二的電- 程,便可使Rv / L值比傳統的熱電堆感測元件呈有效的提 方法 此外,本發明亦提供一種熱電堆紅外線感測器之製造 圖6A至6H係以某一部分之剖面示意表示本發明較佳實 施例之熱電堆紅外線感測器之製造程序。圖7A至7H係以另 一部分之剖面示意表示本發明較佳實施例之熱電堆紅外 感測器之製造程序。 如圖6A與圖7A所示’首先提供一矽基板1,然後,以 一種低應力介電材料,於石夕基板1上形成一第一介電層2, 並於位於第一介電層2反側之矽基板丨上形成一絕緣膜2,, 接著,並於該第一介電層2上形成複數之切割道14。 然後’如圖6B與7B所示,於該第一介電層2上以多晶 矽形成複數之多晶矽導體3。 阳 接著,於該多晶矽導體3與第一介電層2上以介電材 堆積一第二介電層4 ’並形成複數之切割道丨4。然後,於 第二介電層4上形成迂迴彎曲狀之複數第一金屬子導體 5a,第一金屬子導體5a分別與奇數對之多晶矽導體3接觸 於熱端Η與冷端(未顯示)。 接著,如圖6C與7C所示’於第二介電層4與第一金屬Page 15 406446 V. Description of the invention (13) f 6 is considered on the upper second dielectric layer 4 and the first metal sub-conductor 5a, and is used for "Ϊ; 6 / ,; the plurality of second metal sub-conductors 5b, located at上 On the dielectric layer 6, a fourth dielectric layer 13 is located on the third dielectric layer 6 and the second sub-conductor 5b to cover the second metal sub-conductor 讣; a mile: gold 7 is located on the first Among the four dielectric layers 13 are μm…, the body layer and a canopy 8. The central layer of the layer 13 is used to absorb heat; referring to FIG. 4C, we can understand the measurement of this embodiment more clearly. The layout of the components. Comparing FIG. 4C with FIG. 3A, this implementation is sensitive to dividing the metal conductor 5 of FIG. 3A into an odd-numbered pair of features 5a and an even-numbered pair of second metal sub-conductors 5b. Among them, the first gold metal The sub-conductor 5a and:-the intersecting sub-conductor "are made of two identical metal processes: formed on the first; the electrical layer 4 and the third dielectric layer 6; Because there is a third dielectric layer 6 between the "shape 5a" and the second metal sub-conductor 5b, the first and ^^ and 5b of the SMT can be overlapped with each other during the layout without causing short, -In the case where the minimum design specification of the 'body' remains unchanged: =: The dagger can be used in the length of the two-metal subconductor 5U5b, so as to increase the sensing of the first and second devices. In order to prove the feasibility of SMT, the cantilever-type thermopile knives made by the eighth layout method of the present invention should be shown in Figures 3A and 40 / Tang as two aluminum, corresponding to η The value is also about 2. The width of the metal used is ^!) // !!!, the number of thermocouples N = 21, and its size is 200 " m, and 64.8kQ. About the SMT junction of the present invention is the relationship between the input power and the output thermal voltage of the 64.2 ΙΩ tester. The structure of the thermopile inductor is shown in Figure 5, which can be issued --406446_ V. Description of the invention (14) Under the same radiation wheel input, the thermopile sensor of SMT technology has a higher wheel output voltage, which increases by a multiple. It is caused by the effective reduction of the heat conduction value, and its resistance value does not affect its 1 value. Therefore, only two additional electrical processes are required in the manufacturing process to make the Rv / L value more effective than the traditional thermopile sensing element. In addition, the present invention also provides a thermopile infrared sensor manufacturing. Figure 6A To 6H are schematic diagrams showing the manufacturing process of a thermopile infrared sensor according to a preferred embodiment of the present invention with a cross section of a part. Figs. 7A to 7H are schematic cross-sectional views showing the manufacturing process of a thermopile infrared sensor according to a preferred embodiment of the present invention. As shown in FIG. 6A and FIG. 7A, a silicon substrate 1 is first provided, and then a low-stress dielectric material is used to form a first dielectric layer 2 on the Shixi substrate 1 and located on the first dielectric layer 2. An insulating film 2 is formed on the opposite silicon substrate, and then a plurality of scribe lines 14 are formed on the first dielectric layer 2. Then, as shown in FIGS. 6B and 7B, a plurality of polycrystalline silicon conductors 3 are formed on the first dielectric layer 2 with polycrystalline silicon. Next, a second dielectric layer 4 'is deposited with a dielectric material on the polycrystalline silicon conductor 3 and the first dielectric layer 2 to form a plurality of scribe lines. Then, a plurality of first metal sub-conductors 5a are formed in a meandering shape on the second dielectric layer 4, and the first metal sub-conductors 5a are in contact with the odd-numbered pair of polycrystalline silicon conductors 3 at the hot end and the cold end (not shown). Next, as shown in FIGS. 6C and 7C, on the second dielectric layer 4 and the first metal
第17頁 406446 五、發明說明(15) 子導體5a上堆一第三介電層6 ’並形成複數之切割道14。 然後’於第三介電層6上形成迂迴彎曲狀之複數第二金屬 子導體5b,第二金屬子導體5b分別與偶數對之多晶矽導體 3接觸於熱端Η ’且第二金屬子導體5b係與該等第一金屬子 導體5a在投影於第一介電層2上時,各第二金屬子導體5b 係介設於相鄰兩第一金屬子導體5a之間。 然後,如圖6D與7D所示,於第三介電層6與第二金屬 子導體5b上堆積一第四介電層13 ’並形成複數之切割道 14。接著,於罩覆上述熱端H之區域形成黑體層7。 接著,如圖6E與7E所示,於該絕緣膜2,上形成複數之 蝕刻窗口 1 5與切割窗口 1 6,蝕刻窗口丨5係罩覆於熱端η之 下’且各切割窗口 1 6係與各切割道1 4對準β 然後,如圖6F與7F所示,於黑體層7與第四介電層13 上,以一種高分子厚膜材料堆積形成一晶片固定層17 ^ 接>著,如圖6G與7G所示,經由蝕刻窗口15對該矽基板 8 ^ ΐ密度電漿(HDP )活性離子蝕刻,以形成複數之窪部 8 ’同時經由切割窗口16以相同的乾式異方性轴刻進 片分離過程。 ,後,如圖7H與8H所示,於碎基板 】固4=,然後去除該晶片固定層",完成感測器之 表造生產流程。 因此,本發明之製程特點在於:(一 1 7以進行姓刻和切割的程序,將 日日 的破裂現象;(二)採用高密度電號、. 又电聚活性離子蝕刻技術,並Page 17 406446 V. Description of the invention (15) A third dielectric layer 6 'is stacked on the sub-conductor 5a and a plurality of scribe lines 14 are formed. Then 'a plurality of second metal sub-conductors 5b are formed in a meandering shape on the third dielectric layer 6, and the second metal sub-conductors 5b and the polycrystalline silicon conductor 3 of the even pair are in contact with the hot end respectively' and the second metal sub-conductor 5b When the first metal sub-conductors 5a are projected on the first dielectric layer 2, each second metal sub-conductor 5b is interposed between two adjacent first metal sub-conductors 5a. Then, as shown in FIGS. 6D and 7D, a fourth dielectric layer 13 'is stacked on the third dielectric layer 6 and the second metal sub-conductor 5b to form a plurality of scribe lines 14. Next, a black body layer 7 is formed in a region covering the hot end H. Next, as shown in FIGS. 6E and 7E, a plurality of etching windows 15 and cutting windows 16 are formed on the insulating film 2. The etching windows 5 are covered under the hot end η and each cutting window 16 Align with β of each cutting track 14 Then, as shown in FIGS. 6F and 7F, a high-molecular thick film material is stacked on the black body layer 7 and the fourth dielectric layer 13 to form a wafer fixing layer 17 ^ 接 & gt As shown in FIGS. 6G and 7G, the silicon substrate 8 ^ ΐ density plasma (HDP) active ion etching is performed on the silicon substrate 8 through the etching window 15 to form a plurality of depressions 8 ′ at the same time through the cutting window 16 in the same dry type The square axis is carved into the film separation process. After that, as shown in FIGS. 7H and 8H, the broken substrate is fixed to 4 =, and then the wafer fixing layer is removed, to complete the production process of the surface of the sensor. Therefore, the manufacturing process of the present invention is characterized by: (1-17 the process of engraving and cutting, which will break the day-to-day phenomenon; (2) the use of high-density electrical signals, and electro-active ion etching technology, and
40^446 五、發明說明(16) 同時執行晶片異方性蝕刻與晶片分離過程,以取 矽異方性蝕刻和晶片切割方式,藉以提高單位晶 並提高生產良率。 代傳統的 圓之產能40 ^ 446 V. Description of the Invention (16) Simultaneously perform wafer anisotropic etching and wafer separation processes to take silicon anisotropic etching and wafer cutting methods to increase unit crystal and increase production yield. Generation of traditional round capacity
第19頁Page 19
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI452272B (en) * | 2011-05-24 | 2014-09-11 | Univ Nat Kaohsiung Applied Sci | Thermopile sensing element |
| CN111463340A (en) * | 2020-05-09 | 2020-07-28 | 中国科学院微电子研究所 | Thermopile and method of making the same |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI452272B (en) * | 2011-05-24 | 2014-09-11 | Univ Nat Kaohsiung Applied Sci | Thermopile sensing element |
| CN111463340A (en) * | 2020-05-09 | 2020-07-28 | 中国科学院微电子研究所 | Thermopile and method of making the same |
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