經濟部中央標準局貝工消費合作社印製 413989 A7 B7 五、發明説明（/) 本發明一般係關於電信資料切換並且尤其是關於用以 控制電信匯流排之系統和裝置。 現代電信系統一般採用數位式編碼資料取代類比資 料。如果類比資料被使用，則被轉換至數位資料以便將資料 在引導媒體之間切換。資料的切換發生於大電信交換機•其 可接收並且處理成千上萬的資料通道。 在'切換的處理程序中，兩組或者多組分別的資料流可被 組合以形成一組單一資料流=當兩組或者多組資料流被組合 時，被組合的傳輸資料流的總資料數量I或者頻帶寬度*等 於各分別資料流的頻帶寬度之和。當結合兩組或者多組分別 的資料流進入一組單一資料流以便防止資料匯流排上面資 料崩潰時需要精確的控制。 雖然通常以相等的頻帶寬度組合兩組或者多組資料流 進入一組單一資料流，當此組合產生時，產生資料傳輸錯誤 並非不尋常》當它們被組合時此錯誤阻止兩組或者多組資料 流上面另外的資料處理被達成·因爲另外的資料處理將使此 錯誤不易或者不可能檢測。 因此，需要有用以結合兩組或者多組資料流之系統和方 法，其允許當它們被組合時兩組或者多組資料流上面另外的 資料處理被達成。 依據本發明，所提供之資料匯流排控制的系統和方法顯 著地消除或者減低先前所發展結合資料流的系統和方法的 相關缺點和問題》 本發明之一論點是提供用以結合資料流之系統，其包含 .4 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） ---------袭------·訂------^ (請先閲讀背面之注項再填寫本頁) 經濟部中央標準局負工消費合作社印製 413989 A7 _ B7 五、發明説明（2 ) 用以控制資料匯流排之系統該系統包含平行地接收資料封 之資料封接收器。連接到該資料封接收器之一組資料封儲存 元件儲存該資料封》連接到該資料封儲存元件之資料封傳輸 器從該資料封儲存元件接收被儲存的資料封並且經由一組 出口匯流排傳輸該資料封》 本發明提供許多重要的技術優點•本發明之一重要.技術 優點是用以結合資料流之系統選擇分別的資料封以便依據 資料封位址而儲存並且從多數個入口匯流排重新傳輸。利用 改變對應的位址可容易地改變資料封被儲存和重新傅輸之 順序。 本發明另一重要的技術優點是用以控制資料匯流排的 方法包含反應於來自應用電路之引動信號而經由一組出口 匯流排從緩衝器傳輸被儲存的非同步傳送模式資料封。這方 法允許同步傳送模式資料與非同步傳送模式資料經由相同 匯流排可控制地被傳輸。 爲了更完全明白本發明和其優點，接著將配合附圖參考 下面的說明|其中相同的參考號碼代表相同的部份•其中： 第1圖是實施本發明觀念的電信交換機之光纖終端模組 系統方塊圖： 第2圖是貨施本發明觀念在應用電路和匯流排控制電路 之間互連的方塊圖： 第3圖是實施本發明觀念一般連接在應用電路和匯流排 控制電路之間的方塊圓； 第4圖是實施本發明観念在匯流排控制電路組件之間的 本紙張尺度適用中國國家標準（CNS )八4規格（2丨〇X 297公釐） ! ϋ n I I I n •裝 I I 訂 I I I I 線 (請先聞讀背面之注項再填寫本頁) 經濟部中央標準局員工消費合作社印製 413989 A7 B7 五、發明説明（$ ) 連接方塊圖； 第5圖是實施本發明觀念之匯流排控制電路的功能方塊 rm * 圖， 第6圖是依據本發明展示在鏈路緩衝器電路、檔頭緩衝 器、和出口框多工器第一級和第二級之間的連接之方塊圖； 第7圖是實施本發明觀念之一組入口匯流排框格式圖 形： 第_ 8圖是實施本發明觀念之一組出口匯流排框格式圖 形： 第9圖是實施本發明觀念之一組出口匯流排槽格充塡格 式圖形； 第10圖是實施本發明觀念之一組出口槽格位址圖： 第1〖圖是依搛本發明觀念用以控制電信匯流排之方法 的流程圖。 本發明之較佳寅施例展示於圖形中，相同的標號被使用 以指示各圖形中相同的以及對應的部份。 第1圖是實施本發明觀念使用光纖之電信交換機系統10 方塊圖。尤其是，本發明之資料匯流排界面是用以倂入分別 的電信組件，例如電信交換機系統1 〇的分別組件之一組所設 計模組系統。本發明之資料匯流排界面同時也以或者另外被 使用於界面至資料匯流排的其他電信組件中。 光纖電信交換機系統1〇包含連接到光纖連接單元 <光$ 終端器）14和共同控制器16之交換機12。光學電信資料流， 例如一組或者多組位元串列資料 '位元組串列資料、或者串 ’6 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X 297公釐） I II 1 ^ I I 11 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印敢 A7 B7五、發明説明U ) 列資料框流•經由一組或者多組光纖引導器〗8在光纖連接單 元14被接收。這些電信資料流利用光繊連接單元14被轉換至 電氣信號並且傳輸至交換機12以便在資料通道之間切換。交 換機12可切換任何適當尺寸，例如DSO、DS1、DS3、或者 其他適當通道的資料通道。進一步地，任何資料流可包含一 組或者多組具有適當格式的資料通道，例如DSO、DS卜DS3、 或者其他適當的通道。共同控制器16從光纖連接單元14和交 換機12接收控制資料並且傳輸控制資料至該處》 交換機12是具有Μ輸入通道和N輸出通道之一組電信交 換機，其中Μ和Ν是整數。交換機12在Μ輸入通道之任何一 組接收電信資料並且傳送該電信資料至输出k道之任何一 組。交換機1 2，如第1圖中所展示，是一組數位交換機，但 同時也可是一組類比交換機。交換機1 2可包含，例如，徳州 普雷諾的DSC通訊公司所製造的Megahub 600E數位電信交 換機》交換機12包含耦合至矩陣資料多工器電路（MDM)22、 矩陣控制通道確認處理器（PVP)24、線路中繼管理電路 (LTM)26、管理電路（ADMIN)28、時序產生器電路（TG)30、 以及以太網路電路（ENC)32之訊息運送節點20。 矩陣資料多工器電路22進一步地耦合至矩陣控制通道 確認處理器24和時序產生器電路30。矩陣資料多工器電路22 是可被使用以耦合在光纖連接單元14和交換機12的切換矩 陣（未展示出）之間的資料通道之一組界面電路。尤其是，矩 陣資料多工器電路22提供DS0資料界面。矩陣資料多工器電 路22從以16.3 84 Μ HZ頻率操作的10-位元資料通道上面的光 --------袭------t------^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 413989 A7 __^_B7_ 五、發明説明（Γ ) 纖連接單元14接收2〇48組DSO資料通道。這些DSO資料通道 接著被傳輸至交換機12的切換矩陣之Μ輸入埠。 在交換機I2從共同控制器16所接收的控制命令被使用 以決定在切換矩陣Μ輸入埠和Ν輸出埠之間的適當連接。在 連接形成之後DSO資料通道經由切換矩陣被傳輸.在矩陣資 料多工器電路22從切換矩陣之Ν輸出埠被接收的DSO資料通 道接著被傳輸回至光纖連接單元14» 矩陣控制通道確認處理器24被耦合至光纖連接單元14 並且至.訊息運送節點20»矩陣控制通道確認處理器24是一組 切換矩陣管理和控制組件，其處理矩陣通道低位準故障檢測 和故障隔離資料。 線路中繼管理電路26被耦合至光纖連接單元14和訊息 運送節點20。線路中繼管理電路26是一組切換矩陣控制組 件，其接收並且傳輸關於光纖連接單元I4之呼叫處理功能的 資料。 時序產生器電路30被耦合至矩陣資料多工器電路22和 共同控制器丨6»時序產生器電路30是一組交換機時序電路， 其從外部源頭，例如光纖連接單元I4·接收時序資料並且傳 输該時序資料至交換機12組件。 以太網路電路32被耦合至訊息運送節點20和共同控制 器1 6。以太網路電路32是一組資料通訊界面，並且在訊息運 送節點20和共同控制器1 6之間傳送資料。 光纖連接單元14包含光學界面電路（〇TM)40、STSM電 路（STSM)42、匯流排控制電路（BCM)44、矩陣界面電路 _8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I— n ' < —訂 n II， 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印裝 413989 A7 ______B7_. 五、發明説明u ) (MTXI)46 '音調辨認電路（TONE)48，以及高速線路中繼處 理器電路（LTP)50 »光纖連接單元14從光纖引導器18接收數 位式編碼光學資料，進行從光纖引導器丨8所接收資料流的廣 播切換，傳輸同步傳送模式（STM)電信資料至矩陣資料多工 器電路22以及矩陣控制通道確認處埋器24以便經由交換機 12的切換矩陣而切換，並且從交換機12接收被切換的電信資 料以便傅輸於光纖引導器18之上。 光學界面電路40可終止連接到公用交換網路（PSN)之光 學信號，例如OCN3。光學界面電路40從光繊引導器18接收 數位式編碼光學電信資料並且轉換該光學信號成爲電氣信 號•例如具有STS-I-P資料格式之數位信號，以便傳輸至光 纖連接單元14的其他組件。光學界面電路40被耦合至光纖引 導器18以及STSM電路42。 光學界面電路40可包含一組單一電路卡，其具有插入式 連接器（未展示出）以允許電路卡容易地被安裝於包含光纖 連接單元14的其他組件電路卡容室中。另外，光學界面電路 4〇可包含兩組或者多組電路卡|或者一組或者多組電路卡上 面之分離組件。 應用電路一般是任何電信資料傳輸系統組件，它們被耦 合至匯流排控制電路44。各應用電路可包含具有插入式連接 器（未展示出)之單一電路卡以便容易地被安裝於包含光纖 連接單元14的機架中"另外*各應用電路可包含多組電路 卡，或者單一電路卡上面分別的組件。 如第1圖中所展示，STSM電路42被組態以從光學界面電 9 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） — -H n n n I •裝 I II I I I 訂— I I I I . 線 (請先閲讀背面之注$項再填寫本頁) 413989 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明（7 ) 路40接收資料並且傳輸資料至該處。這資料可包含同步傳送 模式電信資料。例如，STSM電路42可接收包含672組DS0所 組成有效負荷資料的資料通道之單一STS-1-P資料通道，其 中各DS0資料通道是等於每秒6七000位元的連續資料流。 STS-1-P資料格式同時也包含於商業標準STS-1資料格式中 之管理、控制、和路由資料，加上另外的專屬管理、控制、 和路由資料。管理資料、控制資料、和路由資料被使用以分 離在STS-1-P資料通道之內分別的DS0資料通道、進行通道 確認、進行設備診斷監視、以及其他適當的功能。 STSM電路42同時也可接收非同步傳送模其（ATM)電信 資料，例如作爲iMPAX封包層資料封或者其他適當的資料格 式被傳輸的資料。iM PAX封包層資料封是一種專屬512-位元 資料格式*其包含4位元有效負荷型式辨識資料、76-位元檔 頭部份、424-位元有效負荷部份 '以及S-位元控制記錄檢査 部份。非同步傳送模式資料可作爲包含另外資料流的固定位 元格式資料框之單一資料流被傳輸。對於所給予的資料流之 每秒傳輸資料框數目可針對非同步傳送模式資料變化以便 容納每組資料流中資料數量以及被傳送資料流數目的浮 動。 匯流排控制電路44可被耦合至一些具有適當功能的其 他應用電路，例如矩陣界面電路46、音調辨認電路48、以及 高速線路中繼處理器電路5 0。所有的應用電路經由入口匯流 排60傳輸資料至匯流排控制電路44並且經由出口匯流排62 從匯流排控制電路44接收資料。這些應用電路同時也包含一 10 本紙張尺度適用中國國家楼準（CNS ) A4規格（210X297公釐) ----------装-- (請先閱讀背面之注意事項再填寫本頁) ,ιτ 線 經濟部中央標準局員工消費合作社印製 413989 A7 B7 五、發明説明（s ) 組模組匯流排界面電路（未展示出）》該模組匯流排界面電路 從應用電路接收資料並且將它轉換成預定格式以便經由入 口匯流排60傳輸。模組匯流排界面電路同時也經由出口匯流 排62接收預定格式的資料並且將它轉換成匯流排界面電路 相關的應用電路可使用的格式》 匯流排控制電路44經由入α匯流排60從應用電路接收 預定格式之電信資料，將該資料多工化進入預定格式之單一 廣播資料流，並且經由出口匯流排62傳輸該廣播資料流。以 此方式，匯流排控制電路44同時也操作如同一組廣播切換元 件》各應用電路從其他的應用電路接收包含資料的廣播資料 流，並且可以適當的方式處理被選擇的資料。舉例而言， STSM電路42可傅輸資料回至光學界面電路40以便在光纖引 導器18上面傳輸至網路。匯流排控制電路44可包含具有插入 式連接器（未展示出）之一組單一電路卡以便容易地被使用 於包含光纖連接單元14之機架中。另外，匯流排控制電路44 可包含多組電路卡，或者單一電路卡上面分別的組件。 矩陣界面電路46提供在光纖連接單元Μ和交換機〖2之 間的協定以及運送格式轉換。矩陣界面電路46是一組應用電 路，其從匯流排控制電路44所傳輸的廣播資料流選擇所需的 資料通道，並且重新格式化且傳輸該資料至交換機12。矩陣 界面電路46被耦合至匯流排控制電路44'矩陣資料多工器電 路22、和矩陣控制通道確認處理器24。矩陣界面電路46轉換 從匯流排控制電路44和交換機1 2所接收的廣播資料流之資 料格式進入可分別地與交換機丨2和匯流排控制電路44匹配 11 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） I- I t —II 批衣— 訂 —I*— 银 (請洗Μ讀背面之注意事項再填寫本頁) A7 413989 B7 五、發明説明（f ) 的資料格式·矩陣界面電路46可包含具有插入式連接器（未 展示出）之單一電路卡以便容易地被使用於包含光纖連接單 元I4之機架中。另外，矩陣界面電路46可包含多組電路卡· 或者單一電路卡上面分別的組件。 音調辨認電路48是一組應用電路，其被耦合至匯流排控 制電路44並且進行光纖連接單元14之音調辨認功能。對於每 組交換機I2的201 6組矩陣埠需要一對音調辨認電路48。音調 辨認電路48與廣播資料流界面並且檢測包含廣播資料流之 各DS0通道上面鍵盤音調之資料表示，最大可至2016組DS0 資料通道。 音調辨認電路48具有可被組態以提供音調檢測和產生 之數位信號處理器元件（未展示出）陣列。音調辨認電路48 可包含具有插入式連接器（未展示出）之單一電路卡以便容 易地被使用於包含光織連接單元14之機架中。另外，音調辨 認電路48可包含多組電路卡，或者單一電路卡上面分別的組 件。 高速線路中繼處理器電路50是光纖連接單元14中所有 電路卡的主要格子控制器並且提供在光纖連接單元14和交 換機12之間的界面=高速線路中繼處理器電路50包含一組微 處理機以及至線路中繼管理電路26之一組通訊界面。 髙速線路中繼處理器電路50可包含具有插入式連接器 (未展示出）之單一電路卡以便容易地被使用於包含光纖連 接單元14之機架中"另外，高速線路中繼處理器電路5 0可包 含多組電路卡|或者單一電路卡上面分別的組件。 12 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） I I 11 線 {請先閲讀背面之注項再填寫本頁) 經濟部中央標準局負工消費合作社印聚 A7 413989 B7_ 五、發明説明（/〇) 入口匯流排60是一組資料匯流排，其從一組應用電路攜 帶具有預定位元結構和預定頻率的資料流至匯流排控制電 路44。例如，各入α匯流排60可包含以25.92MHZ頻率操作 的8位元資料流。其他的位元結構和頻率可被適當地使用。 出口匯流排62 —組資料匯流排•其從一組應用電路攜帶 具有預定位元結構和預定頻率的資料流至匯流排控制電路 44 «例如，各入口匯流排62可包含以5 1.64MHZ頻率操作的 16位元資料流。其他的位元結構和頻率可被適當地使用。 共同控制器16被耦合至交換機12和光纖連接單元14。共 同控制器16是一組處理器，其從交換機12和光纖連接單元14 接收管理 '控制、和路由資料|並且產生安排交換機12和光 纖連接單元1 4之操作的管理、控制、和路由資料"共同控制 器1 6可另外配合於交換機12或者光纖連接單元14之內。 操作時，來自網路的電信資料經由光纖引導器18被傅輸 並且被光纖連接單元14接收。這電信資料接著被轉換成爲電 氣信號，例如672組DS0資料通道，並且從光學界面電路40 經由STSM電路42被傳輸並且經由入口匯流排60被傳輸至匯 流排控制電路44。匯流排控制電路44將接收自各應用電路之 資料多工化進入一組單一廣播資料流並且經由各出口匯流 排62傳輸該廣播資料流。 被傅輸的該廣播資料流被接收於矩陣界面電路46,其接 著傳輸該資料至交換機12。交換機12在分別的672組DSO資 料通道進行切換，例如利用重建672組DS0資料通道之順 序。672組DS0資料通道接著被傳輸回至矩陣界面電路46。 _____ 13 本紙張尺度適用中國國家揉準（CNS > A4規格（210 X 297公釐） I ，裝 訂 银 (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標率局負工消費合作杜印製 經濟部中央標準局員工消費合作社印製 413989 A7 __B7_ 五、發明説明（"） 矩陣界面電路46以預定格式經由入口匯流排60傳輸該672組 DS0資料通道至匯流排控制電路44。匯流排控制電路44接著 產生廣播資料流，包含經由交換機12被切換的672組DS0資 料通道。該廣播資料流被接收於STSM電路42以便經由光學 界面電路40再經由光纖引導器丨6而傳输。該廣播資料也可以 或者另外地被傳輸至矩陣界面電路46、音調辨認電路48、高 速線路中繼處理器電路5 0,或者其他適當的資料處理之適當 電路。 第2圖是展示在STSM電路42和匯流排控制電路44之間 的連接之匯流排控制系統70之連接圖。適當數目的應用電 路’例如STSM電路42,可經由入口匯流排60被耦合至匯流 排控制電路44之多工器78(MUX)。各STSM電路42經由一組 相關的入口匯流排60傳輸被編碼資料之單一資料流至匯流 排控制電路4心在多工器78從各入口匯流排60所接收的被編 碼資料之單一資料流接著被匯流排控制電路44組合進入一 組廣播資料流。該廣播資料流經由出口匯流排62從多工器78 被傳輸至STSM電路42以及其他的應用電路。該廣播資料流 包含來自各單一資料流的一些或者所有的資料，其被編碼格 式允許資料之任何部份被辨識並且置放在廣播資料流之 內。 匯流排控制系統70的平面72和平面74可包含組件，例如 STSM電路42，入口匯流排60 '匯流排控制電路44，以及出 口匯流排62。平面72和平面74之匯流排控制電路44經由高速 率鏈路76被耦合在一起，它們是高頻率資料流，例如以 14 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠） (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 經濟部中央標準局貝工消費合作社印製 413989 A7 B7 五、發明説明（U) 5 1.84MHZ操作的16-位元平行資料通道。從平面74經由髙速 率鍵路76在平面72被接收的該廣播資料流可反應於管理、控 制、和路由資料而部份或者整體地被多工化成爲從平面72 傅輸至平面74的廣播資料流。從平面72經由高速率鏈路76 在平面所接收之廣播資料流也可部份或者整體地被多工 化成爲從平面74傳輸至平面72的廣播資料流。 平面72和平面74可被組態爲完全多餘的實際運送層而 攜帶經由光纖引導器18被接收電信資料的多餘資料流。在這 組態中，只要一組完全資料傳輸通道保持可用，則多餘平面 72和平面74中分別組件的多重失效將不會中斷資料傳输》 平面72和平面74可另外被組態爲攜帶唯一電信資料的 獨立運送層"平面72或者平面74的分別STSM電路42也可以 多餘的格式被組態，以至於一組或者多組STSM電路42在平 面72和平面74中是多餘的》 操作時，平面72之匯流排控制電路44從各入口匯流排60 接收預定資料格式的多數個單一資料流並且將該單一資料 流多工化進入具有預定資料格式之一組第一廣播資料流。平 面72之匯流排控制電路44接著經由出口匯流排62傳輸該第 一廣播資料流至應用電路42»平面72之匯流排控制電路44 同時也經由高速率鏈路76傳輸該第一廣播資料流至平面74 之匯流排控制電路44 » 平面之匯流排控制電路44從各入口匯流排60和該第 —廣播資料流接收包含同步傳送模式資料和非同步傳送模 式資料之多數個單一資料流，並且將該單一資料流以及來自 15 本紙張尺度適用中國國家標準（CNS ) A4規格（2I0X297公釐） ---------ά------tr------線 (1*先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 413989 A7 B7 五、發明説明（〇) 第一廣播資料流的部份或者所有的資料多工化進入一組第 二廣播資料流。平面74的匯流排控制電路44接著經由出口匯 流排62傅輸該第二廣播資料流至STSM電路42 »平面74之匯 流排控制電路44同時也經由高速率鏈路76傳輸該第二廣播 資料流至平面72的匯流排控制電路44。平面72的匯流排控制 電路44接收該第二廣播資料流，並且將來自該第二廣播資料 流的部份或者所有資料多工化進入該第一廣播資料流。 第3圖是依據本發明所建立匯流排控制系統90之連接 圖。匯流排控制系統90包含平面72和平面74。平面74包含 STS Μ電路42，光學界面電路40、矩陣界面電路46'音調辨 認電路48、和高速線路中繼處理器電路50,各如所展示被入 口匯流排60和出口匯流排62耦合至匯流排控制電路44»平面 72包含回音消除器電路（ECHO)92，其被入口匯流排60和出 口匯流排62耦合至匯流排控制電路44»平面72和平面74之匯 流排控制電路44被高速度鏈路76耦合在一起》 STSM電路42、矩陣界面電路46'音調辨認電路48、和 高速線路中繼處理器電路50是應用電路，其以預定格式經由 入口匯流排60傳輸資料並且經由出口匯流排62接收資料。這 資料可包含同步傳送模式資料和非同步傳送模式資料，例如 iMPAX封包層資料封。各應用電路可包含一組模組匯流排界 面電路（未展示出）。該模組匯流排界面電路從應用電路接收 資料並且將之轉換成爲預定格式以便經由入口匯流排60傳 輸。模組匯流排界面電路同時也經由出口匯流排62以預定格 式接收資料並且將之轉換成爲可被匯流排界面電路相關的 •16 本紙張尺度適用中國國家標準（CNS ) A4規格（2ϋ297公釐） ---------袭------1Τ------Φ. (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 413989 A7 __B7___ 五、發明説明（/4 ) 應用電路使用的格式。 光學界面電路40從出口匯流排62接收廣播資料流並且 經由入口匯流排60傳輸一組資料流至匯流排控制電路44。被 光學界面電路接收和傳輸的資料一般僅包含iMPAX封包層 資料封形式之非同步傳送模式資料，它們被使用以在光纖連 接單元1 4組件之間攜帶控制資料和控制命令。同步傳送模式 資料同時也可經由入口匯流排60和出口匯流排62被光學界 面電路40接收和傳輸。 回音消除器電路92包含一組或者多組數位信號處理器 (未展示出），它們可用以從包含於廣播資料流中的分別DS0 資料通道移除回音信號。回音消除器電路92可包含具有插入 式連接器（未展示出）之單一電路卡以允許該電路卡容易地 被安裝於包含光纖連接單元14的其他組件電路卡之容室 中》另外，回音消除器電路92可包含兩組或者多組電路卡， 或者單一電路卡上面一組或者多組分離組件。 匯流排控制系統90之平面72和平面74的匯流排控制電 路44從各入口匯流排60接收單一資料流並且將該資料多工 化以分別地形成第一廣播資料流和第二廣播資料流。該等第 一和第二廣播資料流接著經由出口匯流排62被髙速度鍵路 76傳輸至應用電路，並且至不同平面的匯流排控制電路44。 操作時，資料流被接收於光學界面電路4〇並且被傳輸至 STSM電路42以便經由入口匯流排60依序地傳輸至匯流排控 制電路.44。這些電信資料流接著被匯流排控制電路44多工化 並且經由出口匯流排62和高速率鏈路76以單一廣播資料流 17 本紙張尺度適用中國國家標隼（CNS ) A4規格（2!0X297公釐） ----：-----袭------1T------^ (請先聞讀背面之注意事項再填寫本頁) 413989 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（/5") 傳輸至其他的應用電路" 例如，平面72之匯流排控制電路44的廣播資料流可被接 收於音調辨認電路48。音調辨認電路48處理含在廣播資料流 之內分別的D SO資料通道以辨識包含在分別DSO資料通道中 的雙重音調多頻率（DTNF)音調信號》另外或者添加地，廣 播資料流可被接收於矩陣界面電路46以傳輸至交換機12而 供經由交換機12的矩陣構造對於分別的DS0資料通道之切 換。第一廣播資料流同時也可經由高速度鏈路76被傳輸至回 音消除器電路92並且依序地被平面74的匯流排控制電路44 多工進入第二廣播資料流以便被處理而消除回音信號。 第4圖是匯流排控制系統70和匯流排控制系統90的匯流 排控制電路44之方塊圖。匯流排控制電路44包含入口界面電 路（ING) 100 |其耦合至多數個入口匯流排60。入口界面電路 1〇〇包含用以儲存非同步傳送模式資料之資料緩衝器（未展 示出）以及用以揀帶同步傅送模式資料之旁通連接電路••資 料緩衝器和旁通連接電路之輸出被耦合至多工器電路 (MUX)106之輸入。匯流排界面和時序電路（BIF)104同時也 被耦合至入口界面電路丨00。 匯流排界面和時序電路1〇4是一組模組界面電路，其被 使用以從出口匯流排62接收廣播資料流並且經由入口匯流 排60傳輸一組單一資料流。如第4圖中所展示，匯流排界面 和時序電路104被使用以從出口界面電路102接收廣播資料 流並且將之傅輸至入口界面電路100»從板上控制器電路114 接收的控制資料被使用以選擇地控制資料，該資料是當出口 •18 本紙張尺度適用中國國家標準（CMS ) A4現格（210X297公釐） ---------.裝— (請先閲讀背面之注意事項再填寫本頁)Printed by the Central Standards Bureau of the Ministry of Economy, Shellfish Consumer Cooperative 413989 A7 B7 V. Description of the Invention (/) The present invention is generally related to telecommunication data switching, and in particular, to systems and devices for controlling telecommunication buses. Modern telecommunications systems generally use digitally encoded data to replace analog data. If analog data is used, it is converted to digital data to switch the data between boot media. Data switching takes place in large telecommunication exchanges, which can receive and process thousands of data channels. In the 'switching process', two or more sets of separate data streams can be combined to form a single set of data streams = When two or more sets of data streams are combined, the total number of data in the combined transmission data streams I or the band width * is equal to the sum of the band widths of the respective data streams. When two or more separate data streams are combined into a single data stream in order to prevent the data on the data bus from crashing, precise control is required. Although it is common to combine two or more data streams into a single data stream with equal bandwidth, it is not unusual to generate data transmission errors when this combination is generated. "When they are combined, this error prevents two or more sets of data. Additional data processing on the stream is achieved because additional data processing will make this error difficult or impossible to detect. Therefore, there is a need for a system and method useful for combining two or more sets of data streams that allows additional data processing on the two or more sets of data streams to be achieved when they are combined. According to the present invention, the provided data bus control system and method significantly eliminate or reduce the related disadvantages and problems of previously developed systems and methods that combine data streams. One of the arguments of the present invention is to provide a system for combining data streams , Which contains .4 This paper size applies to Chinese National Standards (CNS > A4 specifications (210X297 mm) --------- Raid ------ · Order ------ ^ (Please Please read the note on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 413989 A7 _ B7 V. Description of the Invention (2) System for controlling data buses Data envelope receiver. A set of data envelope storage elements connected to the data envelope receiver stores the data envelope. A data envelope transmitter connected to the data envelope storage element receives the stored data envelope from the data envelope storage element and passes A set of outlet buses transmits the data envelope. The present invention provides many important technical advantages. One of the important aspects of the present invention. The technical advantage is that the system used to combine the data streams selects separate data envelopes in accordance with the data. The address is stored and re-transmitted from a plurality of entry buses. The order of data storage and re-transmission can be easily changed by changing the corresponding address. Another important technical advantage of the present invention is to control the data flow The method includes the transmission of stored asynchronous transmission mode data packets from a buffer via a set of outlet buses in response to a trigger signal from an application circuit. This method allows synchronous transmission mode data and asynchronous transmission mode data to pass through the same bus. Controllable transmission. In order to fully understand the present invention and its advantages, the following description will be referred to in conjunction with the drawings | wherein the same reference numbers represent the same parts • Among them: Figure 1 is a telecommunication switch implementing the concept of the present invention Block diagram of the optical fiber terminal module system: Figure 2 is a block diagram of the interconnection between the application circuit and the bus control circuit of the concept of the present invention: Figure 3 is the implementation of the concept of the present invention is generally connected to the application circuit and the bus A square circle between control circuits; FIG. 4 is a bus control circuit assembly for implementing the present invention. This paper size applies to China National Standard (CNS) 8-4 specifications (2 丨 〇X 297 mm)! Ϋ n III n • Install II and IIII line (please read the note on the back before filling this page) Economy Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the People's Republic of China 413989 A7 B7 Fifth, the description of the invention ($) Connection block diagram; Figure 5 is a functional block rm * diagram of the bus control circuit implementing the concept of the present invention, and Figure 6 is in accordance with the present invention Block diagram showing the connections between the first and second stages of the link buffer circuit, header buffer, and exit box multiplexer; Figure 7 is a set of ingress bus box formats implementing the concepts of the present invention Figures: Figure _8 is a set of export bus box format graphics that implements the concept of the present invention: Figure 9 is a set of export bus box grid formatting patterns that implements the concept of the present invention; Figure 10 is a view of implementing the concepts of the present invention A group of outlet slot address maps: Figure 1 is a flowchart of a method for controlling a telecommunications bus according to the concept of the present invention. A preferred embodiment of the present invention is shown in the drawings, and the same reference numerals are used to indicate the same and corresponding parts in each drawing. FIG. 1 is a block diagram of a telecommunication switch system 10 using optical fiber to implement the concepts of the present invention. In particular, the data bus interface of the present invention is used to insert a respective telecommunication component, such as a module system designed by a group of the respective components of the telecommunication switch system 10. The data bus interface of the present invention is also used in or in addition to other telecommunications components that interface to the data bus. The optical fiber telecommunication switch system 10 includes a switch 12 connected to an optical fiber connection unit (optical terminator) 14 and a common controller 16. Optical telecommunication data stream, for example, one or more sets of bit tandem data 'bit tandem data', or string '6 This paper size adopts China National Standard (CNS) A4 specification (210X 297 mm) I II 1 ^ II line 11 (please read the notes on the back before filling this page) Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China A7 B7 V. Invention Description U) Column data frame flow • Via one or more sets of fiber guides 8 is received at the optical fiber connection unit 14. These telecommunication data streams are converted into electrical signals using the optical fiber connection unit 14 and transmitted to the switch 12 for switching between data channels. Switch 12 can switch data channels of any suitable size, such as DSO, DS1, DS3, or other suitable channels. Further, any data stream may include one or more groups of data channels with appropriate formats, such as DSO, DS, DS3, or other appropriate channels. The common controller 16 receives control data from the optical fiber connection unit 14 and the switch 12 and transmits the control data there. The switch 12 is a group of telecommunication switches having M input channels and N output channels, where M and N are integers. The switch 12 receives telecommunication data in any one of the M input channels and transmits the telecommunication data to any one of the k channels of output. Switch 12, as shown in Figure 1, is a group of digital switches, but it can also be a group of analog switches. Switch 12 may include, for example, a Megahub 600E digital telecommunications switch manufactured by DSC Communications of Luzhou Preno. Switch 12 includes a matrix data multiplexer circuit (MDM) 22, a matrix control channel confirmation processor (PVP) 24. A message transfer node 20 of a line relay management circuit (LTM) 26, a management circuit (ADMIN) 28, a timing generator circuit (TG) 30, and an Ethernet circuit (ENC) 32. The matrix data multiplexer circuit 22 is further coupled to a matrix control channel validation processor 24 and a timing generator circuit 30. The matrix data multiplexer circuit 22 is a set of interface circuits that can be used to couple data channels between the optical fiber connection unit 14 and a switching matrix (not shown) of the switch 12. In particular, the matrix data multiplexer circuit 22 provides a DS0 data interface. Matrix data multiplexer circuit 22 emits light from a 10-bit data channel operating at a frequency of 16.3 84 MHz HZ ---------------- t ------ ^ (Please Please read the notes on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 413989 A7 __ ^ _ B7_ V. Description of the Invention (Γ) The fiber connection unit 14 receives 2,048 DSO data channels. These DSO data channels are then transmitted to the M input port of the switch matrix of switch 12. The control commands received at the switch I2 from the common controller 16 are used to determine the appropriate connection between the switch matrix M input port and N output port. After the connection is formed, the DSO data channel is transmitted via the switch matrix. The DSO data channel received at the matrix data multiplexer circuit 22 from the N output port of the switch matrix is then transmitted back to the fiber connection unit 14 »Matrix control channel confirmation processor 24 is coupled to the fiber optic connection unit 14 and to the message transfer node 20 »matrix control channel confirmation processor 24 is a set of switch matrix management and control components that handles matrix channel low-level fault detection and fault isolation data. The line relay management circuit 26 is coupled to the optical fiber connection unit 14 and the message carrying node 20. The line trunk management circuit 26 is a set of switching matrix control components which receives and transmits data about the call processing function of the optical fiber connection unit I4. The timing generator circuit 30 is coupled to the matrix data multiplexer circuit 22 and a common controller. The timing generator circuit 30 is a set of switch timing circuits that receives timing data from an external source, such as an optical fiber connection unit I4. The timing data is input to the switch 12 components. The Ethernet circuit 32 is coupled to the message carrying node 20 and the common controller 16. The Ethernet circuit 32 is a set of data communication interfaces, and transmits data between the message transport node 20 and the common controller 16. The optical fiber connection unit 14 includes an optical interface circuit (〇TM) 40, an STSM circuit (STSM) 42, a bus control circuit (BCM) 44, and a matrix interface circuit_8 This paper is sized to the Chinese National Standard (CNS) A4 (210X297) (%) I—n '< —Order nII, line (please read the precautions on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 413989 A7 ______B7_. 5. Description of the Invention u) (MTXI ) 46 'Tone identification circuit (TONE) 48, and high-speed line relay processor circuit (LTP) 50 »The fiber connection unit 14 receives digitally encoded optical data from the fiber guide 18, and performs the data received from the fiber guide 8 Stream broadcast switching, transmitting synchronous transmission mode (STM) telecommunications data to the matrix data multiplexer circuit 22 and matrix control channel confirmation register 24 for switching via the switching matrix of switch 12, and receiving switched telecommunications from switch 12 The information is fed to the fiber guide 18. The optical interface circuit 40 may terminate optical signals, such as OCN3, connected to a public switched network (PSN). The optical interface circuit 40 receives digitally encoded optical telecommunication data from the optical fiber guide 18 and converts the optical signal into an electrical signal, for example, a digital signal having an STS-I-P data format for transmission to other components of the optical fiber connection unit 14. The optical interface circuit 40 is coupled to the fiber guide 18 and the STSM circuit 42. The optical interface circuit 40 may include a set of a single circuit card having a plug-in connector (not shown) to allow the circuit card to be easily installed in the other component circuit card housing containing the optical fiber connection unit 14. In addition, the optical interface circuit 40 may include two or more sets of circuit cards | or separate components on one or more sets of circuit cards. The application circuit is generally any telecommunications data transmission system component that is coupled to the bus control circuit 44. Each application circuit may include a single circuit card with a plug-in connector (not shown) to be easily installed in a rack containing the optical fiber connection unit 14 " In addition * each application circuit may include multiple sets of circuit cards, or a single The separate components above the circuit card. As shown in Figure 1, the STSM circuit 42 is configured to electrically from the optical interface. This paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 mm) — -H nnn I • Installation I II Order III — IIII. (Please read the note on the back before filling in this page) 413989 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (7) Route 40 receives the data and transmits the data to the Office. This information may include telecommunication information in synchronous transmission mode. For example, the STSM circuit 42 may receive a single STS-1-P data channel containing 672 data channels composed of payload data composed of DS0, where each DS0 data channel is a continuous data stream equal to 6-7 000 bits per second. The STS-1-P data format also includes management, control, and routing data in the commercial standard STS-1 data format, plus additional proprietary management, control, and routing data. Management data, control data, and routing data are used to separate the DS0 data channels within the STS-1-P data channels, perform channel confirmation, perform device diagnostic monitoring, and other appropriate functions. The STSM circuit 42 can also receive asynchronous transmission mode (ATM) telecommunications data, such as data transmitted as an iMPAX packet layer data packet or other appropriate data format. iM PAX Envelope Data Packet is a proprietary 512-bit data format * which contains 4-bit payload type identification data, a 76-bit header section, a 424-bit payload section ', and an S-bit Control record inspection section. Asynchronous transfer mode data can be transmitted as a single stream of fixed-bit format data frames containing additional streams. For the given data stream, the number of transmitted data frames per second can be changed for asynchronous transmission mode data in order to accommodate fluctuations in the amount of data in each set of data streams and the number of transmitted data streams. The bus control circuit 44 may be coupled to other application circuits having appropriate functions, such as a matrix interface circuit 46, a tone recognition circuit 48, and a high-speed line relay processor circuit 50. All application circuits transmit data to the bus control circuit 44 via the ingress bus 60 and receive data from the bus control circuit 44 via the egress bus 62. These application circuits also include a 10-sheet paper that applies to China National Building Standard (CNS) A4 specifications (210X297 mm) ---------- install-(Please read the precautions on the back before filling in this Page), ιτ printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 413989 A7 B7 V. Description of the invention (s) Group module bus interface circuit (not shown) "The module bus interface circuit receives data from the application circuit And it is converted into a predetermined format for transmission via the ingress bus 60. The module bus interface circuit also receives the data in a predetermined format via the outlet bus 62 and converts it into a format usable by the application circuit related to the bus interface circuit. The bus control circuit 44 enters the alpha bus 60 from the application circuit. Receive telecommunications data in a predetermined format, multiplex the data into a single broadcast data stream in a predetermined format, and transmit the broadcast data stream via an exit bus 62. In this way, the bus control circuit 44 also operates like a set of broadcast switching elements. Each application circuit receives a broadcast data stream containing data from other application circuits, and can process the selected data in an appropriate manner. For example, the STSM circuit 42 can input data back to the optical interface circuit 40 for transmission over the fiber guide 18 to the network. The bus control circuit 44 may include a set of single circuit cards with plug-in connectors (not shown) to be easily used in a rack containing the optical fiber connection unit 14. In addition, the bus control circuit 44 may include multiple sets of circuit cards, or separate components on a single circuit card. The matrix interface circuit 46 provides an agreement between the optical fiber connection unit M and the switch 2 and a transport format conversion. The matrix interface circuit 46 is a set of application circuits that selects a required data channel from the broadcast data stream transmitted by the bus control circuit 44 and reformats and transmits the data to the switch 12. Matrix interface circuit 46 is coupled to bus control circuit 44 'matrix data multiplexer circuit 22, and matrix control channel validation processor 24. The matrix interface circuit 46 converts the data format of the broadcast data stream received from the bus control circuit 44 and the switch 12 to enter and can be matched with the switch 2 and the bus control circuit 44 respectively. 11 This paper size applies to the Chinese National Standard (CNS) Α4 Specification (210X297mm) I- I t —II Batch—Order—I * — Silver (please wash and read the notes on the back and fill in this page) A7 413989 B7 V. Data format of the description of the invention (f) · The matrix interface circuit 46 may include a single circuit card with a plug-in connector (not shown) so as to be easily used in a rack including the optical fiber connection unit I4. In addition, the matrix interface circuit 46 may include multiple sets of circuit cards or separate components on a single circuit card. The tone identification circuit 48 is a set of application circuits which is coupled to the bus control circuit 44 and performs a tone identification function of the optical fiber connection unit 14. A pair of tone identification circuits 48 is required for each of the 201 6-group matrix ports of switch I2. The tone recognition circuit 48 interfaces with the broadcast data stream and detects the data of the keyboard tone on each DS0 channel containing the broadcast data stream, indicating that it can reach a maximum of 2016 DS0 data channels. Tone identification circuit 48 has an array of digital signal processor elements (not shown) that can be configured to provide tone detection and generation. The tone identification circuit 48 may include a single circuit card with a plug-in connector (not shown) so as to be easily used in a rack including the optically woven connection unit 14. In addition, the tone recognition circuit 48 may include multiple sets of circuit cards, or separate components on a single circuit card. The high-speed line relay processor circuit 50 is the main lattice controller of all circuit cards in the fiber connection unit 14 and provides an interface between the fiber connection unit 14 and the switch 12 = The high-speed line relay processor circuit 50 contains a set of microprocessing And a set of communication interfaces to the line relay management circuit 26. The high-speed line relay processor circuit 50 may include a single circuit card with a plug-in connector (not shown) so as to be easily used in a rack including the optical fiber connection unit 14. In addition, the high-speed line relay processor Circuit 50 may include multiple sets of circuit cards | or separate components on a single circuit card. 12 This paper size applies to China National Standard (CNS) A4 (2 丨 0 X 297 mm) II 11 line {Please read the note on the back before filling this page) Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, India Poly A7 413989 B7_ V. Description of the Invention (/ 〇) The entrance bus 60 is a group of data buses, which carries a data stream with a predetermined bit structure and a predetermined frequency from a group of application circuits to the bus control circuit 44. For example, each incoming alpha bus 60 may include an 8-bit data stream operating at a frequency of 25.92 MHz. Other bit structures and frequencies can be used as appropriate. Outlet bus 62—a group of data buses • It carries a data stream with a predetermined bit structure and a predetermined frequency from a group of application circuits to the bus control circuit 44 «For example, each of the inlet buses 62 may include operating at a frequency of 5 1.64MHZ 16-bit data stream. Other bit structures and frequencies can be used as appropriate. The common controller 16 is coupled to the switch 12 and the fiber connection unit 14. The common controller 16 is a group of processors that receives management, control, and routing information from the switch 12 and the fiber connection unit 14 and generates management, control, and routing information that schedules the operation of the switch 12 and the fiber connection unit 14 The common controller 16 can additionally fit in the switch 12 or the optical fiber connection unit 14. In operation, telecommunication data from the network is input via the fiber guide 18 and received by the fiber connection unit 14. This telecommunication data is then converted into electrical signals, such as 672 DS0 data channels, and is transmitted from the optical interface circuit 40 via the STSM circuit 42 and via the entry bus 60 to the bus control circuit 44. The bus control circuit 44 multiplexes the data received from each application circuit into a set of single broadcast data streams and transmits the broadcast data streams via each of the egress buses 62. The broadcast data stream that has been lost is received by the matrix interface circuit 46, which in turn transmits the data to the switch 12. The switch 12 switches between the respective 672 groups of DSO data channels, for example, by using the order of reconstructing the 672 groups of DS0 data channels. The 672 DS0 data channels are then transmitted back to the matrix interface circuit 46. _____ 13 This paper size applies to the Chinese national standard (CNS > A4 size (210 X 297 mm) I, binding silver (please read the precautions on the back before filling this page)) Central Standards Bureau of the Ministry of Economic Affairs Cooperative Du printed by the Central Consumers Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives 413989 A7 __B7_ V. Description of the Invention The matrix interface circuit 46 transmits the 672 DS0 data channels to the bus control circuit 44 via the entry bus 60 in a predetermined format. The bus control circuit 44 then generates a broadcast data stream, which includes 672 DS0 data channels that are switched via the switch 12. The broadcast data stream is received at the STSM circuit 42 for transmission via the optical interface circuit 40 and then through the fiber optic director 6 The broadcast data can also or alternatively be transmitted to the matrix interface circuit 46, the tone recognition circuit 48, the high-speed line relay processor circuit 50, or other appropriate circuits for appropriate data processing. Figure 2 is shown in STSM Connection diagram of the connection between the circuit 42 and the bus control circuit 44 of the bus control system 70. Appropriate number of application circuits' such as STSM Circuits 42 may be coupled to the multiplexer 78 (MUX) of the bus control circuit 44 via the inlet bus 60. Each STSM circuit 42 transmits a single data stream of encoded data to the bus via a set of related inlet buses 60 The control circuit 4 centers a single data stream of the encoded data received by the multiplexer 78 from each of the ingress buses 60 and is then combined by the bus control circuit 44 into a set of broadcast data streams. The broadcast data stream is transmitted from the egress bus 62 through The multiplexer 78 is transmitted to the STSM circuit 42 and other application circuits. The broadcast data stream contains some or all of the data from each single data stream, and its encoded format allows any part of the data to be identified and placed on the broadcast Within the data stream. Planes 72 and 74 of the bus control system 70 may include components such as STSM circuit 42, inlet bus 60 'bus control circuit 44, and exit bus 62. The buses of plane 72 and 74 The control circuit 44 is coupled together via a high-speed link 76, which is a high-frequency data stream, for example, in accordance with the Chinese paper standard (CNS) A4 in 14 paper sizes. (210X297 public address) (Please read the notes on the back before filling out this page)-Binding and printing Printed by the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Shellfish Consumer Cooperative 413989 A7 B7 V. Invention Description (U) 5 1.84MHZ Operation 16- Bit-parallel data channel. The broadcast data stream received from plane 74 via plane rate key 76 on plane 72 may be partially or wholly multiplexed into slave plane 72 in response to management, control, and routing data. The broadcast data stream input to the plane 74. The broadcast data stream received on the plane from the plane 72 via the high-rate link 76 may also be multiplexed in part or in whole into a broadcast data stream transmitted from the plane 74 to the plane 72. Plane 72 and plane 74 may be configured as completely redundant physical transport layers while carrying an excess data stream that receives telecommunication data via fiber optic guide 18. In this configuration, as long as a complete set of data transmission channels remains available, the multiple failures of the components in the redundant plane 72 and plane 74 will not interrupt the data transmission. Plane 72 and plane 74 may be additionally configured to carry unique data. The independent transport layer of telecommunication data " The respective STSM circuits 42 of the plane 72 or plane 74 can also be configured in redundant format, so that one or more groups of STSM circuits 42 are redundant in the plane 72 and plane 74. The bus control circuit 44 of the plane 72 receives a plurality of single data streams of a predetermined data format from each ingress bus 60 and multiplexes the single data stream into a group of first broadcast data streams having the predetermined data format. The bus control circuit 44 of the plane 72 then transmits the first broadcast data stream to the application circuit 42 via the outlet bus 62. The bus control circuit 44 of the plane 72 also transmits the first broadcast data stream to the high-speed link 76 to The bus control circuit 44 of the plane 74 »The plane bus control circuit 44 receives a plurality of single data streams including synchronous transmission mode data and asynchronous transmission mode data from each of the entry buses 60 and the first broadcast data stream, and This single data stream and 15 paper sizes are applicable to China National Standard (CNS) A4 specifications (2I0X297 mm) --------- ά ------ tr ------ line (1 * Please read the notes on the back before filling in this page) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 413989 A7 B7 V. Invention Description (〇) Part or all of the first broadcast data stream is multiplexed into a group The second broadcast data stream. The bus control circuit 44 of the plane 74 then transmits the second broadcast data stream to the STSM circuit 42 via the exit bus 62. The bus control circuit 44 of the plane 74 also transmits the second broadcast data stream via the high-speed link 76. Bus control circuit 44 to plane 72. The bus control circuit 44 of the plane 72 receives the second broadcast data stream, and multiplexes part or all of the data from the second broadcast data stream into the first broadcast data stream. Fig. 3 is a connection diagram of the bus control system 90 established according to the present invention. The bus control system 90 includes a plane 72 and a plane 74. The plane 74 contains an STS Μ circuit 42, an optical interface circuit 40, a matrix interface circuit 46 'tone identification circuit 48, and a high-speed line relay processor circuit 50, each of which is coupled to the bus by an inlet bus 60 and an outlet bus 62 as shown. The bus control circuit 44 »plane 72 contains an echo canceller circuit (ECHO) 92, which is coupled to the bus control circuit 44 by the inlet bus 60 and the outlet bus 62» the bus control circuit 44 of the plane 72 and the plane 74 is high-speed Link 76 is coupled together "STSM circuit 42, matrix interface circuit 46 'tone identification circuit 48, and high-speed line relay processor circuit 50 are application circuits that transmit data in a predetermined format via the ingress bus 60 and via the egress bus 62 receiving information. This data can include isochronous transfer mode data and asynchronous transfer mode data, such as iMPAX packet layer data packets. Each application circuit can include a set of module bus interface circuits (not shown). The module bus interface circuit receives data from the application circuit and converts it into a predetermined format for transmission via the inlet bus 60. The module bus interface circuit also receives data in a predetermined format via the outlet bus 62 and converts it into the relevant bus interface circuit. • 16 This paper size applies the Chinese National Standard (CNS) A4 specification (2ϋ297 mm) --------- Raid ----- 1T ------ Φ. (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 413989 A7 __B7___ 5. Description of the Invention (/ 4) Format used by the application circuit. The optical interface circuit 40 receives a broadcast data stream from the egress bus 62 and transmits a set of data streams to the bus control circuit 44 via the ingress bus 60. The data received and transmitted by the optical interface circuit generally includes only the asynchronous transmission mode data in the form of an iMPAX packet layer data packet, and they are used to carry control data and control commands between the 14 components of the optical fiber connection unit. In the synchronous transmission mode, data can also be received and transmitted by the optical interface circuit 40 via the ingress bus 60 and the egress bus 62. The echo canceller circuit 92 includes one or more sets of digital signal processors (not shown), which can be used to remove the echo signals from the respective DS0 data channels included in the broadcast data stream. The echo canceler circuit 92 may include a single circuit card with a plug-in connector (not shown) to allow the circuit card to be easily installed in a compartment containing the other component circuit cards of the optical fiber connection unit 14. In addition, the echo canceler The processor circuit 92 may include two or more sets of circuit cards, or one or more sets of separate components on a single circuit card. The bus control circuit 44 of the plane 72 and the plane 74 of the bus control system 90 receives a single data stream from each entry bus 60 and multiplexes the data to form a first broadcast data stream and a second broadcast data stream, respectively. The first and second broadcast data streams are then transmitted to the application circuit via the speed key 76 via the egress bus 62, and to the bus control circuits 44 on different planes. In operation, the data stream is received in the optical interface circuit 40 and transmitted to the STSM circuit 42 for sequential transmission to the bus control circuit 44 via the ingress bus 60. 44. These telecommunication data streams are then multiplexed by the bus control circuit 44 and transmitted as a single broadcast data stream via the exit bus 62 and the high-rate link 76. This paper size applies the Chinese National Standard (CNS) A4 specification (2! 0X297). (Li) ----: ----------------- 1T ------ ^ (Please read the notes on the back before filling in this page) 413989 Employee Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Print A7 B7 V. Description of the invention (/ 5 ") Transmission to other application circuits " For example, the broadcast data stream of the bus control circuit 44 of the plane 72 can be received in the tone recognition circuit 48. The tone identification circuit 48 processes the respective D SO data channels included in the broadcast data stream to identify the dual-tone multi-frequency (DTNF) tone signals contained in the respective DSO data channels. Alternatively or in addition, the broadcast data stream may be received at The matrix interface circuit 46 is transmitted to the switch 12 for switching between the DS0 data channels through the matrix structure of the switch 12. The first broadcast data stream can also be transmitted to the echo canceller circuit 92 via the high-speed link 76 and sequentially multiplexed by the bus control circuit 44 of the plane 74 into the second broadcast data stream for processing to cancel the echo signal. . Fig. 4 is a block diagram of the bus control circuit 44 of the bus control system 70 and the bus control system 90. The bus control circuit 44 includes an inlet interface circuit (ING) 100 | which is coupled to a plurality of inlet buses 60. The entrance interface circuit 100 includes a data buffer (not shown) for storing asynchronous transmission mode data and a bypass connection circuit for picking up synchronous synchronous feed mode data. • Data buffer and bypass connection circuit The output is coupled to an input of a multiplexer circuit (MUX) 106. The bus interface and sequential circuit (BIF) 104 are also coupled to the entry interface circuit 00. The bus interface and timing circuit 104 is a set of module interface circuits that are used to receive broadcast data streams from the egress bus 62 and transmit a single data stream via the ingress bus 60. As shown in Figure 4, the bus interface and timing circuit 104 is used to receive the broadcast data stream from the exit interface circuit 102 and input it to the entry interface circuit 100. The control data received from the on-board controller circuit 114 is Use to selectively control the data, which is when exported • 18 paper sizes are applicable to China National Standard (CMS) A4 (210X297 mm) ---------. Packing-(Please read the back (Please fill in this page again)
.1T 線 經濟部中央標準局貝工消費合作社印製 413989 A7 _____B7_ 五、發明説明（/&) 匯流排62上面資料信號頻帶寬度大於入口匯流排60上面資 料信號之頻帶寬度時被傳輸至入口界面電路100。 多工器電路106包含匯流排槽格多工器電路 (BSM)l 12，其耦合至鏈路緩衝器電路（LBC)l 16、板上控制 器電路（OBC)114、和雙埠緩衝器電路（DPB)130。接收自入 口界面電路100和雙埠緩衝器電路Π0之資料反應於接收自 板上控制器電路114的控制資料而被匯流排槽格多工器電路 11 2多工化。經由入口匯流排60和出口匯流排62傳輸的資料 包含多數個匯流排槽格，其中各匯流排槽格是包含同步傳送 模式資料封、非同步傳送模式資料封、或者閒散資料封之64 位元組資料格式。各資料封包含控制資料，例如封包形式指 示器以及控制記錄檢査資料，它們被入口界面電路100或者 出口界面電路1 08使用於診斷I例如證實框對齊、檢測控制 記錄檢查錯誤、檢測框同步/存在錯誤、檢測封包形式指示 器錯誤'或者其他的適當診斷目的- 板上控制器電路114是一組模組控制電路，其被安裝於 匯流排控制器電路44之相同電路卡上面，或者於附帶子電路 卡上面。板上控制器電路114被耦合至匯流排界面電路104、 仲裁器電路110、多工器電路〖06、出口界面108、以及匯流 排控制器電路44的其他組件。板上控制器電路Π 4從仲裁器 電路（ARB)丨1 〇接收控制資料並且傳输控制資料至該處，它 被使用以提供控制資料至匯流排槽格多工器電路Π2以及出 口框多工器電路（EFM)l 1 8 · 仲裁器電路被使用以程式規劃地安置在入口界面電 19 本紙張尺度適用中國國家標準（CNS)"^4規格（21〇X297公釐） ----------坤衣------ΐτ------m, (請先聞讀背面之注意事項再填寫本頁) 413989 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（7) 路100從多數個入口匯流排60所接收的各資料流之頻帶寬 度。例如，各入口匯流排60可傳輸以25.92MHZ頻率操作的 8-位元資料通道，而其有效資料頻帶寬度大約是每秒200百 萬位元。出口匯流排62可傳輸以51.84MHZ頻率操作之16-位元資料通道，而其有效資料頻帶寬度大約是每秒800百萬 位元。當從所有入口匯流排60接收的資料大於每秒800百萬 位元時，接收自仲裁器電路11〇的控制資料被使用以安置在 入口界面電路100所接收各入口匯流排的資料頻帶寬度。 雙埠緩衝器電路130經由高速鏈路76,那是以51. 84MHZ 操作的1 6·位元平行資料通道，從匯流排控制電路44接收廣 播資料流"高速鏈路接收器電路（H SLR) 13 4被耦合至髙速鏈 路76並且傳送廣播資料流至出口改編器電路（ERC)132,其 轉換廣播資料通道成爲以25.92MHZ頻率操作的兩組8-位元 的平行資料通道。被轉換的廣播資料流接著被雙埠緩衝器電 路13 0提供至多工器電路112»仲裁器電路110同時也控制雙 埠緩衝器電路130所提供廣播資料流之頻帶寬度的安置》 在多工器電路Π 2接收的資料反應於從仲裁器電路110 所接收的控制資料利用選擇地儲存該資料於四組鏈路緩衝 器電路11 6之一組而被多工化。來自鏈路緩衝器電路丨16之資 料接著與出口檔頭資料被出口框多工器11 8多工化以形成一 組廣播資料流。 該廣播資料流被傳輸至出口界面（EIF) 108,其包含出口 處理器電路（EPC)120、廣播電路（BX)122、以及廣播界面電 路（BXI) 124。該廣播流從廣播電路122被傅輸至出口改編器 20 (請先閲讀背面之注意事項再填寫本頁) -裝1 訂 绿 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐) 經濟部中央標準局員工消費合作社印製 413989 A7 B7 五、發明説明（a) 電路132以便傳輸至高速度傳輸器電路（HST) 136和高速鏈 路76。廣播界面電路12 4傳輸16組多餘的廣播資料流至出口 匯流排驅動器102,其提昇廣播資料流信號強度以便經由出 口匯流排62傳輸》 操作時，多數個單一資料流從入口匯流排60被接收於匯 流排控制電路44之入口界面電路1〇〇。管理和控制資料被抽 取並且在該管理和控制資料上面達成診斷資料分析》非同步 傳送模式資料暫時地被儲存於資料緩衝器中，並且同步傅送 模式資料直接地被傳輸至匯流排槽格多工器112。此外，接 收自一組或者多組其他的匯流排控制電路44的廣播資料流 資料同時也被傳輸至匯流排槽格多工器1丨2。來自入口界面 電路100中資料緩衝器的非同步傳送模式資料依據仲裁器電 略110所決定的轉動優先順序被傳輸至匯流排槽格多工器電 路 1 12。 以此方式，可從STSM電路42接收資料通道，經由匯流 排控制電路44傳輸，並且引導至其他的應用電路以便進行資 料處理，例如切換、回音消除、音調檢測、或者其他適當的 資料處理。DS0資料可接著被引導回至匯流排控制電路44 · 並且最後被傳輸回至STSM電路42。接收自任何所給予應用 電路的資料頻帶寬度可被控制，並且雖然與其他的資料組合' 但仍然可在該資料上面達成資料處理而不會妨礙錯誤被檢 測或者干擾錯誤檢測和診斷功能。 匯流排槽格多工器電路丨12依據板上控制器電路11 4所 規劃反應於接收自仲裁器電路H0的控制資料而儲存多工化 21 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------^------ΐτ------^ (請先Μ讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印聚 413989 A7 ___；_B7 五、發明説明（θ) 資料於鏈路資料緩衝器電路116中》鏈路資料緩衝器電路116 接著傳送資料至出口框多工器電路118，其將來自鏈路資料 緩衝器電路1U之資料與出口槍頭資料組合以形成一組廣播 資料流。該廣播資料流接著被高速度鏈路76傳輸至一組或者 多組匯流排控制電路44，並且利用出口匯流排驅動器電路 102至出口匯流排62。 第5圖是依據本發明展示在入口匯流排60、入口界面電 路100、和多工器電路106之間的連接之方塊圖。各入口匯流 排60被耦合至入口資料緩衝器電路（IDB)150,它是選擇地儲 存並且傳輸資料之一組資料儲存元件。在入口界面電路1 00 所接收來自入口匯流排60之單一資料流中的非同步傳送模 式資料暫時地儲存在對應的入口資料緩衝器電路150中以便 依序地傳輸至匯流排槽格多工器電路112» 來自各單一資料流的同步傳送模式資料被傳輸至匯流 排槽格多工器電路112。來自廣播資料流之同步傳送模式資 料被接收於雙埠緩衝器電路130並且直接地被傳輸至匯流排 槽格多〇：器電路11 2。各匯流排槽格多工器電路11 2是選擇地 儲存被接收資料於相關的鏈路緩衝器電路116中的一組34: 1 多工器。鏈路緩衝器電路11 6的輸出是一組16-位元的平行資 料流。 操作時，依據從各應用卡傳輸至匯流排控制電路44之 iMPAX封裝層資料封引動信號，非同步傳送模式資料被儲存 於入口資料緩衝器電路150中直至非同步傳送模式資料被選 擇傳輸爲止。該iMPAX封裝層資料封引動信號可經由特定資 本紙張尺度適用中國國家標準（CNS ) A4現格（2! 0 X 297公釐） ^iT价 (請先閱讀背面之注意事項再填寫本頁) 413989 經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明（α) 料線被引動，或者可被包含於一組或者多組資料匯流排之預 定時間槽內》 各入口資料緩衝器電路150具有預定的資料儲存容量並 且當傅輸目前儲存資料時儲存新的非同步傳送模式資料。這 非同步傳送模式資料隨著同步傳送模式資料被傳輸至匯流 排槽格多工器電路112»供多工器112選擇的控制資料是導自 利用仲裁器電路Π 0產生的控制資料。儲存多工化資料於鏈 路緩衝器電路Π6中是被控制以便進行同步傳送模式資料和 非同步傳送模式資料之廣播切換。 第6圖是依據本發明展示在鏈路緩衝器電路11 6、檔頭緩 衝器電路152、和出口框多工器第一級11 8Α和第二級11_8Β之 間的連接之方塊圖。鏈路資料緩衝器電路Π 6被耦合至出口 框多工器第一級Π8Α·它將來自四組鏈路資料緩衝器電路 116的資料流多工化進入一組中間資料流。儲存在檔頭緩衝 器電路152中的框檔頭資料接著被出口框多工器第二級 1 1 8Β利用中間資料通道多工化以形成廣播資料通道·廣播 資料通道接著被傳輸至出口界面電路108。 第7圖是實施本發明觀念之一組入口匯流排框格式160 的圖形經由入口匯流排60傳輸的資料可被編碼爲入口匯流 排框格式160之格式，或者其他適當的格式。 入口匯流排框格式160具有丨25微秒週期，並且具有包含 32位元組資料之框檔頭塊組8·位元組的資料墊塊被包含 以協助時脈同步。入口匯流排框格式160同時也包含50組64-位元組匯流排槽格。各匯流排槽格可被傳輸於以25.92ΜΗΖ 23 本紙張尺度適用中國國家標準（CNS ) Α4规格（2Ι0Χ：297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝_ 訂 413989 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（"） 頻率操作的一組8-位元寬資料流上面，以提供大約2〇〇Mb/s 的頻帶寬度。也可使用其他適當的資料流格式和頻率，例如 具有在1和128之間任何整數値寬度之資料流，具有較多或者 較少位元組數目之較多或者較少匯流排槽格，以及在，okHz 和200MHZ之間以1Hz增量之操作頻率。 第8圖是實施本發明觀念的一組出口匯流排框格式170 之圖形。經由出口匯流排62傳輸的資料可被編碼爲出口匯流 排框格式170之格式，或者其他適當的格式》 出口匯流排框格式170具有125微秒週期，並且具有包含 32位元組資料之框檔頭塊。一組8-位元組的資料墊塊被包含 以協肋時脈同步出口匯流排框格式170同時也包含2〇2組 64-位元組匯流排槽格》各匯流排槽格可被傳輸於以 5 1.84MHZ頻率操作的一組16-位元寬資料流上面，以提供大 約800Mb/s的頻帶寬度。也可使用其他適當的資料流格式和 頻率，例如具有在1和1 28之間任何整數値寬度之資料流，具 有較多或者較少位元組數目之較多或者較少匯流排槽格，以 及在10kHz和200MHZ之間以1Hz增量之操作頻率》 第9圖是實施本發明觀念之一組出口匯流排槽格充塡格 式18 0的圖形。出口匯流排槽格充塡格式180展示一種順序， 其中資料從多工器電路106之四組鏈路資料緩衝器電路116 以出口匯流排框格式170經由出口匯流排62被傳輸。在32-位元組出口匯流排檔頭被傳輸之後，鏈路A傳輸包含3 2組16-位元資料封包之一組資料封，其形成一組64-位元組出口匯 流排槽格。這資料封可以是一組同步傅送模式資料封、一組 (諳先閏讀背面之注意事項再填寫本頁) —裝1 ,w 24 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部中央標準局員工消費合作社印袋 413989 A7 B7 五、發明説明（β) 非同步傅送模式資料封，例如iMP ΑΧ封裝層資料封、一組閒 置資料封、或者其他的適當的資料封。鏈路Β、鏈路C、和 鍵路D接著各傳輸32組16 -位元資料資料封。處理程序接著 重複每四組匯流排槽格直至2 0 0組出口匯流排槽格被傳輸爲 止。兩組閒置資料封接著被傳輸以完成202-位元組之出口匯 流排框格式170的有效負荷。 以此方式，來自入口匯流排框格式160之匯流排槽格資 料可被累積在四組鏈路資料緩衝器電路116中直至它們被塡 滿爲止。資料被儲存在四組鏈路資料緩衝器電路116中而使 得鏈路Α可傳輸第一組64.位元組出口匯流排槽格，然後依 順序是鏈路B、鏈路C、和鏈路D。只要各鍵路緩衝器在適當 的時間具有完全64-位元組的資料被傅輸，從丨6組入口匯流 排60之匯流排槽格所接收的資料可依適當的順序被儲存在 四組鏈路緩衝器電路M6中。因此，當鏈路A被傳輸時，如 果鏈路B已經塡滿則鏈路D可被充塡。接著，當鏈路B被傳輸 時，鏈路C和鏈路A可被充塡，以此類推》 第10圖是實施本發明觀念之一組出口槽格位址圖190的 圖形。出口槽格位址圖190可被儲存在第4圖仲裁電路110的 隨機存取記憶體中。出口槽格位址圖1 90是一組202位元組位 址圖，其包含對應各出口匯流排62之匯流排槽格的入口匯流 排60之匯流排槽格源位址。 一組出口匯流排框格式170的200組匯流排槽格依展示 順序可包含50組鏈路A資料封、50組鏈路B資料封、50組鏈 路C資料封、以及50組鏈路D資料封。將被使用以提供出口 25 本紙張尺度適用中國國家^準（CNS ) A4規格（2〖0父297公¥ ) I I I 裝 n I I i 银 (請先閲讀背面之注項再填寫本頁) 經濟部中央橾準局員工消費合作社印製 413989 A7 B7 I、發明说明（对） 槽格位址圖190的對應位置之資料封的入口匯流排60之匯流 排槽格的位址被儲存於出口槽格位址圖190中。 例如，出口匯流排槽格A1可被充塡以來自16組入口匯流 排60之第13組的匯流排槽格之同步傳送模式資料封》這入口 匯流排源的位址將被儲存在出口槽格位址圖190之A1圖位 置中。如果需要切換改變•例如儲存來自16組入口匯流排60 之第3組的iMPAX封裝層資料封於出口匯流排槽格A1中*則 新的入口匯流排源位址被儲存在出口槽格位址圖190中》仲 裁電路110接著產生適當的命令而使得四組鏈路緩衝器電路 116和出口框多工器第一級118A置放適當的入口匯流排槽 格於出口匯流排槽格A1中。 第Π圖是依據本發明觀念用以控制電信匯流排之方法 200的流程圖。方法200開始於步驟202，其中多數個入口匯 流排之匯流排槽格被接收於匯流排控制電路。這些入口匯流 排之匯流排槽格可包含同步傳送模式資料封、非同步傳送模 式資料封、以及閒置資料封。除了該等多數個入口匯流排之 匯流排槽格之外，包含來自另一匯流排控制電路和一組匯流 排界面電路之非同步傳送模式資料的出口匯流排之匯流排 槽格也可被接收》 在步驟2 04,框檔頭資料被匯流排控制電路從各入口匯 流排框格式中抽取出。該框檔頭資料可包含路由、控制、以 及其他的管理資料•它們可被板上控制器電路使用以決定入 口匯流排之匯流排槽格之出口匯流排之匯流排槽格指定。該 方法接著前進至步驟206,其中非同步傳送模式資料封被儲 26 本紙張尺度逍用中國闺家標準（CNS ) A4規格（210X297公釐） ---------,-裝------訂-----，線 (請先閱讀背面之注意事項再填寫本頁) 413989 A7 B7 五、發明説明（π ) 的資料匯流排控制器。本發明之另一優點是允許多組進入的 資料匯流排被多工化成爲單一出去的資料匯流排之資料匯 流排控制系統。 雖然許多本發明之實施例和其優點已經被詳細說明•應 該可了解本發明可有各種轉變、改變、替代、轉換、修改、 變化、和更動而不脫離所附申請專利範圍所定本發明之精神 和範疇。 ---------‘寒------ir-----1' 0 (請先閱讀背面之注意事項再填寫本頁) 經濟.外中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）.1T printed by the Central Standards Bureau of the Ministry of Economics, printed by the Shellfish Consumer Cooperative 413989 A7 _____B7_ V. Description of the Invention (&) The bandwidth of the data signal on the bus 62 is greater than the bandwidth of the data signal on the bus 60 is transmitted to the entrance Interface circuit 100. The multiplexer circuit 106 includes a bus slot multiplexer circuit (BSM) 12 which is coupled to a link buffer circuit (LBC) 116, an on-board controller circuit (OBC) 114, and a dual-port buffer circuit (DPB) 130. The data received from the interface circuit 100 and the dual-port buffer circuit Π0 are multiplexed by the bus slot multiplexer circuit 11 2 in response to the control data received from the on-board controller circuit 114. The data transmitted through the inlet bus 60 and the outlet bus 62 includes a plurality of bus slots, and each of the bus slots is a 64-bit file containing a synchronous transmission mode data cover, an asynchronous transmission mode data cover, or an idle data cover. Group profile format. Each data packet contains control data, such as a packet form indicator and control record inspection data, which are used by the entrance interface circuit 100 or the exit interface circuit 108 to diagnose I such as confirming frame alignment, detecting control record inspection errors, detecting frame synchronization / existence Error, detected packet form indicator error ', or other appropriate diagnostic purposes-On-board controller circuit 114 is a set of module control circuits that are mounted on the same circuit card as the bus controller circuit 44 or attached Above the circuit card. On-board controller circuit 114 is coupled to bus interface circuit 104, arbiter circuit 110, multiplexer circuit 06, outlet interface 108, and other components of bus controller circuit 44. The on-board controller circuit Π 4 receives control data from the arbiter circuit (ARB) 丨 1 〇 and transmits control data to it. It is used to provide control data to the bus slot multiplexer circuit Π 2 and the outlet frame. Worker circuit (EFM) l 1 8 · The arbiter circuit is used to be placed at the entrance interface in a programmatic manner. 19 This paper size applies to the Chinese National Standard (CNS) " ^ 4 specification (21〇297 mm) --- ------- Kun Yi ------ ΐτ ------ m, (Please read the precautions on the back before filling out this page) 413989 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs System V. Description of the Invention (7) The bandwidth of each data stream received by the road 100 from the plurality of ingress buses 60. For example, each ingress bus 60 can transmit an 8-bit data channel operating at a frequency of 25.92 MHz, and its effective data bandwidth is approximately 2 million bits per second. The egress bus 62 can transmit a 16-bit data channel operating at a frequency of 51.84 MHz, and its effective data bandwidth is approximately 800 million bits per second. When the data received from all the ingress buses 60 is greater than 800 million bits per second, the control data received from the arbiter circuit 110 is used to be placed in the data bandwidth of each ingress bus received by the ingress interface circuit 100. The dual-port buffer circuit 130 receives the broadcast data stream from the bus control circuit 44 via the high-speed link 76, which is a 16-bit parallel data channel operating at 51.84MHZ " high-speed link receiver circuit (H SLR 134 is coupled to the high-speed link 76 and transmits the broadcast data stream to the exit adaptor circuit (ERC) 132, which converts the broadcast data channel into two sets of 8-bit parallel data channels operating at a frequency of 25.92MHZ. The converted broadcast data stream is then provided to the multiplexer circuit 112 by the dual-port buffer circuit 130. The arbiter circuit 110 also controls the placement of the bandwidth of the broadcast data stream provided by the dual-port buffer circuit 130. The data received by the circuit UI 2 is multiplexed in response to the control data received from the arbiter circuit 110 by selectively storing the data in one of the four sets of link buffer circuits 116. The data from the link buffer circuit 16 is then multiplexed with the export header data by the export frame multiplexer 118 to form a set of broadcast data streams. The broadcast data stream is transmitted to an exit interface (EIF) 108, which includes an exit processor circuit (EPC) 120, a broadcast circuit (BX) 122, and a broadcast interface circuit (BXI) 124. The broadcast stream is transmitted from the broadcast circuit 122 to the export adaptor 20 (please read the precautions on the back before filling this page)-1 set of green paper size applicable to China National Standard (CNS) A4 specifications (2 丨 0X297) (%) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 413989 A7 B7 5. Description of the Invention (a) Circuit 132 for transmission to High Speed Transmitter Circuit (HST) 136 and High Speed Link 76. The broadcast interface circuit 12 transmits 16 sets of redundant broadcast data streams to the output bus driver 102, which enhances the signal strength of the broadcast data stream for transmission via the output bus 62. During operation, most single data streams are received from the input bus 60 The entrance interface circuit 100 at the bus control circuit 44. Management and control data is extracted and diagnostic data analysis is achieved on the management and control data. Asynchronous transfer mode data is temporarily stored in the data buffer, and synchronous feed mode data is directly transmitted to the bus slot.工 器 112。 Worker 112. In addition, the broadcast data received from one or more other bus control circuits 44 is also transmitted to the bus slot multiplexer 1 丨 2 at the same time. Asynchronous transfer mode data from the data buffer in the entry interface circuit 100 is transmitted to the bus slot multiplexer circuit 1 12 according to the rotation priority determined by the arbiter circuit 110. In this way, the data channel can be received from the STSM circuit 42, transmitted via the bus control circuit 44, and directed to other application circuits for data processing, such as switching, echo cancellation, tone detection, or other appropriate data processing. DS0 data can then be directed back to the bus control circuit 44 and finally transmitted back to the STSM circuit 42. The bandwidth of the data received from any given application circuit can be controlled, and although combined with other data ', data processing can still be achieved on the data without interfering with error detection or interfering with error detection and diagnostic functions. Bus-slot multiplexer circuit 丨 12 According to the plan of the controller circuit 11 4 on the board, the multiplexing is stored in response to the control data received from the arbiter circuit H0. 21 This paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm) --------- ^ ------ ΐτ ------ ^ (Please read the notes on the back before filling out this page) Staff Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Yinju 413989 A7 ___; _B7 V. Description of the invention (θ) The data is in the link data buffer circuit 116. The link data buffer circuit 116 then sends the data to the exit frame multiplexer circuit 118, which will come from the link data. The data of the buffer circuit 1U is combined with the data of the exit gun head to form a group of broadcast data streams. The broadcast data stream is then transmitted to the one or more sets of bus control circuits 44 by the high-speed link 76, and uses the exit bus driver circuit 102 to the exit bus 62. Fig. 5 is a block diagram showing the connections between the inlet bus 60, the inlet interface circuit 100, and the multiplexer circuit 106 according to the present invention. Each ingress bus 60 is coupled to an ingress data buffer circuit (IDB) 150, which is a set of data storage elements that selectively stores and transmits data. Asynchronous transfer mode data in a single data stream received by the ingress interface circuit 100 from the ingress bus 60 is temporarily stored in the corresponding ingress data buffer circuit 150 for sequential transmission to the bus slot multiplexer Circuit 112 »The synchronous transmission mode data from each single data stream is transmitted to the bus slot multiplexer circuit 112. The synchronous transmission mode data from the broadcast data stream is received in the dual-port buffer circuit 130 and directly transmitted to the bus slot. Each busbar slot multiplexer circuit 112 is a group of 34: 1 multiplexers which selectively stores received data in the associated link buffer circuit 116. The output of the link buffer circuit 116 is a set of 16-bit parallel data streams. During operation, according to the iMPAX package layer data seal trigger signal transmitted from each application card to the bus control circuit 44, the asynchronous transfer mode data is stored in the entry data buffer circuit 150 until the asynchronous transfer mode data is selected for transmission. The iMPAX encapsulation layer data envelope trigger signal can apply Chinese National Standard (CNS) A4 standard (2! 0 X 297 mm) via specific capital paper standards. ^ IT price (please read the precautions on the back before filling this page) 413989 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (α) The material line is motivated or can be included in a predetermined time slot of one or more sets of data buses》 Each entry data buffer circuit 150 It has a predetermined data storage capacity and stores new asynchronous transmission mode data when the current data is stored. The asynchronous transmission mode data is transmitted to the bus along with the synchronous transmission mode data. The control data for the multiplexer 112 is selected from the control data generated by the arbiter circuit Π 0. The storage of multiplexed data in the link buffer circuit Π6 is controlled so as to perform broadcast switching of synchronous transmission mode data and asynchronous transmission mode data. Fig. 6 is a block diagram showing the connection between the link buffer circuit 116, the head buffer circuit 152, and the first and second stages 11 8A and 11_8B of the exit box multiplexer according to the present invention. The link data buffer circuit UI 6 is coupled to the exit frame multiplexer first stage UI 8A. It multiplexes the data streams from the four sets of link data buffer circuits 116 into a set of intermediate data streams. The frame header data stored in the header buffer circuit 152 is then multiplexed by the export frame multiplexer second stage 1 1 8B to use the intermediate data channel to multiplex to form a broadcast data channel. The broadcast data channel is then transmitted to the exit interface circuit. 108. FIG. 7 is a diagram of a group of portal bus frame formats 160 implementing the concepts of the present invention. The data transmitted through the portal bus 60 can be encoded into the format of the portal bus frame 160, or other appropriate formats. The entry bus frame format 160 has a period of 25 microseconds, and a data block with a frame header block group of 8 bytes containing 32 bytes of data is included to assist clock synchronization. The entrance bus frame format 160 also contains 50 groups of 64-bit bus slots. Each bus bar can be transferred to 25.92MΗZ. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2Ι0 ×: 297 mm) (please read the precautions on the back before filling this page). _ Order 413989 Economy A7 B7 printed by the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China. 5. Description of Invention (") A set of 8-bit wide data streams operated by frequency is provided to provide a band width of about 200Mb / s. Other suitable data stream formats and frequencies can also be used, such as data streams with any integer width between 1 and 128, more or fewer bus slots with more or fewer bytes, and Operating frequency between okHz and 200MHZ in 1Hz increments. FIG. 8 is a diagram of a set of exit bus frame formats 170 embodying the concepts of the present invention. The data transmitted via the export bus 62 can be encoded into the format of the export bus frame format 170, or other appropriate format. The export bus frame format 170 has a period of 125 microseconds, and has a frame file containing 32-byte data Head block. A set of 8-byte data pads are included in the synchronic clock synchronization outlet bus frame format 170. It also contains 202 sets of 64-bit bus slots. Each bus slot can be transmitted. On a set of 16-bit wide data streams operating at a frequency of 5 1.84 MHz, to provide a bandwidth of approximately 800 Mb / s. Other suitable data stream formats and frequencies can also be used, such as data streams with any integer width between 1 and 1 28, more or fewer bus slots with more or fewer bytes, And the operating frequency in increments of 1 Hz between 10 kHz and 200 MHZ. "Figure 9 is a diagram of a group of outlet busbar grids in a format of 180 which implements one of the concepts of the present invention. The exit bus slot grid filling format 180 shows a sequence in which data is transmitted from the four sets of link data buffer circuits 116 of the multiplexer circuit 106 in the exit bus frame format 170 via the exit bus 62. After the 32-bit egress bus header is transmitted, Link A transmits a packet containing one of 32 sets of 16-bit data packets, which forms a set of 64-bit egress bus slots. This data cover can be a set of synchronous feed mode data cover, a set (read the notes on the back first and then fill out this page) — installed 1, w 24 This paper size adopts China National Standard (CNS) A4 specifications ( 210X297 mm) Printed bags for consumer cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 413989 A7 B7 V. Description of the invention (β) Non-synchronous Fu mode data seals, such as iMP AX packaging layer data seals, a group of idle data seals, or other appropriate Information cover. Link B, link C, and link D then transmit 32 sets of 16-bit data packets each. The processing program then repeats every four groups of busbar slots until 200 sets of outlet busbar slots are transmitted. Two sets of idle data envelopes are then transmitted to complete the 202-byte export bus frame format 170 payload. In this manner, bus slot data from the entry bus frame format 160 can be accumulated in the four sets of link data buffer circuits 116 until they are full. The data is stored in four sets of link data buffer circuits 116 so that link A can transmit the first set of 64. byte exit bus slots, and then in order are link B, link C, and link D. As long as each key buffer has complete 64-byte data at the appropriate time, the data received from the six bus slots of the six entry bus 60 can be stored in four groups in the proper order. In the link buffer circuit M6. Therefore, when link A is transmitted, link D can be recharged if link B is already full. Then, when link B is transmitted, link C and link A can be recharged, and so on. FIG. 10 is a diagram of a group of exit slot address maps 190 that implements one of the concepts of the present invention. The exit slot address map 190 may be stored in the random access memory of the arbitration circuit 110 of FIG. Exit slot address map 1 90 is a set of 202 byte address maps, which contains the source address of the bus slot 60 of the entrance bus 60 corresponding to the bus slot of each exit bus 62. One set of 200 busbars in the form of a set of export bus frames 170 may include 50 sets of Link A data covers, 50 sets of Link B data covers, 50 sets of Link C data covers, and 50 sets of Link D according to the display order. Information cover. Will be used to provide export 25 paper sizes Applicable to China National Standards (CNS) A4 specifications (2 〖0 parent297 public ¥） III Pack n II i Silver (Please read the note on the back before filling this page) Ministry of Economy Printed by the Central Consumers Association Consumer Cooperatives 413989 A7 B7 I. Description of the invention (pair) Information on the corresponding position of the slot address map 190 The address of the bus bar 60 of the entrance bus 60 is stored in the exit slot Address map 190. For example, the outlet busbar slot A1 can be filled with a synchronous transmission mode data cover from the 13th group of the busbar slots of the 16th group of the input busbar 60. The address of the source of the input busbar will be stored in the outlet slot. In the location A1 of the grid address map 190. If you need to switch and change • For example, store the iMPAX package data from the third group of 16 ingress bus 60 and seal it in outlet bus slot A1 In FIG. 190, the arbitration circuit 110 then generates an appropriate command to cause the four sets of link buffer circuits 116 and the first stage 118A of the outlet frame multiplexer to place appropriate inlet bus slots in the outlet bus slot A1. Figure Π is a flowchart of a method 200 for controlling a telecommunications bus according to the concepts of the present invention. The method 200 begins at step 202, in which a plurality of bus slots of an inlet bus are received in a bus control circuit. The bus slots of these ingress buses can contain synchronous transfer mode data covers, asynchronous transfer mode data covers, and idle data covers. In addition to the bus slots of the plurality of inlet buses, the bus slots of the outlet buses containing non-synchronous transfer mode data from another bus control circuit and a set of bus interface circuits can also be received. 》 In step 2 04, the header data of the frame is extracted by the bus control circuit from each entry bus frame format. The header information of the frame can include routing, control, and other management data. • They can be used by the on-board controller circuit to determine the bus slot designation of the outlet bus slot of the inlet bus. The method then proceeds to step 206, in which the asynchronous transmission mode data is sealed and stored in 26 paper sizes using the Chinese Girl Standard (CNS) A4 specification (210X297 mm) ---------,-pack- ----- Order -----, line (please read the precautions on the back before filling this page) 413989 A7 B7 V. Data bus controller of the invention description (π). Another advantage of the present invention is a data bus control system that allows multiple groups of incoming data buses to be multiplexed into a single outgoing data bus. Although many embodiments and advantages of the present invention have been described in detail, it should be understood that the present invention may have various changes, alterations, substitutions, conversions, modifications, changes, and alterations without departing from the spirit of the invention as defined by the scope of the appended patents And categories. --------- '寒 ------ ir ----- 1' 0 (Please read the notes on the back before filling out this page) Economy. Printed by the Consumers Cooperative of the Central Bureau of Standards This paper size applies to China National Standard (CNS) A4 (210X297 mm)