TW416111B - Fabrication method of diffusion barrier layer of semiconductor device - Google Patents

Fabrication method of diffusion barrier layer of semiconductor device Download PDF

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Publication number
TW416111B
TW416111B TW087104982A TW87104982A TW416111B TW 416111 B TW416111 B TW 416111B TW 087104982 A TW087104982 A TW 087104982A TW 87104982 A TW87104982 A TW 87104982A TW 416111 B TW416111 B TW 416111B
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manufacturing
diffusion barrier
patent application
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TW087104982A
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Chinese (zh)
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Jae-Hee Ha
Hong-Koo Baik
Sung-Man Lee
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Lg Semicon Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6329—Deposition from the gas or vapour phase using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69393—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69394—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69397—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing two or more metal elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

The present invention relates to a fabrication method of a diffusion barrier layer of a semiconductor device. The diffusion barrier layer according to the present invention is formed by which at least one of microcrystalline oxide, oxide, microcrystalline nitride, and nitride which are insulating materials is added into a refractory metal material according to a sputtering deposition method or a chemical vapor deposition method. The diffusion barrier layer according to the present invention shows high stability even at high temperature since the insulating material added into the refractory metal material is stuffed into matrix of the refractory metal material, and thus bound with the refractory metal material, thus forming the diffusion barrier layer in microcrystalline or amorphous condition.

Description

A7 416111 B7 五、發明説明（1 ) 太链昍之镅域 本發明偽闢於一半導體元件，且更特別地翻於一種能 夠藉著以各種方法將一絶緣材料加入阑火性金屬而獲得在 高溫是穩定的一半導體元件的一擴散障壁層的半導體擴散 障壁層之製造-方」去〇 背軎討論 為了改善半導體元件之可靠性，處在高摄定性的一纊 散障壁層已被需求；當通過晶粒邊界的擴散在一熱力端像 困難時在一互相連接材料和一基體材料間形成的擴散障壁 層變成一被動障壁，且相反的，當容易通過晶粒邊界被擴 散時其變成一非障壁，並且當在熱力端中不穩定時其變成 一犧牲的障壁；亦即，該擴散障壁層與該互相建接材料或 該基體材料反應，因此防止該等材料之擴散，然而因該反 應而該擴散障壁厢逐漸被耗盡，且最後可預期該擴敗障壁 層之破壞。 在一多結晶薄膜中，因為通過晶粒邊界的擴散較逋過 晶格容恳_故防止通過晶粒邊界的擴散是很重要的。 據此，為了防止通過晶粒邊界的擴散，使用不具晶粒 邊界作為擴散障壁暦的單矽或非結晶矽之方法，與隔離晶 格的填塞方法已被使用；在填塞方法中最通常方法的氪缜 塞和氣填塞具有一不利處即氰或氣微弱地以金屬材料之矩 陣束缚，因此因在高攝__下一長時間的熱處理中的快速:擴散 使擴散障壁層不能用作一防止膜。 以參考所伴隨圈式，一種半導體元件擴散障壁層之習 本紙張尺度適用中國國家標準（CMS ) A4規格（2彳0X 297公釐） (讀先閱讀背而之注意事項再填寫本買) 裝· 訂 經濟部中央標準扃員工消费合作社印51 416111 A7 B7 五、發明説明（2 ) 用製迪方法將被描述。 在第一A圖中，一絶緣層2在具有一雜質區（未示） 的一半導體基體1上形成，且暴露半導體基體1之該雜質區 的一接觸孔3在絶緣層2中形成。 在第一B圖中，含有一金屬材料的一第一擴散障壁層 4在包括接觸孔3的絶緣磨2上形成„ 如在第一 B和一C圖中顯示的，一氣罨漿處理被施加 於笫一擴散障壁層4,因此一第二擴散障壁層5被形成且熱 處理被施加於它；根據該氣電漿處理，氣通過該金靥之晶 粒邊界被擴散，因此獲得一填塞效果；其次，一金屬_6 在具有己被CVD電漿處理的第二擴散障壁層5上形成，且然 後熱處理被施加於它，因此完成用於該半導體元件的擴散 障壁層之該習用製造方法；在此，金屬層6傜以Al、A1合 金、銅、及銅合金形成。 經濟部中央標隼局貝工消費合作社印製 --------裝------訂 Λ . . (讀先間讀谇面之泣意事項再填艿本頁) 被該習用方法製造的擴散障塋層具有數悔不利黏；第 一，因為搌散障壁層係以非結晶矽形成，故熱力I定性掉 落；第二，當施用氮《塞或氣填^_«_tL或屬偽拥!弱地與 該@料束缚，因此因在高溫下的一長時間處理中的快速擴 散該擴散障壁_不能作為防止膜；第三，_當I塞^毫 ，因高離子能量該薄膜可能具有缺損。 據此，本發明被指向於一種半導髏元件擴散障壁層的 製造方法，其除去根據相關技藝的間題。 本發明之一目的偽提供在一高溫回火處理中具有高穩 本紙張尺度適用中國國家梯準（CNS ) Λ4規格（2】0Χ297公釐） 416111 A7 B7 五、發明説明（3 ) 定性的半導體元件擴散障壁層之一種製造方法。 本發明之額外恃擻和利益將在隨#的描述中被説明， 並且從該描述將會清楚，或可藉本發明之施用而認知的； 本發明之目標和其它利益將被在書寫描述和其之申誚專利 範圍以及所附圖式中特別指出的結構而被認知和播得。 為了達成這些和其它利益並根濂本發明之目的t如被 物化和廣泛地被描述的，一種半導體元件擴散障壁層之製 造方法包括下列步驟：形成一絶緣層，其中暴露一半導體 基體之一雜質區的一接觸孔被設在該半導體基髏上；形成 並施加一回火處理於含有在包括該接阑孔的該绝線層上之 一耐火性金屬材料和一絶緣材料的一擴戢障壁層；及形成 並施加一回火處理於在該擴散障壁層上的一互相連接層。 請瞭解到，前述一般描逑和下面詳細描述係例示性和 説明性的並企圖提供如申請專利範圍的本發明之進一步說 明。 圖立之簡.單説盥 經濟部中央標準局貝工消費合作社印黎 1 I— I In t n i . I ϋ I: I11 - , (锖先閱讀背而之注意事項再填寫本頁) 被包括以提供本發明之一更瞭解且被併入和構成此說 明書之一部分的所伴随圖式說明本發明之實施例並與說明 一起用作解釋本發明之原理。 在圈式中： 第一A至一C匾偽垂直截面画建缠地說明一種半導體 元件擴敗障壁層之習用製造方法； 第二A至二C圖傜根據本發明的垂直截面圖建鑲地說 明一種半導體元件擴散障壁層之製造方法； ____ -— -- E --—— 本紙乐尺度適用中國國家標準（CNS)A4規格（210X297公釐） 416111 Λ7 B7 經濟部中央標率爲員工消費合作社印製 五、發明説明（4 ) 第三圖係一圖説明在藉一濺鍍方法將Ta沉積在具有在 第二B圖中一接觸孔的一絶緣層上之Ta 4f XPS頻譜； 第四圖係一圖說明根據本發明擴散障壁雇之一宵施例 以在真空中各種〇6〇3電力條件的5 0 0和80〇1〇間回火的13 + CetWSi糸統之薄片阻抗； 第五圖傜一圖顯示根據本發明擴散障壁層之該實施例 的 Ta + CeOa(150W)層之 Ta 4f !(PS 頻譜； 第六圖係一圖顯示根據本發明擴散障壁層之該實施例 在Ta+Ce0,(150W)層被在800t：回火後之Ta 4f XPS頻譜； 第七圖係一圖説明在Ta + CeO,層被沉積在一 Si基體上 並在各種溫度被回火30分鐘後Ta + CeO, (170W)層之乍見XRD 圖型；及 第八圖偽一圖説明在Ta+CeO,層被沉稽在一 Si基體上 並在各種溫度被回火30分鐘後Ta + CeQs(150W)層之乍見XRD 鼸型。 太發明^拄細锐昍 現在將詳細地參考本發明之較佳實施例，其之例子在 所伴随圖式中被説明。 第二A至二C圖係根據本發明的垂直截面圖連績地銳 明一種半導體元件擴散障壁層之製造方法。 在第二A圖中，一絶緣層2 0在具有一雜質區（未示） 的一半導體基體10上形成.且暴露該雜質匾的一接觴孔30 在絶緣層20中形成。 在第二B圖中，一擴散障壁層40在包含接皤孔30的絶 1. 1! I I n I 、1T -- {請先閱讀背16之注意事項再填巧本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部中央標準扃員工消費合作社印掣 416111 A7 B7五、發明说明（5 ) 緣層20上形成，且然後一回火處理被施於它；在此，有三 種方法可形成擴散障壁層40Ρ 第一，在濺鍍設備中使用包含一耐火從孟屬材料的一 第一靶標及含有一絶緣材料的一第二靶標的一種技藶潘.沉 積方法。 第二，在濺鍍設備中使用包含該酎火性金属材料和該 绝緣材料的一靶標或一板台之一種濺鍍沉稹方法。 第三，在CVD設備中使用包含該耐火性金屬材料和該 絶緣材料的一組合物之一種化學氣相沉積方法。 在此，作為該阑火性金属材料，Ti、Ta、Μο、及W之 至少一傾被使用，且作為該絶線材料微結晶氣化物、氡化 物、徹結晶氮化物、及氮化物之至少一梅被使用。 如上所述的.根據本發明的擴散障壁層可以化學氣相 沆稍方法及濺鍍沉積方法來製造。 在第二_中.一金羼層50被形成在擴散障壁層40上且 該回火處理被施於它；金屬層50以AU Α1合金、Cu、及Cti 合金之至少一個形成。 第三至八圖係説明對應於根據本發明的半導體元件擴 散障壁層之一實施例的一Ta+CetK層之實驗資料的鬮。 第三圖顯示當Ta只被一濺锣方法沉積在具有在第二A 画中的接觸孔之绝縳層上時的Ta 4f XPS(X射線光電示波 器）頻譜；各中心峰值傜分別在22,399eV、24 . 327eV及33 ，4?0eV;這些結果顯示並不組合於氣的Ta 4f特定XPS頻譜。 第四圖說明根據本發明的擴散障壁屬之一實施例的當 -----=-8-=-------— 本紙張尺度適用中國國家標準（CNS } Λ4規格（210X 297公釐） ^^1 n —m tn ♦ ir tth --"^ --:s > - (請先閱讀背而之注意事項再填寫本页) A7 B7 416111 i、發明説明u ) , 11^I -(請先鬩讀背面之注意事項再填寫本頁) 一 Ta + CeO,層被沉積在具有在第二B圖中的接觸孔的絶緣 層上並在宾空中以各種Ce〇a電力條件在500和800亡間回火 時在Ta + Ce〇a/Si条統之薄片阻抗和溫度間的關像；如其中 所示的，随著回火溫度增大，Ta+CeO,之結晶並無改變且 當加入CeO·時其與Si之介面可穩定化高至800 1C ; 130W、 15 0W及17M分別顯示高頻電力源。 第五圖顯示當Ta + CeO, (150W)層被沉積在具有在第二 B圖中的接觸孔之絶綠層上時的Ta 4f XPS頻譜（Al Κ α 激發）；如其中所示的，恃定峰值被示於26eV、28eV,除 了 Ta4f之特定峰值22eV、24eV、及34eV外；此傜線於Ta-0 鍵結，而顯示當Ta和Ce09被一共濺鍍方法沉積時，從Ce〇« 靶檫分解的部分之氧在一電漿情況中與Ta組合。、 第六画顯示當Ta+Ce〇e (15GW)層被沉稹在具有在第二 B圖中的接觸孔之絶綠層上時的Ta 4f XPS頻譜（Al Κ α 激發），並在800 t：回火；如其中所示的，Ta-t)之鍵結能 量在第四圖中在26eV、28eV之待定峰值被在800 t：之回火 處理大大地增加；上述結果指出隨著画火溫度之增大在Ta + C0〇a層中的Ta-Ο鍵結被強化。 經满部中央標準局員工消費合作社印製 第七醑説明在Ta+Ce〇e層被沉積在一 Si基體上並以各 種溫度回火三十分鐘後Ta + Ce〇a (170W, 100nBt)/Si糸統之 乍見XRD(X射線嬈射）圖型；如其中所示的，只出現在37 (Z0) —鲴峰值，顯示該1^ + {：0〇*層傺在一非結晶或一撤 結晶型式，且既使回火溫度增加到750 "C結晶化也無改變 ;亦即，既使以回火溫度之增大，該Ta + Ce0a層仍為非結 __—--—--- 9~ 本紙張尺度適用中國國家標準（CNS ) A4規格（2]0乂297公犛） A7 B7 五、發明説明（7 ) 晶或撇結晶型式，且矽化Ta並不被Ta和Si基體之反醮而形 成。A7 416111 B7 V. Description of the invention (1) The domain of the Tailian chain The present invention is based on a semiconductor device, and more particularly, it can be obtained by adding an insulating material to a flame-resistant metal in various ways. High temperature is a stable semiconductor diffusion barrier layer manufacturing of a semiconductor element-a manufacturing method of the semiconductor diffusion barrier layer "goes to the back of the discussion to improve the reliability of the semiconductor element, a high level of dispersion of the barrier layer has been required; When diffusion through the grain boundary is difficult at a thermal end, a diffusion barrier layer formed between an interconnecting material and a matrix material becomes a passive barrier, and conversely, it becomes a passive barrier when it is easily diffused through the grain boundary. Non-barrier and becomes a sacrificial barrier when unstable in the thermal end; that is, the diffusion barrier layer reacts with the interconnecting material or the base material, thus preventing the diffusion of these materials, but due to the reaction The diffusion barrier is gradually depleted, and finally the destruction of the expanded barrier layer can be expected. In a polycrystalline thin film, it is important to prevent diffusion through the grain boundary because diffusion through the grain boundary is more dense than lattice tolerance. According to this, in order to prevent the diffusion through the grain boundary, the method of using single silicon or amorphous silicon without the grain boundary as a diffusion barrier, and the packing method of isolating the lattice have been used; the most common method in the packing method Congestion and gas packing have a disadvantage that cyanide or gas is weakly bound by a matrix of metallic materials, so due to the rapidity in the next long heat treatment: diffusion makes the diffusion barrier layer cannot be used as a prevention film . With reference to the accompanying circle type, a standard for the diffusion barrier layer of a semiconductor device. The paper size is applicable to the Chinese National Standard (CMS) A4 specification (2 彳 0X 297 mm). (Please read the precautions before filling in this purchase). · Set the central standard of the Ministry of Economy 印 Stamp of Consumer Cooperatives 51 416111 A7 B7 V. Description of Invention (2) The method of making di will be described. In the first diagram A, an insulating layer 2 is formed on a semiconductor substrate 1 having an impurity region (not shown), and a contact hole 3 exposing the impurity region of the semiconductor substrate 1 is formed in the insulating layer 2. In the first diagram B, a first diffusion barrier layer 4 containing a metallic material is formed on the insulating mill 2 including the contact hole 3. As shown in the first diagrams B and C, an air slurry treatment is applied In the first diffusion barrier layer 4, a second diffusion barrier layer 5 is formed and a heat treatment is applied to it; according to the gas plasma treatment, the gas is diffused through the grain boundaries of the gold alloy, thereby obtaining a packing effect; Next, a metal_6 is formed on the second diffusion barrier layer 5 having been treated with a CVD plasma, and then a heat treatment is applied to it, thereby completing the conventional manufacturing method for the diffusion barrier layer for the semiconductor element; Therefore, the metal layer 6 is formed of Al, A1 alloy, copper, and copper alloy. Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs -------- installation ---- order Λ.. (Read the weeping on the first reading page and fill out this page) The diffusion barrier layer made by this custom method has a few regrets and is not sticky. First, because the barrier barrier layer is formed of amorphous silicon, it is thermally active. I fall qualitatively; second, when applying nitrogen "plug or gas filling ^ _« _ tL or pseudo-embrace! Weak It is bound with the @ 料, so the diffusion barrier cannot be used as a preventive film due to the rapid diffusion during a long period of processing at high temperature; third, when I plug it, the film may have defects due to high ion energy. According to Therefore, the present invention is directed to a method for manufacturing a diffusion barrier layer of a semiconducting cross element, which removes the inconvenience according to the related art. One object of the present invention is to provide a paper sheet with high stability in a high temperature tempering process, which is applicable to China. National Ladder Standard (CNS) Λ4 specification (2) 0 × 297 mm 416111 A7 B7 V. Description of the invention (3) A method for manufacturing a qualitative semiconductor element diffusion barrier layer. The additional advantages and benefits of the present invention will be described in the following sections. It is described in the description, and will be clear from the description, or may be recognized by the application of the present invention; the object and other benefits of the present invention will be specifically described in the written description and the scope of its patent application and the drawings. The indicated structure is recognized and broadcast. In order to achieve these and other benefits and root the purpose of the present invention, as materialized and widely described, a semiconductor element diffusion barrier The manufacturing method of the layer includes the following steps: forming an insulating layer in which a contact hole exposing an impurity region of a semiconductor substrate is provided on the semiconductor substrate; forming and applying a tempering treatment to One of the refractory metal material and an expanded barrier layer of an insulating material on the insulation layer; and forming and applying a tempering treatment to an interconnecting layer on the diffusion barrier layer. Please understand that the foregoing general The description and the following detailed description are illustrative and illustrative and are intended to provide further explanation of the invention, such as the scope of patent application. Brief description of the drawings. Simplified. Speaking of the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, India, Li 1-I In tni. I ϋ I: I11-, (锖 Read the following precautions before filling out this page) is included to provide a better understanding of the invention and is incorporated into and forms part of the accompanying illustration The embodiments of the present invention are used together with the description to explain the principle of the present invention. In the circle type: The first pseudo-vertical cross-section drawing of A to C plaques illustrates a conventional manufacturing method for expanding the barrier layer of a semiconductor element; the second A to C shows the vertical cross-sectional view of the ground according to the present invention. Describe a method for manufacturing a semiconductor device diffusion barrier layer; ____ ----E --—— This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 416111 Λ7 B7 The central standard of the Ministry of Economy is the employee consumer cooperative Printing 5. Description of the invention (4) The third diagram is a diagram illustrating the Ta 4f XPS spectrum of Ta deposited on an insulating layer having a contact hole in the second B diagram by a sputtering method; the fourth diagram A diagram illustrating the sheet impedance of the 13 + CetWSi system tempered between 500 and 8000 in various vacuum power conditions in a vacuum according to an embodiment of the diffusion barrier employed in the present invention; fifth FIG. 21 is a diagram showing the Ta 4f! (PS spectrum of the Ta + CeOa (150W) layer of the embodiment of the diffusion barrier layer according to the present invention; FIG. 6 is a diagram showing the embodiment of the diffusion barrier layer according to the present invention at Ta + Ce0, (150W) layer is 800t: Ta 4f XPS spectrum after tempering The seventh diagram is a diagram illustrating the XRD pattern of the Ta + CeO, (170W) layer after Ta + CeO, the layer is deposited on a Si substrate and tempered at various temperatures for 30 minutes; and the eighth diagram The pseudo-picture shows that at Ta + CeO, the layer is sunk on a Si substrate and tempered at various temperatures for 30 minutes. At first glance, the Ta + CeQs (150W) layer is seen as an XRD type. Reference will be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The second A to C diagrams are a series of semiconductor device diffusion barrier layers sharpened in accordance with the vertical sectional view of the present invention. Manufacturing method. In the second diagram A, an insulating layer 20 is formed on a semiconductor substrate 10 having an impurity region (not shown), and a contact hole 30 exposing the impurity plaque is formed in the insulating layer 20 In the second diagram B, a diffusion barrier layer 40 is located between the 1. 1! II n I and 1T including the junction hole 30-{Please read the precautions on the back 16 before filling in this page) Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Central Standard of the Ministry of Economy 扃 Staff Consumer Cooperative Cooperative Stamp 416111 A7 B7 Description of the Invention (5) The edge layer 20 is formed, and then a tempering treatment is applied to it; here, there are three methods to form the diffusion barrier layer 40P. First, in a sputtering apparatus, a refractory material containing a refractory metal is used. A technique for depositing a first target and a second target containing an insulating material. Second, a sputtering deposition method using a target or a plate including the pyrophoric metal material and the insulating material in a sputtering apparatus. Third, a chemical vapor deposition method using a combination of the refractory metal material and the insulating material in a CVD apparatus. Here, as the flame-resistant metallic material, at least one of Ti, Ta, Mo, and W is used, and as the insulation material, at least one of microcrystalline gaseous, hafnium, completely crystalline nitride, and nitride is used. Yimei was used. As described above, the diffusion barrier layer according to the present invention can be manufactured by a chemical vapor deposition method and a sputtering deposition method. In the second step, a gold hafnium layer 50 is formed on the diffusion barrier layer 40 and the tempering treatment is applied to it; the metal layer 50 is formed of at least one of AU A1 alloy, Cu, and Cti alloy. The third to eighth figures are explanatory diagrams of experimental data of a Ta + CetK layer corresponding to one embodiment of the semiconductor device diffusion barrier layer according to the present invention. The third figure shows the Ta 4f XPS (X-ray photo oscilloscope) spectrum when Ta is deposited on the barrier layer with the contact hole in the second A picture only by a splash gong method; each center peak is, 22,399 eV , 24. 327eV and 33, 4? 0eV; these results show Ta 4f specific XPS spectrum that is not combined with gas. The fourth figure illustrates an embodiment of the diffusive barrier according to the present invention. -------- =-8-= -------— This paper size is applicable to the Chinese national standard (CNS) Λ4 specification (210X 297 Mm) ^^ 1 n —m tn ♦ ir tth-" ^-: s >-(Please read the precautions before filling in this page) A7 B7 416111 i 、 Invention Note u), 11 ^ I-(Please read the notes on the back before filling this page)-Ta + CeO, the layer is deposited on the insulating layer with the contact hole in the second B figure and various CeOa power is used in the guest space. The conditions between the sheet impedance and temperature of the Ta + Ce0a / Si system during tempering between 500 and 800; as shown in the figure, as the tempering temperature increases, the crystals of Ta + CeO, There is no change and when CeO · is added, its interface with Si can be stabilized up to 800 1C; 130W, 150W and 17M respectively show high-frequency power sources. The fifth figure shows the Ta 4f XPS spectrum (Al K α excitation) when the Ta + CeO, (150W) layer is deposited on the green layer with the contact hole in the second B diagram; as shown therein, The fixed peaks are shown at 26eV and 28eV, except for the specific peaks of Ta4f, 22eV, 24eV, and 34eV; this line is bonded to Ta-0, and shows that when Ta and Ce09 are deposited by a co-sputtering method, they are removed from Ce. «Part of the target's decomposition of oxygen is combined with Ta in the case of a plasma. The sixth painting shows the Ta 4f XPS spectrum (Al κ α excitation) when the Ta + Ce〇e (15GW) layer is immersed on the green layer with the contact hole in the second B diagram, at 800 t: tempering; as shown therein, the bond energy of Ta-t) in the fourth figure is 26eV, 28eV to be determined peak at 800 t: tempering treatment greatly increased; the above results indicate that with the drawing The increase in fire temperature strengthens the Ta-O bond in the Ta + Coa layer. Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the People's Republic of China. The seventh illustration shows that the Ta + Ce〇e layer is deposited on a Si substrate and tempered at various temperatures for 30 minutes. Ta + Ce〇a (170W, 100nBt) / At first glance of the Si system, see the XRD (X-ray diffraction) pattern; as shown therein, it only appears at the peak of 37 (Z0)-鲴, showing that the 1 ^ + {: 0〇 * layer 傺 in an amorphous or A crystallization pattern is withdrawn, and even if the tempering temperature is increased to 750 " C crystallization, there is no change; that is, even with the increase of the tempering temperature, the Ta + Ce0a layer is still non-junction __---- —--- 9 ~ This paper size is in accordance with Chinese National Standard (CNS) A4 specification (2) 0 乂 297mm 牦 A7 B7 V. Description of the invention (7) Crystal or skimming type, and Ta silicide is not affected by Ta and Ta The Si substrate is instead formed.

第八圖說明在Ta + CeO,層被沉積在一Si基體上並以各 種溫度回火三十分鐘後Ta + CeO，（150W, 100na)/Si条統之 乍見XRD圖型；如其中所示的，在150 W之電力情況中沉穑 的該Ta + CeO»層在高至750TC之回火溫度仍為一非結晶或一 拥!結晶型式；但是，當回火溫度達到800 TC時，一峰值在 35至38 ( 2Θ )間分離，顯示Ta變的结晶化D 如上所述的，根據本發明的半導體元件鑛散障壁層之 製造方法具有數個優點；由將撖結晶氧化物、氣化物、微 結晶氮化物及氮化物中之至少一種加入耐火性金羼材料而 形成的擴散障堃層會維持撤結晶或非結晶情況，因此在 長期熱處理中具有強穩定性；同時，本發明可避開因當以 電漿方法或植入的《塞氣和氮時所觀測的高離子能量所導 1T的薄膜钕損/另外，If敗障壁層和矽之反蘸可藉適當選 取解火性金屬和絶緣膜而被避免，因此改P該半導體元件 之可靠性。 视濟部中央標準局員工消費合作社印製 ^^1 ^^^1 tm tt ^^^1 ^^^1 ^^^1 —^ϋ I nn .^1^1 ^^^1 TJ. - - (請先閲讀背而之注意事項再填艿本頁) 對於熟於此技術者是清楚的，在本發明之半導體元件 擴散障壁層之製造方法中可作各種修正與變化而不偏離本 發明之精神或範畴；因此只要是在所附申請專利範圍和它 們之等效者之内本發明涵蓋本發明之該等修正和變化。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2丨0·〆297公垒1? 經濟部中央標隼局員工消費合作社印製 416111五、發明説明（8 ) ttF;件迫號對聪耒 1、 10基體 2、 20絶綠層 3、 3 0接觸孔 A7 B7 4、 5、40擴散障壁層 5、 50金屬層 ---------裝-- • - < (請先閱讀背雨之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1+The eighth figure illustrates that at Ta + CeO, the layer is deposited on a Si substrate and tempered at various temperatures for thirty minutes. Ta + CeO, (150W, 100na) / Si system at first glance XRD pattern; as shown therein As shown, the Ta + CeO »layer that has been immersed in the 150 W power condition is still an amorphous or a support at the tempering temperature up to 750TC! However, when the tempering temperature reaches 800 TC, A peak is separated between 35 and 38 (2Θ), which shows the crystallization of Ta. As described above, the method for manufacturing a semiconductor device ore dispersion barrier layer according to the present invention has several advantages; The diffusion barrier layer formed by adding at least one of the compounds, microcrystalline nitrides, and nitrides to the refractory gold alloy material will maintain decrystallization or non-crystallinity, and therefore has strong stability during long-term heat treatment; at the same time, the invention can Avoiding the neodymium loss of 1T film induced by the high ion energy observed when using the plasma method or implanted "gas plugging and nitrogen" / In addition, if the barrier layer and the reverse dipping of silicon can be properly selected, the fire resistance Metal and insulating film are avoided, so change this semiconductor element Reliability. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Inspection ^^ 1 ^^^ 1 tm tt ^^^ 1 ^^^ 1 ^^^ 1 — ^ ϋ I nn. ^ 1 ^ 1 ^^^ 1 TJ.-- (Please read the following precautions before filling out this page) It is clear to those skilled in the art that various modifications and changes can be made in the method for manufacturing the semiconductor device diffusion barrier layer of the present invention without departing from the invention. The spirit or scope; therefore, the invention covers such modifications and variations as long as they are within the scope of the appended patent applications and their equivalents. This paper size applies the Chinese National Standard (CNS) Λ4 specification (2 丨 0 · 〆297 public base 1? Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 416111 V. Invention Description (8) ttF; 1, 10 substrate 2, 20 green insulation layer 3, 3 0 contact hole A7 B7 4, 5, 40 diffusion barrier layer 5, 50 metal layer --------- install-•-(please first Read the precautions for back rain before filling out this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 1+

Claims (1)

經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 1 . 一種半導體元件擴散障壁靥製造方法.其包含下列步 驟： 形成一絶緣其中暴露一半導體基體之一雜質 區的一接觸孔被設置在該半導體基體上； 在包括該接觸孔的該絶緣層上形成含有一附火性 金屬材料和一雙障里歷，並對它施加 一回火處理；及 在該擴散障壁層上形成一互相連接層並»它旃加 —回火處理。 2. 依據申讅專利範圍第1項之製造方法，其中形成該擴 散障壁雇之該步耜施用使用包含該耐火性金匾材料的 一第一靶檫及含有該絶緣材料的一第二靶標的一種共 醆鍍沉積方法。 3. 依據申請專利範圍第1項之製造方法，其中形成該搌 散障壁層之該步驊施用包含該耐火性金鵰材料和該絶 緣材料的一靶標或一板台。 4_依據申請專利範圍第1項之製造方法，其中形成該擴 散障壁層之該步箱施用使用包含該耐火性金屬材料和 該絶緣材料之一化合物的一化學氣相沉穑方法。 5. 依據申_專利範围第1項之製造方法，其中該附火性 金颶材料偽以Ti、Ta、Mo、及W中之至少一種形成， 且該絶線材料偽以微結晶氣化物、氣化物、黴結晶氟 化物、及氮化物中之至少一種形成。 6. 依嬅申諳專利範圍第1項之製造方法f其中該互相連 ___________r 1 ?"-- 本紙張尺度逋用中國國家標準（CNS > A4規格（210X297公釐） i^i^v —^if ml n^i ^^^^1 —B-IB n -(請先閡讀背而之注項再填寫本頁) ABCD 經濟部中央標率局員工消費合作社印製 六、申請專利範圍 接層係以AU A1合金、Cu、及Cii合金中之至少一種形 成。 7. —種半導體元件擴散障壁«製造方法，其包含： 在一半導體基體上形成一絶綠層並在該半導體基 體之一預定部分中形成一接觸孔的一第一步驟； 在包括該接觸孔的該絶緣層上形成含有一耐火性 金靥材料和一絶綠材料的一擴散障壁層的一第二步驟； 在該擴散障壁層上形成一互相連接層的一第三步 琢；及 將該互相連接層和該擴散障壁層鬮型化的一第四 步驟。 8. 依據申請專利範圍第7項之製造方法，其中該半導體 基體之該預定部分愾一雑質區。 9. 依據申請專利範圍第7項之製造方法，其中該第二步 驟之該金屬材料包含阑火性金屬。 10. 依據申請專利範圍第9項之製造方法，其中該耐火性 金靥係以Ti、Ta、Ηο、及W中之至少一種形成。 11. 依據申請專利範圍第7項之製造方法，其中該绝緣材 料係以橄結晶氣化物、氣化物、榭結晶氮化物、及氮 化物中之至少一種形成。 12. 依據申諳專利範園第7項之製造方法，其中該第二步 驟施用使用包含該金屬材料的一第一靶標及含有該绝 躲材料的一第二靶檫的一共濺鍍沉積方法。 13. 依據申請專利範圍第7項之製造方法，其中該第二步 -13- .(請先閱讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標隼（CNS) Α4規格（2丨0Χ297公釐> 4mu ABCD 六、申請專利範圍 驟施用使用包含該金觴材料和該絶緣材料的一化合物 靶標的一濺鍍沉積方法^ 14. 依據申諳專利範画第7項之製造方法，其中該第二步 驟施用使用包含該金屬材料和該絶鏵材料的一板台的 一濺鍍沉積方法。 15. 依撺申謫專利範®第7項之製造方法，其中該第二步 驟施用使用包含該金靨材料和該絶綠材料的一化合物 的一化學氣相沉積方法。 1L依搛申諳專利範圍第7項之製造方法，其中各在該等 第二和第三步驟後，一回火處理被施用。 17.依據申請專利範圍第7項之製迤方法，其中該互相連 接層煤以Al、A1合金、Cu、及Cu合金中之至少一種形 成。 (請先閲讀背面之注意事項再填寫本頁) .裝- -5 經濟部中央標準局員工消費合作社印策 __ ~ 14 ~ 本紙張尺度逋用中國國家標隼（CNS>A4規格（210X297公釐）Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 VI. Patent application scope 1. A method for manufacturing a semiconductor device diffusion barrier 靥, which includes the following steps: forming an insulation in which a contact area of an impurity region of a semiconductor substrate is exposed A hole is provided on the semiconductor substrate; a fire-resistant metal material and a double barrier calendar are formed on the insulating layer including the contact hole, and a tempering treatment is applied to it; and on the diffusion barrier layer An interconnected layer is formed and »it is added-tempered. 2. The manufacturing method according to item 1 of the patent application scope, wherein the step of forming the diffusion barrier is applied using a first target containing the refractory gold plaque material and a second target containing the insulating material. A holmium plating deposition method. 3. The manufacturing method according to item 1 of the scope of patent application, wherein the step of forming the scatter barrier layer is to apply a target or a pallet including the refractory gold carving material and the insulating material. 4_ The manufacturing method according to item 1 of the scope of patent application, wherein the step box forming the diffusion barrier layer is applied by a chemical vapor deposition method using a compound including the refractory metal material and one of the insulating materials. 5. The manufacturing method according to claim 1 of the patent scope, wherein the flammable golden hurricane material is pseudo-formed with at least one of Ti, Ta, Mo, and W, and the insulation material is pseudo-crystalline gaseous. , At least one of gaseous, mold crystal fluoride, and nitride. 6. The manufacturing method according to item 1 of the scope of patent application f which should be interconnected ___________r 1? &Quot;-This paper size uses the Chinese national standard (CNS > A4 size (210X297mm) i ^ i ^ v — ^ if ml n ^ i ^^^^ 1 —B-IB n-(please read the back note first and then fill out this page) ABCD Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The range bonding layer is formed of at least one of AU A1 alloy, Cu, and Cii alloy. 7. A method for manufacturing a semiconductor element diffusion barrier «, comprising: forming a green insulating layer on a semiconductor substrate and forming the semiconductor substrate on the semiconductor substrate A first step of forming a contact hole in a predetermined portion; a second step of forming a diffusion barrier layer containing a refractory gold tincture material and a green insulating material on the insulating layer including the contact hole; A third step of forming an interconnecting layer on the diffusion barrier layer; and a fourth step of forming the interconnecting layer and the diffusion barrier layer into a fourth step. 8. A manufacturing method according to item 7 of the scope of patent application, Wherein the predetermined portion of the semiconductor substrate is 9. The manufacturing method according to item 7 of the scope of the patent application, wherein the metal material in the second step includes a flame-resistant metal. 10. The manufacturing method according to item 9 of the scope of the patent application, wherein the refractory gold alloy is based on At least one of Ti, Ta, Ηο, and W is formed. 11. The manufacturing method according to item 7 of the scope of patent application, wherein the insulating material is made of olive crystalline gaseous, gaseous, crystalline nitride, and nitride At least one of them is formed. 12. The manufacturing method according to item 7 of Shenyang Patent Fanyuan, wherein the second step applies the use of a first target containing the metal material and a second target containing the insulative material. A total of sputtering deposition methods. 13. The manufacturing method according to item 7 of the scope of patent application, where the second step -13-. (Please read the precautions on the back before filling this page) This paper standard (Chinese national standard) (CNS) Α4 specification (2 丨 0 × 297 mm > 4mu ABCD VI. Application scope of patent Application of a sputtering deposition method using a compound target containing the gold tin material and the insulating material ^ 14. According to Shen The manufacturing method of item 7 of Lifan painting, wherein the second step applies a sputtering deposition method using a platen containing the metal material and the insulating material. 15. Manufacturing according to Patent Application No. 7 A method in which the second step applies a chemical vapor deposition method using a compound comprising the gold tincture material and the adiabatic material. 1L is a manufacturing method according to item 7 of the patent application scope, each of which After the second and third steps, a tempering treatment is applied. 17. The method of making plutonium according to item 7 of the scope of the patent application, wherein the interconnected layer coal is formed with at least one of Al, A1 alloy, Cu, and Cu alloy . (Please read the precautions on the back before filling out this page). Packing--5 Printing Policy of Employee Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs __ ~ 14 ~ This paper size uses China National Standards (CNS > A4 Specification (210X297) %)
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US5614437A (en) * 1995-01-26 1997-03-25 Lsi Logic Corporation Method for fabricating reliable metallization with Ta-Si-N barrier for semiconductors
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