TW417272B - Align mark pattern in semiconductor manufacturing process - Google Patents

Align mark pattern in semiconductor manufacturing process Download PDF

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Publication number
TW417272B
TW417272B TW86100445A TW86100445A TW417272B TW 417272 B TW417272 B TW 417272B TW 86100445 A TW86100445 A TW 86100445A TW 86100445 A TW86100445 A TW 86100445A TW 417272 B TW417272 B TW 417272B
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Taiwan
Prior art keywords
pattern
alignment mark
line
microns
mark pattern
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TW86100445A
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Chinese (zh)
Inventor
Chang-Shiun Li
Fu-Jeng Lin
Jen-Tai Guo
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Mosel Vitelic Inc
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Priority to TW86100445A priority Critical patent/TW417272B/en
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Publication of TW417272B publication Critical patent/TW417272B/en

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Abstract

There is provided an align mark pattern for enhancing the alignment accuracy in semiconductor manufacturing process. The align mark pattern comprises: a cross pattern formed on the scribe line to be used for alignment in the process in which the cross pattern includes the horizontal line pattern and vertical line pattern, and the horizontal line pattern is parallel to scribe line and the vertical line pattern is perpendicular to scribe line; and two horizontal wave line pattern in which the horizontal wave line pattern and the scribe line are formed on the scribe line in parallel and connected with the two ends of vertical line of the cross pattern respectively. The horizontal wave pattern comprises the repetitive saw-shape waves formed on the wave horizontal line pattern and the pattern on the junction surface of the vertical line so as to improve the alignment accuracy of the manufacturing process.

Description

417272 Α7 Β7 五、發明説明() 發明領域: 本發明與一種形成於切割道(scribe line)上之對準標 記圈案(align mark pattern)有關,特别是一種增達對準 精確性之對準標記圖案。 發明背景: 半導體製程一直傾向於節省空間之設計,目前使用 兩、三層或是更多之内連線製作技術,而且執行一功能所 需之元件數目亦漸減,例如早期需要六個電晶體之DRAM 現在可以用一個電晶體與電容器所取代。417272 Α7 Β7 V. Description of the invention () Field of the invention: The present invention relates to an align mark pattern formed on a scribe line, especially an alignment that increases alignment accuracy. Tag pattern. Background of the Invention: Semiconductor manufacturing processes have always favored space-saving designs. Currently, two, three or more layers of interconnect manufacturing technology are used, and the number of components required to perform a function is gradually reduced. For example, six transistors were required in the early days. DRAM can now be replaced with a transistor and a capacitor.

經濟部中央標準局貝工消費合作社印$L -------^---Ί褽! (請先閱讀背面之注意事項再填寫本頁) 對準(alignment)是確保半導體製程中上層膜層與底 層膜層對準之主要方法,囡爲於半導體製程時有多層之内 連線形成於基板之上’假如其中有_層膜層沒有對準則將 造成製程之錯誤。對接觸窗之蝕刻、光阻之微影、膜層之 沈積一般均有數個對準標記圏案(align mark pattern)形 成於晶片之上以利製程之對準,膜層間之對準準確性是考 慮該層與對應膜層間是否有依要求之方式配合,爲了此目 的因此使用了對準標記圖案(align mark pattern),一般 而T,上述之對準標記囷案形成於晶片切割道(scribe line) 之中或之上。 本紙張尺度適用令國國家標準(CNS ) A4規格(210X297公釐) 417272 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明() 如第一圖所示,對準標記圈案1〇通常爲一十字形圖 案形成於一墊層(pa(H aye 〇 12之中或之上,該垫廣12是 於製程時形成於晶片之切割道之上,典型之切割道寬度小 於100微未。於對準程序時,一光束由X方向與γ方向掃 描以偵測對準揉記圖索1 0之位置以確定是否有對準。參 閲第二圏,當光束由X方向輿γ方向掃描時,囡十字形對 準襟記圖案10與墊層12間有落差因此於設備之監控器 上有一尖峰16出現’上述之整_層(pa(j layer) 12可以由金 屬、複晶梦或是介電質所組成。 不幸地,墊層(pad layer)12之邊緣與切割道之間亦 有落差,®此當光束由Y方向掃描時,此情沉產生之干擾 訊號因此也會於設備之監控器上有尖峰18出現。有些情 況之下,尖峰16、18之強度非常接近,囡此將會造成對 準之失敗。 發明目的及概述: 本發明之主要目的爲提供一種增進半導體製程對準 準確性之對準標記圖案。 本發明之對準標記圖案包含一十字形囷案與兩個具 有波形之水平線圉案,該對準標記圖案形成於切割道之 上》上述之十字形圖案包含一平行於切割道之水平線圈案 與垂直於切割道之垂直線圏案,具有波形之水平線圖案爲 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨0X297公釐) 1-f,' "^―装 , (請先閎讀背面之注意事項再填寫本頁} 417272 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明() 平行於切割道之圖案,上述之水平線圖案中點分别連接於 垂直線圖案之兩端,該水平線圖案與垂直線圖案連接之一 面具有重複之波形圖案用以改變干擾訊號之波形’任何適 合之波形均可例如三角波、方波、鋸齒狀波’本發明之對 準標記圖案可以準確地判定何者爲正確之訊號,因此本發 明利用改變干擾訊號之波形以以利於判定而增進半導體 製程對準準確性。 圖式簡單説明·· 第一圖爲傳统對準標記圖案之俯視圖。 第二圖爲傳统對準標記圖案訊號與干擾訊號之圖形。 第三圖爲本發明之對準標記圖案之俯視圖° 第四圈爲本發明之對準標記圖中鋸兹狀圈形。 第五圖爲本發明對準標記圖案訊號與干擾訊號之圖形。 發明詳細説明: 本發明利用改變干擾訊號之波形以以利於判定而增 進半導體製程對準準確性,爲了達到此目的一種對準標記 圖索將於下述。 參閲第三圖,本發明之對準標記圖案包舍一十字形圖 案10a與兩個具有波形之波形水平線圖案20a,該對準標 記圖案形成於切割道之上。再參閱第三圖,上述之十字形 ▼---^^------訂------鍵 (請先閎讀背面之注意事項再填寫本頁) 本紙張尺度適用争國國家標準(CNS ) A4規格(210X2?7公釐) 417272 A7 — B7 五、發明説明() f請先閲讀背面之注意事項再填寫本頁} 圖案10a包含一平行於切割道之水平線圖案12a舆垂直 於切割道之垂直線囷案14a,水平線圖案12a與垂直線圈 案14a之線寬爲2至3微米,當然任何合適之線寬亦可以 應用於本發明。 波形水平線圈案20a爲平行於切割道之圖索,波形水 平線圖案20a主體宽度爲2微米,上述之波形水平線圖案 2 0a中點分别連接於垂直線圉案14a之兩端,該波形水 平線圖案20a與垂直線圖案i4a連接之一面具有重複之 波形圖案22a用以改變干擾訊號之波形,當掃描光束掃描 對準標記囷案時’波形闺索22a將干擾其择描結果而改變 原先之干擾訊號,任何適合之波形均可例如三角波、方 波’本實施例之波形爲鋸齒狀之波22a,如第四圖所示, 該錄兹狀波22a之高Η、寬w均爲3微朱,錄兹狀波22a 間之齒距D约爲3微米》 經濟部中央標準局員工消費合作社印製 參間第五圈’當掃描之光束由Y方向掃描時,對準之 波形16a與干擾波形18a均由對準標記圖案產生,由囷中 可知,傳统之干擾波形18之波形已被轉變爲干擾波形 18a’因此可以準確地判定何者爲正確之訊號,因此本發 明利用改變干擾訊號之波形以以利於判定而增進半導體 製程對準準確性。 本發明以一較佳實施例説明如上,而熟悉此領域技藝 本紙張尺度適用令國國家標準(CNS ) A4規格(210 X 297公釐) 417272 A7 B7 五、發明説明() 者,在不脱離本發明之精神範面内,當可作些許更動滴 飾,其專利保護範面更當視後附之申請專利範圍及其等同 領域而定。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 本紙張尺度適用t國國家標準(CNS ) A4規格(210 X 297公釐)$ L ------- ^ --- Ί 褽! (Please read the precautions on the back before filling out this page) Alignment is the main method to ensure the alignment of the upper layer and the lower layer in the semiconductor process. For the semiconductor process, multiple interconnects are formed on the If there are no layers on the substrate, there will be process errors if there are no film layers. The contact window etching, photoresist lithography, and film deposition generally have several alignment mark patterns formed on the wafer to facilitate the alignment of the process. The alignment accuracy between the films is Consider whether the layer and the corresponding film layer cooperate according to requirements. For this purpose, an align mark pattern is used. Generally, T, the above-mentioned alignment mark pattern is formed on the wafer scribe line. ) In or above. This paper size applies the national standard (CNS) A4 specification (210X297 mm) 417272 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () As shown in the first figure, the alignment mark circle 1 〇Usually a cross-shaped pattern is formed on a pad (pa (H aye 〇12). The pad 12 is formed on the scribe line of the wafer during the process. The typical scribe line width is less than 100 micrometers. No. During the alignment procedure, a light beam is scanned in the X direction and the γ direction to detect the position of the alignment map 10 to determine whether there is alignment. See the second point, when the light beam is shifted in the X direction and γ When scanning in the direction, there is a gap between the cross-shaped alignment pattern 10 and the cushion layer 12, so there is a spike 16 on the monitor of the device. 'Pa (j layer) 12 can be made of metal or polycrystalline Dreams or dielectrics. Unfortunately, there is also a gap between the edge of the pad layer 12 and the cutting path, so when the light beam is scanned in the Y direction, the interference signal generated by this emotion will also be A spike 18 appears on the device's monitor. In some cases The peaks 16, 18 are very close in strength, which will cause alignment failure. Purpose and Summary of the Invention: The main object of the present invention is to provide an alignment mark pattern that improves the alignment accuracy of semiconductor processes. The alignment of the present invention The mark pattern includes a cross pattern and two horizontal line patterns with a wave shape, and the alignment mark pattern is formed on the cutting line. The above-mentioned cross pattern includes a horizontal coil pattern parallel to the cutting path and perpendicular to the cutting path. The vertical line pattern, the horizontal line pattern with the waveform is based on the Chinese paper standard (CNS) A4 specification (2 丨 0X297 mm) 1-f, '" ^ installation, (please read the note on the back first) Please fill in this page again for the matter} 417272 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () The pattern parallel to the cutting path, the midpoint of the above horizontal line pattern is connected to the two ends of the vertical line pattern respectively, the horizontal line The pattern and the vertical line pattern are connected on one side with a repeating wave pattern to change the waveform of the interference signal. 'Any suitable waveform can be a triangular wave, Square wave, sawtooth wave 'The alignment mark pattern of the present invention can accurately determine which is the correct signal. Therefore, the present invention utilizes changing the waveform of the interference signal to facilitate the determination and improve the alignment accuracy of the semiconductor process. The first image is a top view of a conventional alignment mark pattern. The second image is a pattern of a conventional alignment mark pattern signal and an interference signal. The third image is a top view of the alignment mark pattern of the present invention. The fourth circle is the present invention. The fifth figure is the pattern of the alignment mark pattern signal and the interference signal according to the present invention. Detailed description of the invention: The present invention utilizes changing the waveform of the interference signal to facilitate judgment and improve the semiconductor process pair. Quasi-accuracy, to achieve this purpose an alignment mark chart will be described below. Referring to the third figure, the alignment mark pattern of the present invention includes a cross pattern 10a and two wavy horizontal line patterns 20a, and the alignment mark pattern is formed on the cutting track. Refer to the third picture again. The above-mentioned cross-shaped ▼ --- ^^ ------ Order ------ key (please read the precautions on the back before filling this page) National Standard (CNS) A4 Specification (210X2 ~ 7mm) 417272 A7 — B7 V. Description of Invention () f Please read the notes on the back before filling this page} Pattern 10a contains a horizontal line pattern 12a parallel to the cutting path. The line width 14a of the vertical line perpendicular to the cutting path, and the line width of the horizontal line pattern 12a and the vertical coil line 14a are 2 to 3 microns. Of course, any suitable line width can also be applied to the present invention. The waveform horizontal coil case 20a is a picture parallel to the cutting path. The main width of the waveform horizontal line pattern 20a is 2 micrometers. The midpoints of the waveform horizontal line pattern 20a are connected to the two ends of the vertical line pattern 14a. The waveform horizontal line pattern 20a One side connected to the vertical line pattern i4a has a repeating wave pattern 22a to change the waveform of the interference signal. When the scanning beam scans the alignment mark case, the 'waveform cable 22a will interfere with its selection result and change the original interference signal. Any suitable waveform can be, for example, a triangular wave or a square wave. The waveform of this embodiment is a sawtooth wave 22a. As shown in the fourth figure, the height and width w of the recorded zigzag wave 22a are both 3 μ Zhu, recorded. The tooth pitch D between the zigzag waves 22a is about 3 microns. "The fifth circle printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. When the scanned beam is scanned in the Y direction, the aligned waveform 16a and the interference waveform 18a are both It is generated by the alignment mark pattern. It can be seen from the figure that the waveform of the traditional interference waveform 18 has been transformed into the interference waveform 18a '. Therefore, it is possible to accurately determine which is the correct signal. To change the waveform of the interference signal is determined to facilitate the alignment and enhance the accuracy of the semiconductor manufacturing process. The present invention is described above with a preferred embodiment, and the paper is familiar with the art in this field. The paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) 417272 A7 B7. Within the spirit scope of the present invention, when some changes can be made, the scope of patent protection should be determined by the scope of the attached patent application and its equivalent fields. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper size is applicable to National Standards (CNS) A4 (210 X 297 mm)

Claims (1)

417272 AS BS C8 D8 申請專利範圍 包 案 圖 記 標 準 對 該 案 圖 記 標 準 對 之 程 製 體 導 半 種 含 之 準 對 中 程 製 爲 做 以 用 上 之 道 割 切 於 成 形 案 圖 形 字 該 字 圖 包 有 圖 線 案案十圖 請複 圖圖該之 申重 ,線擾與形 如爲 用平干别波2.形417272 AS BS C8 D8 Patent application scope package diagram standard If you have a picture of the case, please repeat the figure. The line interference and the shape are as follows: 分有 上具 之上 道索 #圖 波 之 述 上 中 水及 該-, ,直 案垂 圖道 線 波 之 述 上 中 其 , 案 圖 記 標 準 對 之 項 T— 第 0 範 利。 專波 請角 申三 如爲 3 形 波 之 迷 上 中 其 案 圖 記 標 準 對 之 項 1 第 圍 範 專。 請波 申方 如爲 4形 (請先閲讀背面之注意事項再填寫本頁) .装- -9 經濟部中央標準局員工消費合作社印衷 波 之 述 上 中 其 案 圖 記 標 準 對 之 項 第 圍 範 利。 專波 請齒 申錯 如爲 5.形 鋸 之 述 上 中 其 9 案 圖 記 標 準 對 之 項 5 ο 第米 圍微 範3 利爲 專約 請高 申之 如波 6.齒 本紙乐尺度適用中國國家插準(CNS ) A4規格(210X297公釐) 經濟部中央標準局負工消費合作社印製 417272 as C8 D8六、申請專利範圍 7. 如申請專利範圍第5項之對準標記圖案,其中上述之鋸 齒波之寬約爲3微米。 8. 如申請專利範圍第5項之對準標記圖案,其中上述之 鋸齒波之齒距约爲3微米。 9. 如申請專利範圍第1項之對準標記圖案,其中上述之十 字形圖索水平線圖案之線寬约爲2至3微米。 10. 如申請專利範面第1項之對準標記圖案,其中上述之 十字形圖案垂直線圖案之線寬约爲2至3微米。 11. 如申請專利範園第1項之對準標記圖案,其中上述之 干擾圖案之線寬約爲2微米。 12. —種半導體製程之對準標記圖案,該對準標記圖案包 含: 一十字形圖案,形成於切割道之上用以做爲製程中對準之 用,該十字形圖案包含有水平線圖案與垂直線圖案,該水 平線圖案與切割道平行,該垂直線圖索與切割道垂直;及 兩個干擾圖案,該干擾圖案與切割道平行形成於切割道之 上分别與該十字形圖案之垂直線兩端連接,該干擾圖案上 具有重複鋸齒狀波形形成於該干擾圖案與該垂直線連接 面上用以增進製程之對準準確性。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐}There are 上 上 上 道 索 # 图 波 的 上 上 中 水 and the-,, and the straight case vertical line of the line is described in the above, the case map standard pairs of items T — 0th Fanli. The special wave asks the corner Shen San to be a fan of the 3-shaped wave. The standard of the plan of the case is the right one. Please ask Boshen if it is a 4-shape (please read the precautions on the back before filling this page). Equipment--9 Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economy Fan Li. The special wave asks for the wrong application of the tooth. If the shape saw is described above, the item 9 of the 9 plans in the standard is the right item 5 ο Mi Mi Wei Fan 3 The benefit is the contract, please Gao Shen of the wave 6. The paper scale is applicable to China National Interpolation (CNS) A4 specification (210X297 mm) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 417272 as C8 D8 6. Application for patent scope 7. If the registration mark pattern of item 5 of the scope of patent application, the above The width of the sawtooth wave is about 3 microns. 8. For the alignment mark pattern in item 5 of the patent application, the tooth pitch of the above sawtooth wave is about 3 microns. 9. As for the alignment mark pattern in the first patent application, the horizontal width of the zigzag horizontal line pattern is about 2 to 3 microns. 10. As for the alignment mark pattern in the first patent application, the vertical width of the cross-shaped pattern vertical line pattern is about 2 to 3 microns. 11. For the alignment mark pattern of the first patent application, the line width of the interference pattern is about 2 microns. 12. An alignment mark pattern for a semiconductor process, the alignment mark pattern includes: a cross-shaped pattern formed on a scribe line for alignment during the process, the cross-shaped pattern includes a horizontal line pattern and A vertical line pattern, the horizontal line pattern is parallel to the cutting path, the vertical line pattern is perpendicular to the cutting path; and two interference patterns, the interference pattern is formed in parallel with the cutting path on the cutting path and is perpendicular to the cross-shaped pattern, respectively The two ends are connected. The interference pattern has a repeating zigzag waveform formed on the connection surface between the interference pattern and the vertical line to improve the alignment accuracy of the process. (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) 々、申請專利範圍 13. 如申請專利範圍第12項之對準標記圖案,其中上述之 鋸齒波之高爲3微米 14. 如申請專利範圍第12項之對準標記圖案,其中上述之 鋸齒波之宽爲3微米。 15. 如申請專利範圍第12項之對準標記圖案,其中上述 之锯齒波之齒距爲3微米。 16. 如申請專利範圍第12項之對準標記圖案,其中上述之 十字形圖案水平線圖案之線寬爲2至3微米。 17. 如申請專利範園第12項之對準標記圖案,其中上述之 十字形圖案垂直線圖案之線寬爲2至3微米。 18. 如申請專利範圍第12項之對準標記圖案,其中上述之 干擾圉案之線寬爲2微米。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X29?公釐)范围 、 Applicable patent range 13. If the alignment mark pattern of item 12 of the patent application range, the height of the above sawtooth wave is 3 micrometers 14. If the alignment mark pattern of the item 12 of patent application range, the above sawtooth wave The width is 3 microns. 15. For example, the alignment mark pattern of the scope of application for patent No. 12, wherein the tooth pitch of the above sawtooth wave is 3 microns. 16. For the alignment mark pattern of the scope of application for item 12, the line width of the horizontal line pattern of the aforementioned cross pattern is 2 to 3 microns. 17. The alignment mark pattern of item 12 of the patent application park, wherein the line width of the above-mentioned cross pattern vertical line pattern is 2 to 3 microns. 18. If the alignment mark pattern of item 12 of the patent application range, wherein the line width of the above interference case is 2 microns. (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210X29? Mm)
TW86100445A 1997-01-16 1997-01-16 Align mark pattern in semiconductor manufacturing process TW417272B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743792B (en) * 2020-05-19 2021-10-21 力晶積成電子製造股份有限公司 Vernier mark for semiconductor manufacturing process and lithographic process inspection method using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743792B (en) * 2020-05-19 2021-10-21 力晶積成電子製造股份有限公司 Vernier mark for semiconductor manufacturing process and lithographic process inspection method using the same

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