TW426832B - Central processing unit having an extension instruction - Google Patents

Abstract

A central processing unit having an extension instruction comprises a memory address, an offset and a fixed length instruction of varying immediate data. The central processing unit comprises a general register, a special register, a register file constituted as an inner register, a function block for executing the calculation function; an instruction register for memorizing the instruction, a control block for generating/outputting a control signal to the instruction register and a plurality of status flags, in which the special register enables a programmer to be accessed thereto and includes only an extension data field for memorizing extension data or an extension register having the extension data field as one element and an extension flag for changing its status when the instruction memorizing the extension data in the extension register is executed and having one or a plurality of bits that a programmer is accessible.

Description

Printed by employees of the Ministry of Economic Affairs, Bureau of Intellectual Property and Finance, printed by Fi 426832 A7 _____ B7 _______ V. Description of the invention () '--- Field of invention:… The invention relates to the provision of central processing with fixed-length instructions. Zhuo Yuan ^ Change 1 Jiyi body pull site 1 offset and immediate data. BACKGROUND OF THE INVENTION As shown in Figure 5 *, a traditional central processing unit contains a register of 7'g which contains a GPR (general purpose register) that is structured to fit a structured area for use. One can easily access and an SPR (Special Purpose Register) for special purposes; an instruction register 4 for latching instructions filled by the memory;-a decoding / controlling section 5 for Decode a 10p code and an operand, which is locked in the instruction register 4 (part h) is also used to generate a predetermined control signal according to an instruction; an arithmetic part 6 is used to process the decoded Instructions in the decoding / controlling section 5; a memory data n register 1 $ when writing data in the memory or reading the data from the memory 'to latch and flush the data; a memory address register 2 For latching / outputting an address calculated in the program calculator: and a control signal register 3 'for buffering the control signal from the outside source. The designation of the central processing unit represented by the configuration of the base unit is called "machine language", which contains an OP code to represent the role, and an operand is the target of the action performed by the OP code. Add command 'As an example of oop code and operands, A = B + c, add B and C and store the result here, where 1 + 1 is a QP code' to represent the operation, and I1 and 'B' and 'c' is an operand, as an object to be calculated on it. And, the representation can be represented by a machine language, for example, the note size on page 4 applies the Chinese national standard (CNS> A4 specification (210x297) ) ----- ^ --- 1 --- 1 ------ Order ------ line (please read the notes on the back before filling in this page) A7 42683 2 V. Description of the invention () '0001 0000 0001 0010 ,, 0001, represents — double ~ 〇P code, its # &, symbol represents. _000 ,,' 0001, and 0010_ equal parts' A + ^

And C are symbolized. Generation of binary numbers A * B

乂 乂 is often used as a hexadecimal number ’because the binary number is too long and very ~ ten,, 'Leave. In the above example, the representative of the ten-digit decimal number becomes 'Ox. In, in this machine language, the operand contains a register' and a memory location. ~ Pseudo-shift and immediate. In many examples, the number of registers is limited to 32. For example, if the number of registers is 16, it can be used as a 4-bit operand (2 "4 = 16). However, when the memory address, _„ „— j2 bit central processing early 7G can use 4G bytes of memory. It will require the bit address as its representative. Therefore, the operand length that defines it becomes longer, and in offsets and immediate data, the operand length is used as the memory. Becomes longer than if the length of the operand becomes longer, 'the length of the machine code is also longer than the length of the machine language', the size of the program increases and the efficiency becomes worse. For these reasons, each central processing unit should have a technical method, 803 86 used in iBM personal computers to effectively represent this operand 3 has multibyte length instructions. For example, the instruction machine language 'MOV' of 803 86 is defined based on the operand length as follows: MOV AL! 12 BO 12 MOV AX '1 2 3 4 — B83412 MOV EAX' 1 2345678 — 66B8 78 56 34 n At the same time, the MC68000 has a number of 16-bit length instructions similar to 8086. It can be changed as described above. The length instruction has the ability to represent-operation Zhang scale is applicable to China National Standards (CNS) Α4 specifications (2) 0 × 297 mm) (Please read the notes on the back before filling out this page. Bureau ’s consumer cooperation printing 7i 4 268 3 2 A7 -_______ Β7 V. Description of the invention () Any advantage of length, but its disadvantage is that it becomes difficult to handle instruction decoding and exception status, because the length of the machine language is changed The central processing unit with variable-length instructions is called CISC (Complex Instruction Set Computer). On the other hand, in RISC (Reduced Instruction Set Computer), the length of the machine language is fixed = For example, 'MIPS-R3000, SPARC, ARM-7, etc. have a 102-bit fixed-length instruction 'sh_3 manufactured by Hitachi has a 16-bit fixed-length instruction. These fixed-length instructions make the decoding of instructions' exception handling and the use of management routes easy, Achieving the high performance of the central processing unit 'because of the fixed length of the machine language. Conversely, because the instruction length is fixed', it is accompanied by a pair of operands For example, MIPS-R3000 has a 32-bit memory. However, the representative of a bias in machine language is a 16-bit, and it is a 32-bit central processing unit. The length is limited to 16 bits. Therefore, it becomes the reason for the difficulty in programming and the decrease in efficiency-~~ * 〇 At the same time, the instruction of 'MOVE is an operation for copying-each in the scratchpad A register, where the register operand has a length of 5 bits, because MIPS-R3000 has 32 registers. Assuming that the operation code for the move is defined as 6 bits, fixed-length instructions can be defined as 16-bit instructions. However, in order to use a fixed-length instruction, a 6-bit representative instruction may be represented as a 32-bit instruction. However, 32-bit fixed-length instructions have the disadvantages of limited operand length and unnecessary lengthy instructions. Take TR-4101 as another example. 'TR-4101 has a 16-bit solid __ _ page e paper size Gu; Guan Jia Pi (CNS) 8 4 secret (2 丨 0X297 mm 7 " I ______ _ ______ -n _ nn IKT nnnn II (please read the precautions on the back before filling this page) 426832 A7 ________B7 V. Description of the invention () Fixed-length instructions and extended part of the functions of fixed-length instructions and operands. For example, A command 'LO AR forces data to be retrieved from memory, the command contains a 0P code' to represent, LOAD, and a target register to retrieve and store on behalf of a register, an index temporary The register indicates an operand and the location of the memory 'and' an offset operand represents an offset from the operand and the index. In order to represent these Op codes and various operands on a 16-bit length instruction, TR -4 1 〇1 Limits the offset to 5 bits. The 5-bit offset is not enough to represent the memory location ^ Therefore, TR-4 1 0 1 uses one, which means that the 0 extension t instruction contains 5 bits. OP code and 丨 丨 bit immediate constant operand. Here, the 11-bit immediate constant operand It is interpreted based on the fact that the 'instruction' is not a single instruction. For example, when 扩充 〇AD is to extend the next instruction of τ, 'instruction ΝΤΤΝΙν < η-bit real-time constant operand and instruction 5 bits Yuan offsets are connected to each other to represent 16 digits_difficult. The Ministry of Economic Affairs and Intellectual Property Co., Ltd. 4¾ printed the TR-410 丨 instruction expansion technology only expands the offset and the immediate constant becomes a 16-bit Limits on the length of operands in traditional RISC central processing units. Operands can be extended to make instructions based on the appearance of the instruction 'EXTEND'. Linked to—from the previous instruction 'EXTEND' A command is taken into consideration. In other words, in the command 'EXTEND, the next exception processing has the disadvantage of being unable to operate, and cannot be processed immediately in response to the requirements of peripheral equipment. Therefore,' to solve these disadvantages and problems > The system provides a central processing unit, which has an extended instruction, which can be applied to the Chinese standard (CNS) standard (210X29? Mm) ^ 1 ^^^ 4 268 3 2 V. A7 B7 Invention description () and the advantages of RIS C to represent memory addresses of all lengths' and offset and real-time data to simplify the use of instruction decoders with fixed instructions' and make exception handling easy ' This simplifies a pipeline and MU (memory management unit). Another object of the present invention is to provide a central processing unit with an expansion instruction to enable return to the next routine 1 to process the expansion instruction ' Which extended instruction processing is stopped after executing an exception handler 'even if an exception occurs next to the extended instruction. Aim1's purpose and overview: In order to achieve these goals, a central processing unit with an extended instruction, including a register file, a small-scale memory unit, a set of registers, where the access speed is fast; a内 汇流 #, connected to the register file to send / receive information: a foreign exchange bus buffer is connected to the internal bus to connect to a foreign exchange bus; a function block is connected to the internal bus and used to perform calculation functions ; A command register is connected to the internal bus and used to memorize the instructions in the executed program; a control block is connected to the instruction register and used to interpret the instruction and generate / output a control signal to the register file 'internal bus 'Forex stream buffer, function block and instruction register; and one or more status flags to represent the status of the calculation result of the function block' The state of the instruction register controls the state of the block, where the register flag The program contains one or more accessible general states for storing calculation source data and calculation results and memorizing them in memory addresses, and one or more special registers It is used to recall the information required for the operation of the central processing unit, and a bite page 8 (please read the precautions on the back before filling in this purchase), printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * 4 268 3 2 A7 B7 V. Description of the invention (most internal registers are used to memorize, and the special functions required for the operation of the processing unit are not accessible to a program planner. In the strong register, Next to the calculation intermediate procedure, the status flag contains the status flag that can be accessed by the program planner, and a program counter, using a program performed by a special register < memory address; program The address of the program pointed from the mountain χ ~ punch counter is output to the internal bus; output to .. ,, ^ L called the program address is output to the memory process through the foreign exchange buffer, Yiwai C The memory address; the instruction is output from the external memory v indicated by the above & Wanfa and transmitted to the internal memory via the foreign exchange buffer; the instruction is, ... Existed? Explained to the control The instructions in the register in the box—the temporary storage ^., To generate a control signal ’to execute a command and change a related status flag, and the keys stored in the instruction register and interpreted in the control block

7 D0 is used to represent the 0P code or 0P code of the operation and an operator block. The I ^ rule of the majority block is calculated by the system operation printed and returned to the system by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: 0PM operation. The element contains—or most of the binary bits, where the operand is interpreted / executed to represent the memory address—the address operand 'represents the bias of the memory address stored in the general register or the special register | An immediate constant operand is used to calculate or memorize the bit position or control, or an instantaneous register operand that represents the scratch register, etc .: The number 1 contains:-extended register, only-extended data Column, or an expansion register with expansion data, as a component for storing the expansion data in an accessible register, the accessible register contains the expansion data representing 1 The instruction of the 0P code of the operation of the constant operand in the extended data register of the extended register is explained in the control block. ° The memory body is the constant data element of the extended register in the extended register of the extended register. ----- Page 9 The scale remote wealth national scale (CNS) A4 · (2lQx297 public director) ^ 268 3 2 V. Description of the invention (A7 B7 'The expansion instruction contains 0p ^ Extend the operation column in the Japanese order to the expansion data in the expansion data 1 in the expansion register to form -port.yunyi palm and be interpreted / execute the instruction with the new operation block. 5 Dagger ° The correction instructions in the op code and the different element column link the expansion data stored in the expansion data of the 2 register copper to the correction finger: operator 襕 'to form -new finger +, so that the newly formed instruction can be interpreted. At the same time, according to the present invention, the central processing unit with an expansion instruction includes # non-flag to represent the two states of the expansion data column of the expansion register: it contains the data that the programmer has accessed. The state of one or more bits: the flag * contains the data used to represent the memory expansion data in the expansion register "the operation of expanding the data block and immediate constant operands". The 0P code is interpreted in the control block to remember Instantaneous constant operands are stored in the expansion temporary R expansion Fill the data and execute it in the 'box' to change the status of the expansion flag. The H 0P code and the operands of the extensible instruction are interpreted / executed according to the status of the expansion flag. The instruction of the operand block in the instruction, or the expansion data linking the operation column contained in the expandable instruction to the expansion data block stored in the expansion register, is expected to form a new operand shed and be interpreted / Execute is an instruction with a newly formed operation to execute the expandable instruction in the control block and change the status of the extension flag. 'The present invention includes a central processing unit and an extension register ER to represent the extension temporary. Register state organization, an instruction to store a paper size applicable to China National Standards (CNS) Eighty-fourth Secret (2! Ox 297 public director) (Please read the precautions on the back before filling this page) Order the Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperatives page 10 Printed by the Ministry of Economic Affairs ’s Smart Finance 4 Bureau employees' fee cooperatives 4 2 68 3 2 4, A7 B7 V. Description of the invention () Values in the ER, and an instruction to force calculations Motoki Extended register to the state of 0 is explained inventions can be achieved with a fixed length. The central processing unit of order, and changing the length of the address, i.e. the offset, and constants used in a memory. Brief description of the drawings: The present invention will be described with reference to the accompanying drawings, wherein: Fig. I is a block diagram of a central processing unit according to the present invention. Fig. 11: Fig. 2 is a block diagram of the operation of the pipeline of the central processing unit. Figure 3 is a timing diagram ^ illustrates the execution of instructions and decoding of the pipeline. Fig. 4 is a block diagram illustrating an instruction format in which the expansion flag is set to a state flag. Fig. 5 is a block diagram illustrating the central processing unit of the prior art. 1 Memory data register 2 Memory address register 3 Control signal register 4 Instruction register 5 Decoding / control section 6 Operating system 7 Register file 1 0 Data latch section 20 Pre-instruction register 3 0 pre-decoder 40 instruction register 50 decoder / control unit 60 arithmetic logic description unit 70 division / multiplier 80 register file 90 address generation unit (please read the precautions on the back before filling this page) 11 pages of this paper are in accordance with Chinese National Standards (CNS) A4 specifications (210X297 mm) 4268 3 2 Μ B7 ______. --- 5. Description of the invention () Detailed description of the invention: Figure 1 is a block diagram. An embodiment of a central processing unit with extended instructions according to the present invention, wherein the β-pass secret uses a 32-bit MCU. This may also allow MClJ to make a bus path and width expansion and reduction 'in the same way and its detailed blocks can be defined in various ways. However, the embodiment using a 32-bit MCU is for the purpose of simplifying the description. According to an embodiment of the present invention, a 32-bit central processing unit with an expansion command includes a register file S0, a 32-bit bus, a decoder / controller 50, and an arithmetic logic narrative unit 6 0 (hereafter referred to as ALSU), a multiplier / divider 70 and an address generation unit 90, wherein the instruction includes a 1 bit and uses a three-stage T line, and a memory structure includes four 8 bits The memories are connected to each other. From now on, the basic functions and operations of each unit of a 32-bit central processing unit with an extended instruction will be explained. When the system is first reset, the MC U reads the start address from a memory and stores it in the data latch section 103. Then, the address value is stored in the register file 80. Program counter (PC). As long as the program is performed sequentially from the following cycle, the value is increased according to the memory configuration. The address generating section 90 indicates the value and reads a program desired by the user from the memory. The address generation unit 90 selects the components equivalent to the following instructions and the data memory addresses, and uses them for program direction and non-sequence direction to read the instructions at the address and lock them in the previous instruction temporary. Register 20 'to carry out the program in order, or take out the necessary data from the memory, and lock it in the ________ page 12---------------- This paper Standards are applicable to China National Standards (CNS) A4 specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) Order the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, print the bones of the cooperative, and print the employees of the Ministry of Economic Affairs, the Smart Assets 4th Bureau Printed by the Consumer Cooperative 4268 3 2 Λ7 B7 V. Description of the invention () The material latches 10 to perform appropriate calculations. In fact, if the instruction starts to execute, the instruction for the pipeline is fetched into the pre-instruction register (PIR) 20. The pre-decoder 30 classifies the instruction into a large type. At this point, the large type is used based on the number of pipelines and the method to be executed, and the classification definition instruction becomes several similar types to determine the execution Which state transition is performed. Then the instruction is tied Locked in the instruction register (IR) 40. The decoder / controller 50 instructs the latch value and the output from = decode 30, and determines the state transition of the relative instruction to generate a control signal according to each state. 32 Bit ALSU60 and multiplier / divider 70 are actuated by the control signal to store their output results in register case 80. The detailed structure of register file 80 is shown in Figure 4. Temporary storage The device file 80 is divided into GPR and SPR. GPR is an area that can be easily accessed by the user and contains sixteen 32-bit registers. On the contrary, spR is a register. It is used for special purposes And includes a pc (program counter) 'an SP (user / supervisor stacking index), an LR (link register), an ML / MH (multiplication result low / high register), and an SR (status temporary Register) etc. The functions of LR 'ML / MH and SR in these registers are as follows: LR (Link Register): When a branch occurs in a non-sequential program flow, the value of the program counter as described above Stored in memory (stacked area)

I. Then, in the remote function, the operation for receiving the return address and the operation of the call leaf function can be easily operated. Considering these points, the 'address' is not stored in memory when calling the leaf function. Conversely, the 'link register' is used for its temporary storage. When the operation of the function is stopped by the above processing and address ___ page 3, this paper size applies the Chinese national standard {CNS) A4 specification (210X297 mm)------ ^ --- ^ --- -i, ------ Order ------ line (please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2 68 3 / at B7_ V. DESCRIPTION OF THE INVENTION When the () value is retrieved, the system performance is enhanced because the memory no longer needs to be read. ML / MH (multiplication result low / high register): In the MCU, there is a multiplier and divider. Therefore, these two registers are used to temporarily store their operation results. S R (state register): This register is used to store various state values in the calculation program in all MCUs. It is a collection of state flags representing the state of the central processing unit. The central processing unit having an expansion instruction according to the present invention further includes an expansion register (ER) in the register file 80 and an expansion flag representing the expansion status of the instruction. In this embodiment, the expansion register is arranged in SPR, but its address is not related to the address that any programmer can access, but it is located in SR in this embodiment. Expansion Register (ER): The expansion register is used to temporarily store a biased or immediate data value and generate a predetermined amount of operands. In this embodiment, the expansion flag representing the expansion register is included in the status register. The total length of the ER is changed according to the character length of the central processing unit and has a length of 16 bits or less in a 16-bit central processing unit, and a length of 32 or less in a 32-bit central processing unit. And 64 bits in a central processing unit equal to or less than 64 bits. Here, the 32-bit length of ER is explained as an example, but it should be noted that it tries to make the description easier rather than limiting the ER length and character length of the central processing unit. Page 14 The standard of this paper is applicable to China National Standards (CNS) Α4 specifications (2! 〇 X 297 Gong) ---- ^ ------- V .------ Order ---- --- line (please read the notes on the back before filling this page) 426832 A7 B7 V. Description of the invention (EF should be a shape with a length that exceeds the length that can be easily accessed by planners! Bits in the central processing unit Some flags and registers contain no (please read the notes on the back before filling out this page) and can be accessed by planners. In the embodiment of the present invention, it is not interpreted as the status register One official point. It is important to recognize the three positions and it should be considered that it is an implementation of EF that is not limited to # 1] EF. At the same time, the central processing unit of the present invention stores data in the ER and The extension flag (M) is included to represent the use and non-use of the expansion register, and separate instructions to effectively use ER 'without & using EF. In this embodiment, the example of' & EF being used is It is explained that the central processing unit of this month has the instruction 'to store data in ER at the same time' to set EF in the factory, which is called " Lderp, for convenience of explanation. At the same time, 'assuming that a 16-bit fixed-length instruction is used in a 32-bit central processing unit' and the instruction _LDERI, the operation system is defined as an M-bit immediate constant, the instruction sentence system It is as follows: LDERI # 123 智慧 The Intellectual Property Bureau of the Ministry of Economic Affairs and the Jeonggong Consumer Cooperative Co., Ltd. prints the arithmetic shift ER to the left by 14 bits and operates to add the '123' to the ER of the arithmetic unit. If EF is before the execution of the instruction = arithmetic shift It is an example of using the ER used in the present invention. In addition, there is also a method for filling an inefficient bit with an operand amount, and using an ER with an operand placed at a fixed position for each instruction , ER can be used by a method to allow planners to access various methods. If EF is _, 0 " Before executing the instruction, the central processing unit expands the '123, symbol, which is an operand part of the instruction. 'To complete a 32-bit and store it in the ER. In both examples' EF is set to " 1 s s page 15 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 Mm) 4? RB 3 2 A7 B7 V. Hair It is clearly stated that the length of the operand of the () instruction " IDERi " is determined according to the definition of another instruction, which does not limit its length in the present invention. If used for an immediate constant as an example of the operand in the instruction 'LDERI1' If it is adopted, it should be noted that different types of operands, such as a memory address, etc., can be used. For example, a p C relative addressing can be used. It means that the present invention can have one or more instruction mechanisms, using To load data into the ER. The central processing unit with extended instructions according to the present invention has the prior art of general instructions. Among them, an instruction that needs to change an operand is different in that it interprets the operands based on the EF state. For example, in a 32-bit central processing unit with a 16-bit fixed-length instruction, an instruction 'JMP' having an 8-bit fixed length is represented as follows: JMP Offset instruction 'JMP' is an instruction, using In order to change the sequence of the program, its execution positioning starts at the current program position offset next to the instruction. The run-out offset position is limited to -12 8 bytes to -12 7 bytes, because the offset length is specified by an 8-bit. In this example, it is based on the state of EF, and the offset is interpreted as 2. If ΈΓ is '01, the offset length is interpreted as an 8-bit. If 'EF1 is' Γ, the value of the arithmetic shift ER of the central processing unit is 8 bits to the left and then added to the 8-bit offset represented in the instruction to calculate the offset. Therefore, the operand system of the instruction is expanded to have a 32-bit offset. Example The method using ER is adopted, and the arithmetic shift method used in various ER using methods is adopted. The distance of moving ER to the left is different according to the instructions. = In the previous example, page 16 of this paper applies Chinese National Standard (CNS) Α4 specification (210XW7 mm) (Please read the precautions on the back before filling this page) Μ-, 1T Consumer Finance Department of Wisdom and Finance Bureau of the Ministry of Economics, Printed with DuPont ^ 268 3 2 Α7 Β7 V. Description of the Invention () Instruction 'LDERI' moves 14 bits, and instruction 1JMP1 moves 8 bits. EF The flag is changed to '1' by the instruction _LDERI 'and all instructions that indicate the EF register except the instruction' LDERI 'are, however, the EF flag can have different values depending on the method implemented, and' different implementations' , Represents the state of instruction expansion. Consider another example, when TDERI's operand length is 12 bits in a 64-bit central processing unit with a 16-bit fixed-length instruction, its hypothetical program operates as follows: LDERI #oprl: INSTRUCTION-1 LDERI # opr2: INSTRUCTION-2 LDERI # opr3: INSTRUCTION-3 LDERI # opr4: INSTRUCTION-4 JMP Offset: INSTRUCTION-5 Assume that the EF before INSTRUCTION-Γ is 0, and ER has a Extends the symbol of 'oprl · to a 64-bit element' INSTRUCTION-11 ', and EF becomes' Γ in 'INSTRUCTI0N-1_' and has a value of 'opC'. It is used in ER, such as arithmetic shift To the left is also an example. At the same time, if an exception occurs, the exception processing should be performed in advance without having to execute, INSTRUCT ION-3, in the central processing unit with extended instructions according to the present invention, because EF and ER are It is a register and is planned to allow programmers to access' the content can be retained in the stack and buffer stored in memory. After the exception processing is completed, if stored in the stack and memory, ER and EF are reloaded as iNSTRUCTION-3. The next page of this page applies to the Chinese National Standard (CNS) A4 specification (2! (TX 297 mm). (Please read the precautions on the back before (Fill in this page) -1Τ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives 426 8 3 2 A7 B7 Printed by the Intellectual Property of the Ministry of Economic Affairs ε-R Industrial Cooperative Cooperatives 5. Inventive Instructions () The instructions can be properly implemented. At the same time, even if Exception When another exception occurs, ER and EF are sequentially stored and reloaded to ensure the correct execution of the program. 'INSTRUCTION-5, the offset length is 48 bits' leading enemy, INSTRUCTION-l_ to The arithmetic units of INSTRL'CTI0N-4_ are added to each other, in which all 8-bit offsets of instruction-s' are added to obtain a length of 56 bits. As a result, the central processing unit having the extended instructions according to the present invention is considered to be that all instructions have a fixed length and are executed independently and can have variable length operands. Fig. 4 is a block diagram illustrating a register file structure and an instruction format, in which an expansion flag is set according to an embodiment of a central processing unit having an expansion instruction. As shown in the figure, each bit of a state register represents a predetermined state. Here, it should be noted that the 19th bit is an extended flag as described above, which determines that the next instruction adopts a shorter value or an extended value as the -offset bit-immediate value. Of course, in the one-bit embodiment of the state register, for example, the 19th bit system is used as a flag, but it can only have-examples can be actually implemented in hardware through various methods. Fig. 2 illustrates an example of how the pipeline used for the MCU in this embodiment operates. As mentioned above, the “three-stage pipeline fetching-decoding-executing system” is used. This means that the instruction fetched for each cycle is called, the symbol 罡 J is called + the host system is uncovered, decoded and executed. LD / ST It is an instruction, which is composed of regret sleeves.) U? Buy / write data. This memory also needs a companion segment to obtain-right w double address. At the same time, the 'Central Processing Unit' assists multiple shift instructions without running requests, except that the paper dimensions on page 18 apply the Chinese National Standard (CNS) A4 specifications (21 × 297 mm). Master then fill out this page)-支-= ° 织

, ^ 'Move' where the multiple system is an instruction, which cannot be redundantly executed in this single cycle, where a typical pipeline system represents the instruction. Figure 3 is a timing diagram of a pipeline that can be fetched, decoded and executed. To this end, the general computational flow of the present invention is discussed. Furthermore, the operation of the extended instructions in the 32-bit central processing unit according to the present invention will be described in detail as follows: When executed in a general order, 'there are no extended instructions mentioned above, an MCU performs the following two operations. When the instruction is generated. . First, the 9th bit system of the state register is changed to 丨 • ('0_ in negative logic). If the 19th register is set to, ", the next instruction detects the child flag. Then, if the instruction represents the operation of READ / WRITE, its operation forces the ER to indicate that it is a -bias value '. If the instruction is ALsu In the internal operation, the operation is expressed by the intensity ER as an immediate value. Second, the desired offset or immediate value is brought into £ R, which has two states. In the first state, the extended instruction system Is being used,

^ The value of ER has been used, even if the extended instruction is issued in advance, in the __ ^ state, the ER value has not been used. The extended instruction has been executed in advance to explain it. 'Assume that the extended instruction system is defined as follows. . — T ------ Order ------ Fate (Please read the notes on the back before filling out this page) Printed by the Ministry of Economic Affairs 4

*: IR [13: 0], immediate data sheet 1. Examples of extended instructions Page 1S The paper size is applicable to China National Standard (CNS) A4 specifications 210X297 mm A7 4 2 5-0 B7 V. Description of the invention () In the first example, the 14 bits shown in Table 1 are filled in the 13 bits of the 0 bit of the ER, and the most significant bits are filled with the most efficient bits of the immediate data. As a sign extension. In the second example, since 14 bits have been filled from 13 bits to 0 bits of ER, when shifting 14 bits to the left, keeping the value = · Arithmetic shift system is used as an example. In addition to this method, as described above, 27 bits to 14 bits can be filled for expansion, and 13 bits to 0 bits are held in itself. Through the above processing, repeated execution of the extended instruction can extend the offset and immediate value indefinitely. Furthermore, the operation of an instruction that can occur after the extended instruction will be explained. First, let's see how the instruction in the data shift instruction reads data from the memory or writes data to the memory and how it operates as a bit offset. The instruction will be as defined in Table 2 for the method description. see. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 & & & & U wood * * *%%%% &: IR [15: 12], OP-Code (Load / Storage ) #: IR [1 1: 8], origin / destination register *: IR [7: 4], offset data%: IR [3: 0], index register table 2, a 32-bit payload / Sample instruction example When the instruction is executed, the expansion flag of the 19th bit in the state register is first directed to a decoder 'control section 50. If the flag value is (negative page 20, the paper size is applicable to China National Standard (CNS) A4 size (210X 297 mm) ---- ---- ^ ---- R ------ order ------ line (please read the notes on the back before filling out this page) Intellectual property of the Ministry of Economic Affairs and employee cooperation ^ .; '·' " A7 426832 B7 V. Description of invention () Logic is' Γ ), The effective address represents one of the values added to the index register. Here, one item considers the data width of the memory, because various architectures are available. For example, four 8-bit memories can be connected in parallel to each other for user convenience, or two 6-bit memory can be connected in parallel with each other. As described above, it is assumed in the embodiment that four 8-bit memories can be connected in parallel with each other. At this time, when adding an offset, the offset value must be shifted to the left by two bits. Therefore, the inefficient two bits are meaningless because the current instruction to be executed is a 32-bit load / store instruction. However, when the flag value is '1' (when negative logic is W), it means that the expansion instruction is subsequently executed to shift the offset to be expanded to the ER. Therefore, the effective address shift ER value is four bits to the left, and the inefficient two bits of the four bits included in the instruction are shifted to the left by two bits to add the value of the index register to it. Then, obtain a valid address. Of course, the amount of ER to be shifted to the left is changed based on the definition, but here for consistency of instructions it is defined to shift by only 4 bits. In this example, a 32-bit load / store instruction causes an accessed user to be addressed until the index register +63. However, if the offset exceeds 63 ', the value exceeding 15 is shifted into the ER, and the expansion instruction and 32-bit load / store instruction are executed so that the user can access the desired address. This represents a simple arithmetic notation as follows: When the E flag is; EAe (zero extension [R [7: 4] & " 00 ") + Rindex When the E flag is '11; EA < i = (ER < < 4 & IR [5: 4] & " Ο Ο ") + R, n dex p. 21r, paper size adopts Chinese national standard CNS), \ 4 specifications (210X 297 mm) (Please read the precautions on the back before you fill out this page. Τ Ί The Ministry of Online Economy is smart every time! &Quot; Employee Consumption " Let's print 4 2 68 3? A7 B7 V. Description of the invention () Furthermore, consider when When the immediate data value of a data shift instruction is loaded immediately, the instruction will be defined as indicated in Table 3. 15 14 13 12 11 10 9 8 7 6 5 4 • η 2 1 0 IR [15: 0] & &! & & U -U. # # * * 丰 * t 木 * &: IR [15: 12], OP-Code (load immediate value data) #: IR [11: 8], purpose temporarily *: IR [7: 0], encoding immediate data table 3, an example of an immediate data instruction can be clearly seen in table 3, for example, a 7-bit immediate value with a sign '-256 to +25 5 can pass through this The load immediately instructs the load to the destination register. But If the desired immediate value exceeds the range of -25 6 to +255, the extended instruction is first executed to move the desired immediate value to ER 'then' the load immediate instruction is executed to obtain the desired immediate value. In this example, the load immediate instruction is latched to the instruction register 40. In order to execute it, the 19th bit of the state register is referred to as' when the decoder / controller 50 generates a control signal. If the flag value is' 0 '(negative logic is' 1'), the 7-bit immediate value in the instruction ', for example -2 5 6 to + 2 5 5 is loaded into the target register and left. Shift 4 bits' Then the inefficient 4 bits of the instruction are filled in the shift position to load an immediate value of the desired size. Of course, the ER amount to the left is shifted or filled into it The value can be changed based on the definition of the instruction. If the 32-bit immediate value is required by the defined instruction, the extended instruction is executed twice to move efficiently. Standard (CNS) A4 specification (210X 297 mm) ------ 1 --- Yes, --------- Order --- after (please read first Note the surface to fill out this page) 426832 A7 B7 V. invention is described in () bit into the ER. Thereafter, the load immediate instruction is executed to obtain the 32-bit immediate value. It is expressed as a simple arithmetic notation as follows. (#Read the notes on the back before filling this page) When the E flag is W;

Rdstf has a plus and minus extension of 1 foot [7: 〇] when the E flag is ‘Γ;

Rds t ¢ = E R < < 4 & IR [3: 0] The third, see the ALU instruction example, the instruction will be defined as shown in Table 4 below: 15 14 13 12 11 10 9 8 7 6 5 4 λ 2 1 0 IR [15: 0] & & & & & & & &## * Books &: IR [15: 8], OP Code (ALU instruction) #: IR [7 : 4], destination register *: IR [3: 0], if E, source register, except it is an immediate register Table 4 ALU instruction example Generally speaking, the operation of the ALU instruction is classified as The following are the following types of wisdom and wealth of the Ministry of Economic Affairs and Consumer Cooperation:; ']-type: ① Calculate two temporary registers ② Calculate the value and immediate value of a temporary register ③ Calculate a temporary register and a memory Content

But in the general RISC architecture, except for the load / store instructions, these cannot be accessed by the memory ". Therefore, in the architecture exemplified here, the ALU __Article 231: _ Zhang scale is applicable to the Chinese National Standard (CN'S) Λ4 specification (210X297 mm) 4 2 A7 B7 V. Description of the invention (Calculation is divided into two types according to the characteristics of general RIS C. As shown in Table 4, it represents an instruction ° ALU instruction is locked in the instruction temporary storage Device 40. When the decoder / controller 50 generates a control signal for execution, the E flag of the status register is indicated. If the E flag is _0 '(in positive logic), the instruction is indicated Calculation between two registers. If the E flag is 1 ', the instruction indicates the calculation between the value of a register and the immediate data. In the first situation, any of the' 1 6 registers is passed 4 The bit is selected from the third bit to the lowest bit of the instruction in order to perform the calculation with the destination register 9 (IR [7: 4]) so that the resulting value is recorded in the destination register. Conversely, In the second case, the destination register and the ER register are specified to add their contents to the immediate value. In other words, when the calculation is performed with the immediate data value, the extended instruction is first executed to shift a desired amount to the ER, and then the ALU instruction is executed. This example will be expressed in a simple arithmetic guard notation as follows: When the E flag is '0',

Rdst θ Rsrc + Rdst When the E flag is W ′,

Rdst0 (ER < < 4 & iR [3: 0]) 卞 Rd "Fourth, note that in the example of a branch, the instructions will be defined as shown in Table 5. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 IR [15: 0] 1 & & & & | & | & & & wood * 氺 * + &: IR [15: 8], OP-Code (branch instruction ) *: IR [7: 0], offset data table 5. The size of each branch instruction example is subject to the Chinese National Standard (CNS) Α · 4 specification (: M〇x297 mm (please read the precautions on the back first) (Fill in this page)

Description of the invention (Ministry of Economics, Smart Production, and Industrial Cooperative Printing may include various divisions of this person, Swordsman's Order, but the program counter (pc) related to the instruction is used as shown in Table 5 This is not the case. The instruction is locked in the instruction register 40. Only when the decoder / control unit is in control] 0 when the control signal for the instruction is generated, the 'E flag is also pointed at If the ^ 'T right E flag is' 0', then the 8-bit system with a sign is added to the program. Crying to fly ° Ten digits in the middle 3 For example -512 to +511 range can be branched to the program counter In this case, the reason is that the data length is 8 bits and the range is from -512 to +511. The reason why U 疋 is adopted is that the architecture in the embodiment uses 16-bit instructions and the ancient s > 7 and the four alarm systems with a data width of 8 被 are considered to be connected in parallel with each other. N Because the least significant bit is meaningless, because the least significant bit is filled with 0, the approximate bias value becomes 9 bits. Conversely, if the E flag is r, the ER register on the program counter is indicated to be added. In the setting,. ^ Zhong Youzheng address is branched. In other words, if the branched address is super ^ ~ w > 12 to +51 1 ', the expansion instruction is executed first to shift the desired amount. 'Then, the branch instruction is executed' to get the necessary offset. This example is represented by a simple arithmetic table TF as follows: When the E flag is 1 0 ', EA ¢ = 1 (with the sign I r [ 7: 〇] &, ◦,) + p 匸 When the E flag is '1', EA < = i (ER < &9; IR &7; IR [7: 0] & '〇') + pc to the present So far, in several typical instructions, the ^ Tearless instruction will be explained through some examples. Although it is not explained here, do, 'required instructions or extensions used in the same method as above' ' Immediately on page 2S This paper size applies to China® Home Standard (CNS) 'M specifications (2l0x 297 mm (please read the precautions on the back before filling in this purchase), -0 line. 4268,' A7 137 5. Description of the invention () is available, so the amount of expansion is not limited. Now look at what to do if an exception occurs when an expansion instruction is executed The core of the question is two items about how the state is maintained until the exception processing is completed if the exception occurs during the execution of the extended instruction, and how the offset or immediate value is restored after the exception processing. As mentioned above, the present invention uses An E flag and an ER to solve these problems. In order to implement these solutions, the ER system is placed in the SPR and designated in a bit of the state register to be used as shown in Figure 4. "1 flag. Of course, this is a simple example used to implement these solutions in various methods to implement the hardware of the present invention. According to the present invention, most MCUs are used to store some components in the stacking area to prevent the program flow from being lost before the exception when the exception occurs. The architecture of the embodiment simultaneously stores the values of the program counter and status register in the stack area. Therefore, when the values of the program counter and status register are retrieved, the present invention can solve the problem of the E flag value that is alleged to be related to maintaining the state. If the exception occurs when the extended instruction is executed, and the ER system can Obtained by software to shift the HR value to the stacking area. Before the exception processing, and then after the exception processing occurs, the ER value is restored from the daylight area. Please read the precautions before you fill in the f- :? This &: Order printed by the Ministry of Economic Affairs, Intellectual Property and Finance, Bureau of Industrial and Commercial Cooperatives, printed on paper standards applicable to the Chinese country # 准 （CNS） 4 4 (210 × 297 males)

Claims (1)

4 268 3 2 as Β8 C8 D8 6. Scope of patent application 1. A central processing unit with extended instructions. Zakiba contains a temporary register file, which is a small-scale memory unit with fast access speed. Collection; (" Read the notes on the first page, and then " This page} An internal bus is connected to the register to receive information from Iran'a 7; a foreign exchange is connected to the internal bus , To connect the outer a 丨 4 rows to it; a function block connected to the internal confluence #, and used to h. To execute the counting function; an instruction register is connected to the internal confluence wander. The instructions of the program in 忏; a control block is connected to the instruction temporary storage 涔 > and & and is used to interpret the instruction and generate / output a control signal to the register file, A steep flow, foreign exchange flow and functions Blocks and instruction registers; and one or four night number status registers, which are used to represent the state calculated by the function block, the status of the instruction register, and the state of the control block. The register file contains a bite majority General register for storing meter The source data and calculation result data are stored in the register that the programmer can access and the state to memorize the ship address, one or most special registers, used to memorize the central processing unit, " 丨 硌 < Information and special functions of printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, one or more internal registers, used to memorize the calculation of intermediate procedures required for the operation of the central processing unit, etc. In the register, the status flag includes a flag that the program planner can and cannot access, and a program counter, which is used to memorize the memory address of the program processed and stored by the special temporary storage benefit. The program address indicated by the counter is output to the internal bus; the program address output to the internal bus is output to the memory address where the program is stored via the foreign exchange buffer; the instruction is due to the above method The external memory is read out and transferred to the internal bus through the foreign exchange buffer; the instruction is stored in the instruction register, and the instruction register is resolved. Page 27 Paper size is applicable to China National Standards (CNS) 6 4 standard (210X297 public expense) Printed by Xiaoshen Co., Ltd., employee of the Central Standards Bureau of the Ministry of Economic Affairs 4? Β 8: i? Α8-8 ΒΒ C8 D8 VI. Patent application The scope is explained in one of the registers in the control block to generate a control signal to execute the instruction and change the related status flags. The instructions stored in the instruction register and interpreted in the control block contain only the 0. The P code or OP codes and an operand column have one or more operands related to the operation of the system operation; the 0 P codes and operands include one or most binary bits, where the operands are interpreted / executed Become an address operand representing a memory address, an offset operand representing a memory address offset stored in a general register or a special register, an immediate operand for calculating or memory address or control An immediate constant operand of a constant, or a register operand representing a register, etc., further includes: an extended register with only one extended column or an extended column as a memory Expansion register, which is a component of the expansion data in the register accessed by the program planner, which contains 0 P code, which represents the expansion in the memory expansion register and the expansion data in the immediate constant operand. The data operation instruction is interpreted in the control block. The immediate constant operand is memorized in the expansion data column of the expansion register. The expansion instruction contains the 0P code and the operand column connection is included in the expansion instruction in the control block. The operand blocks and memorizes the expanded data in the expanded data column of the expansion register to form a new operand column and is interpreted / implemented as a finger with a newly formed operand column. 02. As the first item in the scope of patent application The central processing unit described above, which includes the above-mentioned 0P code, which is used to represent the expansion of the memory expansion register. Page 28 This paper size applies to two countries in China (CNS) Λ4 specification (2IOX297). (Please First read the notes on the back to complete this page), 1T Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs ^ 4268 3 2 Ϊ8 (: 8 L > 8 That is, the instruction of the operation of the extended data of the constant operand is interpreted in the control box to memorize the constant constant operand in the extended data column of the extended register; and the above-mentioned modification including the oop code and the operand column The instruction is linked with the expansion data stored in the expansion data of the expansion register in the control block to the operands contained in the modification instruction to form a new instruction so that the newly formed instruction is interpreted and executed. 3. The central processing unit described in item 1 of the scope of patent application, wherein: the above-mentioned central processing unit further includes an expansion flag, which represents the status of the expansion data column of the expansion register, and the expansion flag is Contains one or more bits of one of the majority status flags and is accessible to the programmer. It contains operations to represent the memory expansion data in the expansion data block of the expansion register and the immediate constant operand. 〇P code is interpreted in the control block to memorize the constant constant operand in the expansion data column of the expansion register and execute it in the control block to change the state of the expansion flag; it includes the OP code and the operand column. Expansion instructions are interpreted / executed according to the status of the expansion flag. Instruction 1 with the only operand column contained in the expansion instruction in the control block is linked and the operands contained in the expansion instruction are blocked to the expansion stored in the expansion register. The data of the data block is expanded to form a new operand column and is interpreted / executed as a command with a newly formed operand column to execute the expandable instruction in the control box and Variable expansion flag state. Page 29 Medium-threshold National Standard (CRS) Λ4 specification (210X297 mm) is applicable to this paper standard (Please read the. &Quot; Issue on the back before filling this page) V-5 " 5 6 C \ J 4 ABCP Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards 6. Scope of patent application 4. The central processing unit described in item 1 of the scope of patent application, wherein: the above-mentioned central processing unit further includes an expansion register with a single extended data column or Expansion register with an expansion data column as a component for memorizing control data and expansion flags1 The expansion flag is a status flag containing one or more bits to represent the state of the expansion data of the expansion register One of them: The instruction containing the 0P code is interpreted in the control block, taking into account the immediate constant operand as a positive integer or the 2's complement based on the state of the expansion flag, in order to expand its extension register. The length of the extended data column. The 0P code is used to represent the extended data in the extended data column whose memory has a shorter length than the extended data register and the extended data column of the immediate constant operand. To make the immediate constant operand stored in the expansion register of the expansion register, or shift the expansion data column stored in the expansion register to the left by a predetermined length, linking it to the immediate constant operator, The expansion data is formed and stored in the expansion data register of the expansion register. The command for storing the expansion data in the expansion data column of the expansion register is executed in the control box to change the expansion flag. Status; The extended instruction containing the 0P code and the operator paste connects the operand contained in the extended instruction contained in the control block to the extended data stored in the extended data column of the extended register to form a new operand column And is interpreted / executed as an instruction with a newly formed operand column: and the extended instruction is executed in a control block and changes the state of the extended flag. Page 30 This paper size is applicable to China National Standards (CNS) Λ4 specification (210X25 »7mm) (#Read the precautions first and then fill out this page), = t 4 2 6 8 3 2 Λ8 HS C8 DS 6. Scope of patent application 5. The central processing unit described in item 1 of the scope of patent application, where: {Please read the precautions of the back two before filling out this page) The above-mentioned central processing unit also includes a single extended data An expansion register or an expansion register having an expansion data palm as a component that uses KA memory to control data and an expansion flag. The expansion flag contains one or more bits to represent the expansion data of the expansion register. One of the status flags of the status of the column, where: The instruction containing the 0P code is interpreted in the control block, taking the immediate constant operand as a positive integer or the complement of the 2 based on the status of the expansion flag, with Expand the extended column length of the extended register. The 0 P code is used to represent the extended column of the memory which is shorter than the extended column of the extended register and the extended column of the immediate f-number operator. Expansion of capital Operation, so that the immediate constant operand is stored in the filling column of the expansion register, or the expansion data stored in the expansion register is shifted to the left by a predetermined length, and it is linked to the immediate constant operand To form the expansion data and memorize it in the expansion data column of the expansion register; the staff of the Central Bureau of Standards of the Ministry of Economic Affairs printed the expansion instructions containing OP codes and operators to connect the expansion instructions stored in the control box The expanded data in the operand column in the table to the operand contained in the expansion register to form a new instruction so that the newly formed instruction is interpreted / executed; and the modified instruction is executed in the control block and changed Expand flag status. 6. The central processing unit as described in page] [J] of the scope of patent application, where: page 31 The paper size is applicable to China Standards Standard (CNS) Λ4 specification (210X297 mm) D8 D8 Staff of Central Ministry of Economic Affairs Cooperative printed 6. The scope of patent application The above-mentioned central processing unit further includes an expansion register with a single expanded data block or an expanded temporary block with an expanded data block as a component for memorizing control data and expanding flags. The flag is one of the state flags that contains one or more bits to represent the state of the extended data column of the extended register, where: The instruction containing the oop code is interpreted in the control box to take immediate consideration into account The constant operand is used as a positive integer or 2's complement based on the state of the expansion flag to expand the length of the extended column of the extended register. The 0P code is used to represent the extended column length of the memory compared to the extended register. The extended data operation in the extended data block of the short expansion register and the immediate constant operand allows the immediate constant operand to be stored in the expansion register. Fill in the data column or shift the expansion data stored in the expansion register to the left by a predetermined length, link it to the immediate constant operand to form the expansion data and store it in the expansion data of the expansion register In the palm; the instructions for storing the expanded data in the expanded data block of the expanded register are executed in the control block 改变 to change the state of the expanded flag; the expandable instruction system including the 0P code and the operand column is interpreted / Execute as an instruction with an operand column contained in an expandable instruction, or connect the operand contained in the expandable instruction to the expansion data stored in the expansion data register of the expansion register to form a new The operand is interpreted / executed as having a state based on the expansion flag. In the control block, a command for newly forming an operand column is formed; and the expandable instruction is executed in the control block and changes the state of the expansion flag. The 32th scale of this book applies to the Chinese National Standard Apple (CNS) Λ4 specification (mm) (please read the precautions before filling this page) Order 4 2 6 8 3 2 μ C8 D8 々, patent application park 7. The central processing unit described in item 1 of the scope of patent application, wherein: the above-mentioned central processing unit further includes an expansion register with a single expanded data block or an expanded data block as a memory control data and expansion flag The expansion register of the target component. The expansion flag is one of the state flags that contains one or more bits * to represent the status of the expansion data block of the expansion register. The following: The instruction system containing the 0P code It is explained in the control block, taking the immediate constant operand as a positive integer or the 2's complement based on the state of the expansion flag to expand the length of the expansion column of the expansion register. The OP code is used to represent the memory The expansion data block length of the expansion register which is shorter than that of the expansion register and the expansion data operation in the expansion data column of the immediate constant operand allows the immediate constant operand to be stored in the expansion temporary register. The expansion data column of the device, or the main or constant arithmetic element is stored in a predetermined position of the expansion data paste of the expansion register; printed by Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the first Please fill in this page for the matters needing attention.) The instructions for storing the expansion data in the expansion data column of the expansion register are executed in the control box to change the status of the expansion flag; including the 0P code and the operand column. The expansion instruction connects the operands contained in the expandable instruction contained in the control block to the expansion data stored in the expansion data column of the expansion register to form a new operand block and is interpreted / executed to have a new formation Instructions in the operand column; and the extensible instruction is executed in a control block and changes the state of the expansion flag. 8. The central processing unit as described in item 1 of the scope of patent application, where: page 33 The paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 cm) C8 m 6. The central processing unit described above in the scope of patent application It also includes an expansion register with a single extended data column or an expansion register that serves as a component to memorize control data and expansion flags. The expansion flag contains one or more bits to represent One of the status flags of the status of the expansion data column of the expansion register, where: The instruction containing the 0 P code is interpreted in the control block, taking into account the immediate constant operand as a positive integer or the status based on the expansion flag The 2's complement to expand the length of the extended column of the extended register. The 0P code is used to represent the extended register and the immediate constant operand whose memory has a shorter column length than the extended register. The extended data operation in the extended data column makes the immediate constant operand system be stored in the extended data of the expansion register, or the immediate constant operand system is recorded. Recall in one of the predetermined positions in the expansion data column of the expansion register; printed by the Ministry of Economy ’s central standard "-printed by the Bureau ’s Consumer Cooperatives (please read the precautions below and fill out this page) to remember the expansion data in The instructions in the expansion data column of the expansion register are executed in the control block 改变 to change the state of the expansion flag; the modification instruction containing the 0P code and the operator 橺 or the operation in the modification instruction included in the control block is connected Meta column to the expansion data stored in the expansion data column of the expansion register to form a new instruction and the newly formed instruction to be interpreted / executed; and the modification instruction is executed in the control block and changes the expansion flag Of the state. 9-The central processing unit as described in item 1 of the scope of patent application, wherein: the above-mentioned central processing green element further includes a single extended data block No. 34: ΕΓ This paper is applicable to the standard household standard (CNS &gt); Λ4 is now. (210 × 29? Gongchu) D8 VI. Expansion register of patent application scope or expansion register with expansion data column as a component for memorizing control data and expansion flags. The expansion flag is included One or more bits, one of the status flags used to represent the status of the expansion data column of the expansion register, where: 'The instruction containing the op code is interpreted in the control block, taking the immediate constant operand as the A positive integer or a two's complement based on the state of the expansion flag to expand the expansion column length of the expansion register. The 0P code is used to represent the expansion of the memory when the expansion column length is shorter than the expansion register. The extended data operation in the extended data column of the register and the immediate constant operand enables the immediate constant operand to be stored in the extended data column of the extended register, or makes the immediate constant operand Memorized in one of the predetermined locations on the expansion data side of the expansion register; | Printed by the Ministry of Economic Affairs and the Central Government Bureau of the Consumer Consumption Cooperative (please read the back; please fill out this page before filling out this page) to remember the expansion data The instructions in the expansion data column of the expansion register are executed in the control block 改变 to change the state of the expansion flag; the expandable instructions containing 0 P codes and operands are based on the expansion flag in the control block The state is interpreted / executed as an instruction with an operand column included in the extensible instruction, or by connecting the operand included in the extensible instruction to the expansion data stored in the expansion data column of the expansion register. To form a new operand column and be interpreted / executed as an instruction with a newly formed operand block; and the extensible instruction is executed in a control block and changes the state of the expansion flag. 1 0. As for the scope of patent application The central processing unit described in item 4, wherein the paper size on page 35 above applies to the Chinese National Standard (CNS) Λ4 specification (2.0 × 297 mm) Λ ί-Ν Λ 8 4268 3 2 π »D8, Shen Please extend the register of the patent scope to a register and an expansion flag that can be accessed by the program planner so that the program planner can access it. Π. As described in item 5 of the patent application, the central processing unit, The above-mentioned expansion register is a register and an expansion flag that can be accessed by the program planner, so that the program planner can access it. 1. 2. The central processing unit described in item 6 of the scope of patent application, The above-mentioned expansion register is a register and an expansion flag that can be accessed by the program planner so that the program planner can access it. 1 3. The central processing unit described in item 7 of the patent application park. The above-mentioned expansion register is a register and an expansion flag that can be accessed by the program planner, so that the program planner can access it. 1 4. The central processing unit as described in item 8 of the scope of patent application, wherein the above-mentioned expansion register is a register and an expansion flag that can be accessed by program programmers so that the program planner can access . Employee Consumer Cooperatives of the Central Ramp Bureau of the Ministry of Economic Affairs, India (please read the precautions on the back first, then the “this page”) 1 5 · The central processing unit as described in item 9 of the scope of patent application, of which the above-mentioned extended register It is a register and expansion flag accessible by the program planner to make it accessible to the program planner. 1 6. The central processing unit as described in item 1 of the scope of patent application, wherein: page 36 of this paper applies the Chinese National Standards Officer (CNS) Λ4 present (2) 0 × 297 mm) Printed by the Industrial and Consumer Cooperatives 4 2 6 8 3 2 Ss8 C8 D8 々. The above-mentioned central processing unit for patent application also includes an expansion register with a single expanded data column or an expanded data column for memory control data and expansion The expansion register of the flag component, where: The instruction containing the op code is interpreted in the control block, taking into account the immediate constant operand as a positive integer or expansion based on memory in the expansion data column of the expansion register The two's complement of the data. The 0 P code is used to represent the expansion register and the immediate constant operand that is shorter than the length of the expansion column of the expansion register. The operation of the expansion data is to expand it. The length of the expansion column of the register, so that the constant constant operand is stored in the expansion column of the expansion register, or it is moved to the expansion in the expansion column of the expansion register. Expect a predetermined length to the left and connect it to the immediate constant operand to form the extended data and store it in the extended data block of the extended register; the extension instruction connection containing the 0 P code and the operator side is included in The operand column in the expansion instruction in the control box to the expansion data stored in the expansion data block of the expansion register to form a new operand column and be interpreted / executed as an instruction with a newly formed operand column; And the expansion instruction is executed in the control block and stores a predetermined data in the expansion data column of the expansion register. 1 7. The central processing unit described in item 1 of the scope of patent application, wherein: the above-mentioned central processing unit further includes an expansion register with a single expanded data column or an expanded data column as a component for storing expanded data Expansion register, page 37: This paper size applies Chinese National Standard (CNS) Λ4 specification (2 丨 0X297mm) (Please read the precautions on the back before writing this page) Order the central standard of the Ministry of Economic Affairs & quot Printed by Bureau of Consumers and Cooperatives B8 C8 D8 6. Scope of patent application The instruction containing the oop code is interpreted in the control block, taking into account the immediate constant operand as a positive integer or expansion based on memory in the expansion register The two's complement of the expanded data in the column to expand the length of the expanded column of the expanded register. The p-code is used to represent the memory expanded register and the immediate constant operand is shorter than the expanded register. The operation of expanding the length of the extended data column makes the immediate constant operand stored in the extended data register of the expansion register, or moved to the expansion The expansion data in the expansion data paste of the register is a predetermined length to the left, and it is connected to the immediate constant operand to form the expansion data and store it in the expansion data block of the expansion register; it contains 0 P code and The modification instruction in the operand column connects the operand in the expansion instruction contained in the control block to the expansion data stored in the expansion data of the expansion register to form a new instruction, and the newly formed instruction is interpreted / Execute; and the modification instruction is executed in the control block and stores a predetermined data in the expansion register of the expansion register. 18. The central processing unit described in item 1 of the scope of patent application, wherein: the above-mentioned central processing unit further includes an expansion register having a single expanded data column or having expanded data as a component for storing the expanded data The expansion register, where: The instruction containing ◦ P code is interpreted in the control block, taking the immediate constant operand as a positive integer or based on the expansion data stored in the expansion data column of the expansion register 2 Complement to expand it. 笫 3B pages of this paper according to the standard Chinese National Standard (CNS) Λ4 specifications (210 × 297. Mm) (Please read the precautions on the back before filling in this S). The length of the extended data column of the register. The 0 P code is used to represent the operation of expanding the data in the extended register and the immediate constant operand that is shorter than the length of the extended column of the extended register, so that the immediate constant operand The expansion data stored in the expansion register of the expansion register, or the expansion data stored in the expansion register of the expansion register is moved to the left by a predetermined amount. Length and connect it to the constant constant operand to form the extended data and memorize it in the extended data column of the expansion register; the extended instruction containing the 0 P code and the operand column is connected to the extended instruction contained in the control box The operands in the table are expanded to the expanded data stored in the expanded data column of the expanded register to form a new operand column and are interpreted / executed as an instruction with a newly formed operand column; and the expanded instruction is Run in the control box and memorize a predetermined value in the expansion data register of the expansion register. 1 9. The central processing unit as described in item 丨 of the patent application park, wherein: the above-mentioned central processing unit further includes an expansion register with a single expanded data column or an expanded data column as a memory expansion Expansion register of the data components, which is printed by the staff of the Central Standards Bureau of the Ministry of Economic Affairs and printed by the cooperative (please read the note on the back before filling this page) The instruction containing 0 P code is explained in the control box In the method, the immediate constant operand is considered as a positive integer or based on the two's complement of the expansion data stored in the expansion data column of the expansion register to expand the length of the expansion column of the expansion register. The 0P code is The operation used to represent the expansion data in the memory expansion register and the immediate constant operand that is shorter than the length of the expansion column of the expansion register makes the immediate constant operand p. 39 wooden paper scale Shizhou in the threshold family standard搫 (CNS) Λ4 specification (210X297 mm) Λ BCD 6. The scope of patent application is stored in the expansion data column of the expansion register, or the immediate constant arithmetic unit is memorized One of the predetermined positions in the expansion data column of the expansion register; the expansion instruction including the op code and the operand column connects the operand column included in the expansion instruction of control box 10 to the expansion data column stored in the expansion register Expanding the data in order to form a new operand block and being interpreted / executed as an instruction having a newly formed operand column; and the expanding instruction is executed in a control block and memorizes a predetermined data in the expansion register expansion The central processing unit described in item 1 of the scope of patent application, wherein: the above-mentioned central processing unit further includes an expansion register with a single expansion data block or an expansion data column for use Expansion register of memory expansion data components, which is: ^ Printed by the Ministry of Economic Affairs, Shiyang Standards Bureau, Employees' Corruption Cooperative (please read the precautions on the back before constructing this page) The instruction system containing 0P code Interpreted in the control block, taking the immediate constant operand as a positive integer or the two's complement based on the expansion data memorized in the expansion data block of the expansion register, to expand It expands the length of the extended column of the register. The 0 丨 'code is used to represent the operation of expanding the data in the extended register and the immediate constant operand that is shorter than the length of the extended column of the extended register. The immediate constant operand is memorized in the extended data column of the expansion register, or the immediate constant operand is memorized in a predetermined position in the extended data column of the expansion register; contains the 0P code and the operand column The connection of the modification instruction included in the control on page 40 is applicable to the national standard (CNS) Λ4 specification (210X297 male f) 426832 Λ8 Β8 C8 D8 in the paper standard. The expansion data stored in the expansion data block of the expansion register to form a new operand and the newly formed instruction is interpreted / executed; and the modification instruction is executed in a control block and memorizes a predetermined value In the expansion data register of the expansion register. 2 1 The central processing unit described in item 1 of the scope of patent application, wherein: the above-mentioned central processing unit further includes an expansion register having a single expanded data column or having expanded data as a component for storing the expanded data Expansion register, where: The instruction containing 0 P * code is interpreted in the control block, taking into account the immediate constant operand as a positive integer or based on the expansion data stored in the expansion data column of the expansion register 2 The 0 P code is used to represent the memory expansion register and the immediate constant operation unit, which is shorter than the length of the expansion column of the expansion register. The operation of expanding data enables the immediate constant operand to be stored in the extended data column of the expansion register, or causes the immediate constant operand to be stored in a predetermined position in the extended data column of the expansion register; contains 〇 The expandable instructions of the P code and operand columns are interpreted / executed as having only the data contained in the control based on the expanded data values stored in the expanded data column of the expansion register. The operand block in the expandable instruction in the check box, or the operand block included in the expandable instruction is connected to the expansion data stored in the expansion data column of the expansion register to form a new page 41 of this paper. The standard applies to the China National Standard (CNS) Λ4 grid (210X297 mm) (please read the precautions on the back before filling this page). Order printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy 42683 2 Λ8 B8 C8 D8 The patent range operand block is interpreted / executed as an instruction with a newly formed operand block; and (please read the precautions on the back before filling out this page} The extensible instruction is executed in the control block ten and memorized a reservation Value in the expansion data register of the expansion register " 2 2. The central processing unit described in item 16 of the scope of patent application, wherein the above-mentioned expansion register is a temporary register that can be accessed by program programmers. 2 3. The central processing unit described in item 17 of the scope of patent application, wherein the above-mentioned extended register is a register that can be accessed by the program planner S'j. 2 4 Patent application I The central processing unit described in item 8, wherein the above-mentioned extended register is a register that can be accessed by the program planner. 2 5. The central processing unit described in item 19 of the scope of patent application, wherein The above-mentioned extended register is a register that can be accessed by program planners. The central standard of the Ministry of Economic Affairs and the Employee Consumer Cooperatives Co., Ltd. Yin Fan 26. As described in the scope of patent application 2 (), the central processing unit, Among them, the above-mentioned expansion register is a register that can be accessed by program planners. 2 7. The central processing unit as described in the scope of patent application 21, wherein the above-mentioned expansion register is Registers accessed by programmers. Page 42 The meaning of this paper applies to the Chinese family standard (CNS) M specification (2I0X297 mm)