^34562 4452twf.doc/006 A7 B7 五、發明說明（(） 本發明是有關於一種動態隨機存取記憶體（Dynamic^ 34562 4452twf.doc / 006 A7 B7 V. Description of the Invention (() The present invention relates to a dynamic random access memory (Dynamic Random Access Memory)
Random Access Memory, DRAM)升壓電路（voltage boosting circuits) ’且特S!]是有關於一種應用非對稱金氧半導體的 動態隨機存取記憶體升壓電路。 利用低電壓電源供應（power supplies)以降低電源消耗 之積體電路需要升壓電路來增進其效能。這些升壓電路產 生超過供應至積體電路之電源電壓V。。的信號。例如，在 動態隨機存取記憶體中，其使用低電壓電源操作，便需要 使用字元線（word Hne)升壓電路，來產生高於電源電壓Vcc 的升壓信號。這些升壓信號一般是供應至記憶體裝置的字 元線，增進在動態隨機存取記憶體中，記憶胞陣列的寫入 與讀取操作之可靠性(reliability)。 第1圖繪示一種習知字元線升壓電路的電路圖，第2 圖繪示第1圖字元線升壓電路的操作時序圖。 參照第1圖，N型金氧半導體10的閘極連接電壓源18， 源極連接列解碼器(r〇w decoder)22與N型金氧半導體14 的源極，而汲極連接N型金氧半導體12的閘極，其中列 解碼器22接收位址信號Ai，並輸出解碼字元線信號Φ,。N 型金氧半導體12的汲極連接行解碼器(column decoder)24 與N型金氧半導體14的閘極，源極連接N型金氧半導體 14的汲極、N型金氧半導體16的汲極與記憶胞的字元線（未 繪示），其中行解碼器24接收位址信號 ' 且將其解碼’輸 出真値字元線信號ΦΧ/與互補字元線信號真値字元線 信號丨沿可作爲升壓信號，其具有大於電壓源18電壓Vcc (請先閲讀背面之注意事項再填窝本頁) -i_丨丨1丨丨訂-----Ί---線丨^^丨丨丨丨 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格<210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 434562 A7 4452twf.doc/006 __B7_ 五、發明說明（丄） 之電壓Vpp。N型金氧半導體16的閘極連接行解碼器24， 源極連接接地端20。 請同時參照第1圖與第2圖，以說明第1圖繪示之字 元線升壓電路的操作。在不動作(inactive)期間，行解碼器 24產生電壓”Lew”的真値字元線信號φΧ/，並同時產生電 壓”Hlgh”的互補字元線信號_，使得Ν型金氧半導體14 關閉，而N型金氧半導體16打開，所以節點N3的電壓爲 接地端20電壓Vss。接著，列解碼器22輸出電壓”High”的 解碼字元線信號Φ,，此電壓値比如是，因此節點N1電 壓爲V«，而節點N2電壓爲Vce-Vthl，其中Vthl爲N型金 氧半導體10的臨限電壓（threshold voltage)。 然後，將行解碼器24輸出的真値字元線信號φπ電壓 變爲ν<μ：ζ•，電壓νψ^·爲Vpp，而且電壓與節點Ν1電 壓V。。的差値至少大於Vth2的値，其中Vth2爲Ν型金氧半 導體12的臨限電壓。如此將使得N型金氧半導體14開啓， 並且節點N4電壓爲Vpp，同時使得N型金氧半導體16關 閉。當N型金氧半導體14開啓時，節點N3電壓値與節點 N1的電壓値相同，即節點N3傳給記憶胞的電壓値與節點 N1的電壓値相同。因此，有真値字元線信號φΖ/產生時， 節點Ν4接收到電壓νψ^_，..將使得節點Ν2升壓至電壓約 爲VwV^+ανψ^·，達到提昇電壓的目的，其中α爲自我 升壓比。 上述之字元線升壓電路的電路設計複雜，需使用多個 金氧半導體實作，且佔用較多的基底面積。 . 4 (請先閱讀背面之注意事項再填寫本頁)Random Access Memory (DRAM) voltage boosting circuits' and special S!] Are related to a dynamic random access memory boost circuit using asymmetric metal-oxide semiconductors. Integrated circuits that use low-voltage power supplies to reduce power consumption require boost circuits to improve their performance. These boost circuits generate a supply voltage V exceeding the supply voltage to the integrated circuit. . signal of. For example, in a dynamic random access memory, which operates with a low voltage power supply, a word line boost circuit is required to generate a boosted signal higher than the power supply voltage Vcc. These boosted signals are generally supplied to the word lines of the memory device to improve the reliability of the write and read operations of the memory cell array in the dynamic random access memory. FIG. 1 shows a circuit diagram of a conventional word line boost circuit, and FIG. 2 shows an operation timing diagram of the word line boost circuit of FIG. Referring to FIG. 1, the gate of the N-type metal oxide semiconductor 10 is connected to the voltage source 18, the source is connected to the row decoder 22 and the source of the N-type metal oxide semiconductor 14, and the drain is connected to the N-type metal. The gate of the oxygen semiconductor 12, in which the column decoder 22 receives the address signal Ai, and outputs a decoded word line signal Φ ,. The drain of the N-type metal oxide semiconductor 12 is connected to a column decoder 24 and the gate of the N-type metal oxide semiconductor 14, and the source is connected to the drain of the N-type metal oxide semiconductor 14 and the drain of the N-type metal oxide semiconductor 16 The character line (not shown) of the pole and the memory cell, in which the row decoder 24 receives the address signal and decodes it, and outputs a true word line signal Φ × / and a complementary word line signal.丨 The edge can be used as a boost signal, which has a voltage Vcc greater than 18 of the voltage source (please read the precautions on the back before filling in this page) -i_ 丨 丨 1 丨 Order -------- Ί --- line 丨^^ 丨 丨 丨 丨 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with the Chinese National Standard (CNS) A4 Specification < 210 X 297 mm. doc / 006 __B7_ V. The voltage Vpp of the invention description (发明). The gate of the N-type metal oxide semiconductor 16 is connected to the row decoder 24, and the source is connected to the ground terminal 20. Please refer to FIG. 1 and FIG. 2 at the same time to explain the operation of the zigzag line boost circuit shown in FIG. During the inactive period, the row decoder 24 generates a true word line signal φX / with a voltage “Lew” and simultaneously generates a complementary word line signal _ with a voltage “Hlgh”, so that the N-type metal-oxide semiconductor 14 is turned off. Since the N-type metal-oxide semiconductor 16 is turned on, the voltage at the node N3 is the voltage Vss at the ground terminal 20. Next, the column decoder 22 outputs a decoded word line signal Φ of the voltage “High”. This voltage 値 is, for example, the voltage at the node N1 is V «and the voltage at the node N2 is Vce-Vthl, where Vthl is an N-type metal oxide A threshold voltage of the semiconductor 10. Then, the true character line signal φπ voltage output from the row decoder 24 is changed to ν < μ: ζ, the voltage νψ ^, is Vpp, and the voltage is equal to the voltage V at the node N1. . The difference is at least larger than th of Vth2, where Vth2 is the threshold voltage of the N-type metal-oxide semiconductor 12. This will cause the N-type metal-oxide semiconductor 14 to be turned on, the voltage at the node N4 to be Vpp, and at the same time, the N-type metal-oxide semiconductor 16 to be closed. When the N-type metal-oxide semiconductor 14 is turned on, the voltage 节点 of the node N3 is the same as the voltage 节点 of the node N1, that is, the voltage 节点 transmitted from the node N3 to the memory cell is the same as the voltage 节点 of the node N1. Therefore, when a true character line signal φZ / is generated, the node N4 receives the voltage νψ ^ _, .. will make the node N2 boost to a voltage of about VwV ^ + ανψ ^ ·, to achieve the purpose of boosting the voltage, where For self-boosting ratio. The circuit design of the above-mentioned zigzag line booster circuit is complicated, it needs to be implemented by multiple metal-oxide semiconductors, and it occupies more substrate area. . 4 (Please read the notes on the back before filling this page)
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 434562 A7 4452twf.doc/006 ___B7 ___ 五、發明說明（3 ) 本發明提供一種應用非對稱金氧半導體的動態隨機存 » 取記憶體升壓電路，其電路設計簡單，且佔用較少的基底 面積。 本發明提供一種應，非對稱金氧半導體的動態隨機存 取記憶體升壓電路，此電路應用非對稱N型金氧半導體組 成，其中此非對稱N型金氧半導體的部份源極被閘極覆 蓋° 本發明提供一種應用非對稱金氧半導體的動態隨機存 取記憶體升壓電路，此電路包括第一 N型金氧半導體、.第 一非對稱N型金氧半導體及第二N型金氧半導體，第一 n 型金氧半導體的閘極連接電壓源，源極連接列解碼器，第 一非對稱N型金氧半導體的閘極連接第一 N型金氧半導體 的汲極，源極連接記憶胞字元線，汲極連接行鳐碼器，而 第二N.型金氧半導體的閘極連接行解碼器，源極連接喔地 端，汲極連接記憶胞字元線與第一非對稱N型金氧半導體 源極。 、 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： ’ 第1圖是繪示一種習知字元線升壓電路的電路圖； 第2圖是繪示第1圖字元線升壓電路的操作時序圖； 第3圖是繪示根據本發明較佳實施例之非對稱N型金 氧半導體的剖面圖； (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -AW--------訂·！！線 J0-----il^—1—ΊΙ—---- X 297公釐） 434562 A7 4452twf.doc/006 __B7_ 五、發明說明（7) 第4圖是繪示根據本發明較佳實施例之字元線升壓電 路的電路圖；以及 第5圖是繪示第4圖中非對稱N型金氧半導體的等效 電路圖。 圖式之標記說明： 10, 12, 14, 16, 30, 32, 34 : N 型金氧半導體 18, 38 :電壓源 20, 40:接地端 22, 42:列解碼器 24, 44:行解碼器 實施例 第3圖是繪示根據本發明較佳實施例之非對稱N型金 氧半導體的剖面圖。 , 請參源第3圖，此非對稱N型金氧半導體$汲極32 比源極34大，且部份的汲極32被閘極36所覆蓋，其中 此較大汲極32可以使用有傾角的離子植入來形成。因爲 部份汲極32被閘極36覆蓋的緣故，因此汲極32與閘極36 間的電容Cgd大於源極34與閘極36間的電容Cgs。 第4圖是繪示根據本發明較佳實施例之字元線升壓電 路的電路圖，第5圖是繪示第4圖中非對稱N型金氧半導 體的等效電路圖。 請同時參照第4圖及第5圖，N型金氧半導體40的閘 極連接電壓源48，源極連接列解碼器52，而汲極連接N 型金氧半導體42的閘極，其中列解碼器52接收位址信號 6 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ---.-----—訂------Ί !線 ό-------!! 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 434562 4452twf.doc/006 A7 ____B7___ 五、發明說明（令）This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 434562 A7 4452twf.doc / 006 ___B7 ___ V. Description of the invention (3) The invention provides a dynamic random storage using asymmetric metal-oxide semiconductors » Take the memory booster circuit, its circuit design is simple, and it takes up less substrate area. The invention provides a dynamic random access memory boost circuit for an asymmetric metal-oxide semiconductor. The circuit is composed of an asymmetric N-type metal oxide semiconductor, and a part of the source of the asymmetric N-type metal oxide semiconductor is gated. Extreme coverage ° The present invention provides a dynamic random access memory voltage boosting circuit using an asymmetric metal-oxide semiconductor. The circuit includes a first N-type metal oxide semiconductor, a first asymmetric N-type metal oxide semiconductor, and a second N-type metal oxide semiconductor. Metal oxide semiconductor, the gate of the first n-type metal oxide semiconductor is connected to the voltage source, the source is connected to the column decoder, the gate of the first asymmetric N-type metal oxide semiconductor is connected to the drain of the first N-type metal oxide semiconductor, the source The pole is connected to the memory cell word line, the drain is connected to the row decoder, and the gate of the second N. type metal oxide semiconductor is connected to the row decoder, the source is connected to the ground terminal, and the drain is connected to the memory cell word line and the first. An asymmetric N-type metal-oxide semiconductor source. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: A brief description of the drawings: FIG. Is a circuit diagram showing a conventional word line booster circuit; FIG. 2 is a timing diagram showing the operation of the word line booster circuit of FIG. 1; FIG. 3 is a diagram showing a preferred embodiment of the present invention Sectional view of asymmetric N-type metal oxide semiconductor; (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -AW -------- Order ·! !! Line J0 ----- il ^ —1—ΊΙ —---- X 297 mm) 434562 A7 4452twf.doc / 006 __B7_ V. Description of the invention (7) Figure 4 shows a preferred implementation according to the present invention A circuit diagram of an example word line booster circuit; and FIG. 5 is an equivalent circuit diagram showing an asymmetric N-type metal-oxide semiconductor in FIG. 4. Symbols of the drawings: 10, 12, 14, 16, 30, 32, 34: N-type metal oxide semiconductor 18, 38: voltage source 20, 40: ground terminal 22, 42: column decoder 24, 44: row decoding FIG. 3 is a cross-sectional view illustrating an asymmetric N-type metal-oxide semiconductor according to a preferred embodiment of the present invention. Please refer to Figure 3 of the source. This asymmetric N-type metal-oxide semiconductor $ drain 32 is larger than the source 34, and part of the drain 32 is covered by the gate 36. The larger drain 32 can be used. The inclination is formed by ion implantation. Because part of the drain 32 is covered by the gate 36, the capacitance Cgd between the drain 32 and the gate 36 is larger than the capacitance Cgs between the source 34 and the gate 36. Fig. 4 is a circuit diagram showing a word line booster circuit according to a preferred embodiment of the present invention, and Fig. 5 is an equivalent circuit diagram showing an asymmetric N-type metal-oxide semiconductor in Fig. 4. Please refer to FIG. 4 and FIG. 5 at the same time. The gate of the N-type metal oxide semiconductor 40 is connected to the voltage source 48, the source is connected to the column decoder 52, and the drain electrode is connected to the gate of the N-type metal oxide semiconductor 42. Device 52 receives the address signal 6 (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ---.------- Order ------ Ί! Line ό ------- !! This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 434562 4452twf.doc / 006 A7 ____B7___ 5. Description of the Invention (Order)
Ai，並輸出解碼字元線信號扎。N型金氧半導體42的汲極 連接行解碼器54，源極連接N型金氧半導體ζμ的汲極與 記憶胞的字元線(未繪示）’其中行解碼器54接收位址信號 A」，輸出真値字元線信號φχ與互補字元線信號_，而n 型金氧半導體44的閘極連接行解碼器54，源極連接接地 端50。其中Ν型金氧半導體42爲根據本發明較佳實施例 的非對稱Ν型金氧半導體，如第3圖所示。 在不動作期間，行解碼器54產生電壓，’Low”的真値字 元線信號Φ沿，並同時產生電壓”High”的互補字元線信號 φΑ7 ’使得N型金氧半導體42關閉，而N型金氧半導體44 打開’所以節點Ν6的電壓爲接地端50電壓Vss。接著， 列解碼器52輸出電壓”High”的解碼字元線信號t ,此電壓 値比如是V使得N型金氧半導體40打開，因此節點N,5 電壓VN5爲，其中vth3爲N型金氧半導體40的臨 限電壓。此時，儲存在節點N5的電荷量約爲(Vee-Vth3)(Cgd+C cdn5+Css)，其中C_5爲節點N5接地時，節點N5所形成的 電容。 然後，將行解碼器54輸出的真値字元線信號電壓 變爲νμ7，且電壓νφΛ7爲Vpp，如此將使得Ν型金氧半導 體42開啓，同時使得N型金氧半導體44關閉。此時，在 節點N5已儲存有電荷量約爲(V/V^XCm+C^^+C^)，可 以由寺式（Vcc-Vth3)x(Cgd+C φ N5+Cgs)=VN5 X (Cgd+C φ N5+C£S) +(VN5-VppUCsd，得到節點 N5 的電壓 VN5 約爲（(VppXCgd) / + + + ，由於 Cgd 大於 CgS 及 C(DN5，因此 ...... 7 紙張尺度適用中國國家標準（CNS)A4規格（2】0 x 297公釐） (請先閱讀背面之注意事項再填寫本頁.) 經濟部智慧財產局員工消費合作社印製 ---------訂-------； ·!線 ό------- 4345G2 4452twf.doc/〇〇6 A7 B7 五、發明說明（G) 實際上，節點N5的電壓VN5約爲Vpp+(Vee-Vth3)，達成提昇 電壓的目的。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 1. 整個字元線升壓電路的電路設計簡單，使用數目較 少的金氧半導體即可完成，且因爲使用的金氧半導體數目 較少，整個升壓電路所需佔用的基底面積也比較少。 2. 本發明的升壓電路全由N型金氧半導體組成，並且 使用非對稱N型金氧半導體替換，進一步加強升壓電路的 升壓能力。. 3. 本發明的非對稱N型金氧半導體不需額外製程即可 \ 彤成，可與現有的製程相容。 雖然本發明已以較佳實施例揭露如上，然其並非用以. 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) -4 經濟部智慧財產局員工.消費合作社印製Ai, and output the decoded word line signal. The drain of the N-type metal oxide semiconductor 42 is connected to the row decoder 54, and the source is connected to the word line of the N-type metal oxide semiconductor ζμ and the word line of the memory cell (not shown), wherein the row decoder 54 receives the address signal A ", Output the true character line signal φχ and the complementary character line signal _, and the gate of the n-type metal oxide semiconductor 44 is connected to the row decoder 54 and the source is connected to the ground terminal 50. The N-type metal-oxide semiconductor 42 is an asymmetric N-type metal-oxide semiconductor according to a preferred embodiment of the present invention, as shown in FIG. During the non-operation period, the row decoder 54 generates a voltage, a true word line signal Φ edge of “Low”, and simultaneously generates a complementary word line signal φΑ7 'of the voltage “High”, so that the N-type metal-oxide semiconductor 42 is turned off, and The N-type metal oxide semiconductor 44 is turned on, so the voltage at the node N6 is the voltage Vss of the ground terminal 50. Then, the column decoder 52 outputs the decoded word line signal t of the voltage “High”, and this voltage, for example, V makes the N-type metal oxide The semiconductor 40 is turned on, so the voltage VN5 of the node N, 5 is, where vth3 is the threshold voltage of the N-type metal-oxide semiconductor 40. At this time, the amount of charge stored at the node N5 is about (Vee-Vth3) (Cgd + C cdn5 + Css), where C_5 is the capacitance formed by node N5 when node N5 is grounded. Then, the true word line signal voltage output by row decoder 54 becomes νμ7, and the voltage νφΛ7 is Vpp, which will make N-type gold The oxygen semiconductor 42 is turned on, and at the same time, the N-type metal-oxide semiconductor 44 is turned off. At this time, the amount of charge stored at the node N5 is about (V / V ^ XCm + C ^^ + C ^), which can be changed by a temple (Vcc- Vth3) x (Cgd + C φ N5 + Cgs) = VN5 X (Cgd + C φ N5 + C £ S) + (VN5-VppUCsd, get the voltage of node N5 VN5 is approximately ((VppXCgd) / + + +, because Cgd is larger than CgS and C (DN5, so ... 7 paper size applies to Chinese National Standard (CNS) A4 specifications (2) 0 x 297 mm) ( Please read the notes on the back before filling out this page.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --------- Order ---------; ·! -4345G2 4452twf.doc / 〇〇6 A7 B7 V. Description of the invention (G) Actually, the voltage VN5 of the node N5 is about Vpp + (Vee-Vth3), and the purpose of boosting the voltage is achieved. From the above-mentioned preferred embodiments of the present invention, It can be known that the application of the present invention has the following advantages: 1. The circuit design of the entire word line booster circuit is simple and can be completed by using a small number of metal oxide semiconductors, and because the number of metal oxide semiconductors used is small, the entire voltage booster circuit The area of the substrate to be occupied is also relatively small. 2. The booster circuit of the present invention is entirely composed of N-type metal-oxide semiconductors, and is replaced by an asymmetric N-type metal-oxide semiconductor, further enhancing the voltage-boosting capability of the voltage-boosting circuit .. 3 The asymmetric N-type metal-oxide semiconductor of the present invention can be used without any additional process. Process compatible. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. (Please read the notes on the back before filling out this page) -4 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed by Consumer Cooperatives
B 訂 I !線 _0-------- I--------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Order I! Line _0 -------- I --------- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)