TW436710B - Methods and apparatus for processing video data - Google Patents

Abstract

A computer system includes three processors capable to operate concurrently -- a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation.

Description

436 ^ 1 Ο Λ Printed by the Male Workers Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (1) 1 1 I Invention Back 1 1 I The present invention relates to the processing of data by computer _ and especially by computer 1 Video data processing of I. Please first 11 The computer has been used to compress and decompress the system data.糸 铳 Information includes reading-back \ | ι I Video Assets Section * which includes still and / or moving image images. Β Note on general information 1 1 It may also include audio data f For example, a track of an animation. 0 Allowable video Note 1 I Method and circuit for fast processing of data 9 Will be a desirable 0 and φ 1 Binding 1 I Invention 1 1 The present invention provides a method and circuit for allowing fast processing of video data 1 i 0 in In some practical examples of the present invention, a computer system includes three processors capable of simultaneously ordering 1 | operations, an m-quantity processor, a vector processor, and a bit stream processor 0 in video data. When encoding or decoding, perform to the processor 1 1 all operations that can be performed efficiently by a single instruction multiple data (SI MD »single i nstr uc ti on 1 1 mu 11 i P1 ecata) processor c these operations 1 Including: (1) a linear asset transformation 9 such as a discrete cosine transformation (1 I DCT, disci * ete C 0 si ne tra ns f 0 ΓΒ) and (2) motion compensation 1 1 I 0 bit stream processor execution Operations that include operations on specific bits other than words or semi-words 1 1. These include, for example, the use of MPEG-1, MPEG-2 1 1% Η. 261 and Η _ 2 6 3 standards. Huffman (Hu ffma η) and RLC encoding or decoding 1 1 code 0 scalar processor performs high-level video processing (for example, image level 1 | processing), and makes the vector processor and bit stream processor The operation is synchronized, and the interface between the control system and the external device is 0- 3- 1 1 1 This paper size is free of Chinese National Standards (CNS) Α4 specifications (210X297 mm) 436710 Α7 Β7 Off-line Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Printing 5. Description of the invention (>) In some embodiments, the computer system can process several data streams at the same time. As a result, users of the computer system can hold a video conference with two or more stakeholders. Because the bit stream processor can switch the encoding and decoding of different data streams at the same time in real time * multiple data streams can be processed at the same time. In some embodiments, the scalar processor and the directional processor are programmable. This means that each of these two processors can be programmed to execute a single arithmetic or Bollinger instruction. The bit stream processor is not programmable, which means that the bit stream processor cannot be programmed to perform an entire video data processing operation on a set of video data. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, which will allow the bitstream processor to process more quickly. The programmability of these scalar processors and Xiangdong processors will enable the system to be used to modify the video data encoding and decoding standards. Other features and advantages of the present invention are detailed later. The invention is defined by the scope of the accompanying patent applications. Brief description of the drawings The first picture is a block garden of a media card according to the present invention. The second figure is a block diagram of a multimedia processor according to the present invention. The third picture is a block drawing of a bitstream processor. This bitstream processor is part of the processor of the second drawing. The fourth to sixth laps are block diagrams of the computer system according to the present invention. -4-This paper size is applicable to Chinese National Standard (CNS) A4 ^ grid (210X297 mm) --------- t ------ tr ------ line Note on the back of this page again 3 pages} Α7 Β7 43 67 1 0, 5. Description of the invention (The seventh picture illustrates the firmware structure in the processor of the second picture. The eighth and nine pictures show the use of The address map of the system in the first garden. The tenth map is the block diagram of the DSP core of the second map. The eleventh map illustrates the pipeline used in a vector processor. Part of the processor in the figure. Figure 12 is a functional block diagram of the processor in Figure 11. Circle 13 illustrates the execution data path in the vector processor of the eleventh garden. The figure illustrates the path of loading and storing data in the vector processor of the eleventh circle. The fifteenth circle is a block diagram of a high-speed cache memory system of the processor of the second figure. Figure 15 illustrates the instruction data cache in the high-speed Echung memory system of Figure 15. Figure 17 illustrates the processor of Figure 2. A data path management medium in a high-speed memory control unit in Figure 18. Figure 18 illustrates the data path of an address processing pipeline in a cache control unit used in the system of Figure 2. Figures 19 to 22 illustrate the state mechanism in the processor of Figure 2. Figure 23 illustrates the address format used in the cache system of the 15th sleeper. -5- The size of this paper applies to the National Standards of the Ten Countries (CNS) A4 (2 丨 0X297 mm) ^^ I— H ^ (Please read the precautions on the back before this page) The consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs b A7 B7 V. Description of the invention (The twenty-fourth garden illustrates a bus in the processor of the second graph. The twenty-fifth graph illustrates an arbitration control army in the processor of the second graph Figures 26 to 29 are timing diagrams of the processor in the second figure. Figures 30 to 32 show the memory request signal in the processor in the second circle. A bus arbitration control unit in the processor of the second figure is shown. Figures four to thirty-six are timing diagrams of the second processor. Figures thirty-seven and thirty-eight illustrate the bus interface circuit in the processor of the second figure. Figures thirty-nine and forty illustrate the A virtual frame buffer (VFB) for the system of the first circle. Figure 41 illustrates the bus interface circuit used for the system of the first image. 0 ------ --- ^ ------ 1T ------ 0 {Please read the notes on the back first, and then work, this page) The Central Department of the Ministry of Economic Affairs A picture of i 铳 第 图 is used in the picture, a picture of the first picture is shown in the picture, and a picture of the picture is shown in the picture. Figure forty-four systems, fourteen systems, four control units, body memory control system, location control system, figure 1 Figures of all the systems in the material I of the material I ~ 1 The first figure of the Yuming theory is shown in Figure 7880.44 The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297) (Centi) A7 4367 1 〇 __Β7 V. Description of the invention (f) Block diagram. The forty-ninth to fifty-first diagrams are timing diagrams of the first plaque system. Figures 52 and 53 illustrate the device interface circuit in the second processor. The fifty-fourth to fifty-sixth figures are partial block diagrams of the first figure. The fiftieth t to the fifty-ninth circle illustrate the register in the system of the first picture. 〇 The sixth + diagram illustrates the information segment buffer and video window in the system of the first picture. The sixty-first diagram is a timing diagram of the system of the first diagram. Figure 62 illustrates a register in the system in Figure-Figure 62. The sixty-third diagram is a timing chart of the system of the first diagram. The sixty-fourth to sixty-sixth diagrams illustrate the elements used in the system of the first diagram. The following example shows a media card 10G, which includes a multimedia processor 110. In some embodiments, the processor 110 is a processor of type MSP-1EX (trademark), and its specifications are manufactured by Samsung Semiconductor Co., Ltd. in San Jose, California, USA. The processor MSP-1EX is detailed in Appendix A. The processor 110 is in communication with a mainframe computer system (not shown) via a regional bus 105. In some embodiments, the busbar 105 is a paper size applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) --------- ^ ------ ΪΤ-- -*-^ (Please read the notes on the back before i > i this page) Consumption Cooperation between Employees of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the Society 4 3 67 1 Ο 4 Α7 Β7 5. Description of Invention (^) 3 2-bit 33 MHz PCI bus. One of the digital video data output of the processor 110 is connected to a digital-to-analog (D / A, digital-to-analog) converter Π2. Except for the video part, the digital video The data can then include an audio part, such as a movie's audio track. The output of the converter 112 is connected to a Mythology (not shown) or another system that processes analog data. In some implementations In the example, the processor 110 also includes an input port, which is used to receive digital video data from an analog-to-digital (A / D, analog-to-digital) converter (see fourth to sixth_). 110 is connected to Codec 114. Codec 114 receives analog audio data from a tape recorder (not shown) or another device. Codec 114 receives analog phone data from the telephone medium (not shown). Codec 114 digitizes the analog data and transmits it to the processor 110. Codec 11 4 receives the digital data from the processor 110, and so on. The data is converted into analog format > and the analog data is transmitted as needed. Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs {Please read the precautions on the back first and then this page) Processor 110 is The bus 122 is connected to a memory 120. In the first picture, the memory is 12 million (3 is a synchronous dynamic random access memory (SDRAM, synchronous DRAM), and the sleep bus 122 is a 64-bit 80 megahertz bus. Other memories籴 The bus width and bus speed are used in other embodiments. Asynchronous memory and bus are used in some embodiments. Some embodiments of the card 100 are described in the US patent application n Multi-Processor Operation in Multimedia Signal Processors "(Appointment Case No. M-4354US), which was proposed by Le Nguyen on the same day as the case, and it is a reference to the Chinese Standard (CNS) Α4 of this paper standard Specifications (210 × 297 mm) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 136Ή 0, Α7 Β7 V. Description of Invention (,) and included here. The second figure is a block diagram of an embodiment of the processor 11D. Processing The processor 110 includes a scalar processor 21D, a vector processor (" VP ") 220, and a bit stream processor (" BP") 245. In some embodiments, the processor 21G is a 32-bit processor. Meta RISC processor, which operates at 4 0 Megahertz 'and is applicable to the standard ARM7 instruction set known in this technology β. The vector processor 220 is a single instruction multiple data (SIMD) processor * which operates at 80 Megahertz and has 288 bits Vector register. One embodiment of the vector processor (VP) 220 is described in the US patent application "Effective Library and Original Works in a Multitasking Computing System Environment" (Appointment No. M-43 65 US) • It was proposed by Song et al. On the same day as the case • and incorporated herein by reference. The processors 210 and 220 can be programmed by the program to perform a single arithmetic or Bollinger instruction, or a series of In some embodiments, in order to obtain a high video data processing speed, the bit stream processor 245 is made into a single arithmetic or Boolean instruction that cannot be executed by the program specification. Especially * bit stream The processor (BP) 245 cannot be programmed to execute instructions such as ADD (addition), OR (or), ADDAND ACCUMULATE f and addition). Instead, BP 245 may be instructed to perform a video data processing operation, as described in Chapter 10 of Appendix A. At the same time, scalar processor 210 and vector processor 220 can be programmed to execute a single arithmetic or Bollinger instruction. Yes K, the processor UQ can be used for different video standards. As shown in the second figure, the paper size of the blunt processor 210 and the vector processor 220 is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) --------- ^- ----- ΪΤ ------ ^ (Please read the precautions on the back first, and then 本页. This page) Α7 43 671 〇, ____ Β7 _____ 5. Description of the invention (彡) It is embedded in the cache memory subsystem 230. The cache memory subsystem 230 is connected to a bus 240 ("10 BUS") and a bus 250 ("FBUS"). In some embodiments, IOBUS 240 is a 32-bit 40 megahertz bus, and FBUS 25D is a 64-bit 80 megahertz bus. IOBUS 2 4 0 is connected to the bit stream processor 2 4 5. Interrupt controller 248, Full-Duplex UART unit 2 4 3, and four timers. FBUS 2 50 is connected to the memory controller 258, which in turn is connected to the memory bus 122 (first cycle). FBUS 250 is connected to the PCI bus interface circuit 255, which is connected to the PCI bus 105. FBUS 25Q is also connected to the device interface (also known as “Customer Application ASIC, Customer ASIC”) 252, which includes M and video D / A 112 (first picture), Codec 114, and possibly a Interface circuits for video A / D converters (such as those shown in Figures 4 to 6). The processor 110 also includes a memory processor 290. The processor 110 can process several data streams simultaneously. For example, if a user of the processor 110 has a video conference with two or three objects, the processor 110 provides video and audio processing that allows the user to see the plurality of objects once they are heard. In order to process multiple video data streams, the processor 11Q provides switching in this document. This means that B P 2 4 5 switches between multiple data streams. In a video conference, each data stream may come from a separate distant object. This paper size applies to Chinese National Standard (CNS) A4 (210X297 cm) --------- Home ----- 1T ------ ^ (Please read the precautions on the back first (Revisited ;; this page) The Central Bureau of Standards, Ministry of Economic Affairs, Bei Gong Xiao F Cooperative, printed the film, Xu Fang, Yun Ying, or Dao Jie Jian Ying, a telegram; Yu Yin came from me and I can discuss it. · The news and materials of the newsletter and the information can be used in the same way.

Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of Invention (f). The switching of this article is detailed in Chapter A of Appendix A. 12 ° When this article is about to switch, the scalar processor 210 stores the current article and initializes the PB 245 to process a different article. ΒΡ 24 5 can process the following video data formats: 1. MPEG-1, as described in IS0 / ΪEC standard 11172 (1992) 2. · HPEG-2 * In document ISO / IEC JTC 1 / SC 29 Ν0 9 8 1 Rev (March 31, 1995); 3. H.261, as described in "ITU-T Book H.261" (March 1993); and 4_11_263 * in "Draft 11 ^ -Tweet || Book 11.263 > > (May 2, 2006). Video data processing is divided between scalar processor 210, direction processor 220 and bit stream processor 245 In order to achieve a high processing speed. In particular, the vector processor 220 performs linear transformations (such as a discrete cosine transform (DCT) or its inverse transform (IDCT)) and motion compensation. These operations are suitable for vector processors, Because these operations often need the same instructions to execute on multiple data. The bit stream processor 245 performs Huffman decoding and creping, and zig-zag bit stream processing. Scalar processor 21 (3 Perform demultiplexing and synchronization of video and audio, and I / O interface tasks. Examples of encoding and decoding operations are disclosed in Appendix A, sections 10.6.1 and 10.6.2. Code operation, the uncompressed digital data comes from the memory 120 or the main system (not shown) via the bus 105. At a certain -1 1- The standard of this paper is applicable to the Chinese standard (CNsiA4 specification) {210X29? Mm > --------- " ------ 1T ------ Please read the precautions on the back of the line t. This page 4 Printed by a coward, co-worker, consumer cooperative ^ 367 1 Q ._ ^ __ Jade, Description of Invention (Yc >) In some embodiments, the device interface circuit 252 includes a video A / D converter * and the uncompressed The data guarantee comes from this converter. The vector processor 22 (3. Performs quantization, DCT, and motion compensation. The bit stream processor 2 4 5 receives the rotation of Vf> 2 2 0 and generates blocks Groups (GOBs, Groups of Blocks) or Slices. In particular, BP 2 4 5 performs Huffman and RLC encoding, and processing of the bit stream. The scalar processor 210 receives the output of BP 245 And perform image layer coding (G0P, group of pictures) coding, and sequence layer coding. The scalar processor 210 then multiplexes and transmits audio and video data Encoded data to a storage device (via bus 10 5 or 12 2) or a network. The transmission to the network involves transmission to a device interface circuit 252, which in some instances is connected to a network. When decoding, its processing is reversed. The scalar processor 210 demultiplexes the system data into the video and audio components, and executes the video data sequence layer, GOP, and image layer decoding. The obtained GOBs or cutting sections are dried to the bit stream processor 2 4 5. The processor 245 performs tooth processing and Huffman and RLC decoding. VP 2 2 0 receives the output of BP 2 4 5 and performs dequantization, IDCT, and motion compensation. The VP 22Q performs any possible post-processing (for example, smoothing the edges of the image) and provides the reconstructed digital image to the device interface circuit 252 or a storage device. The scalar processor 210, the child processor 220, and the bit stream processor 245 can operate on different data blocks in parallel. The blunt processor 21Q can handle the image layer and the lower layer, which is reduced by -12- This paper size applies to the National Standard of China (CNS) A4 (210x297 mm) ------- --¾ ------ 1T ----- (Please read the notes on the back before filling this page), A7 _ B7 V. Description of the Invention (丨 J) Cross-processor communication. This is because the image layer and higher layers contain information on the pure K processor 210's κ control and I / O functions, but they are not used by the vector processor 220 or the bit stream processor 245. An example of such information is an information segment rate, which is a scalar processor 21 (3 used by M to transmit information segments to the device interface circuit 2 52. The third figure is a block of an embodiment of the bit stream processor 245 The signals shown in the third circle are detailed in Appendix A, Section 1Q.5. These signals provide a ® interface between the bit stream processor 24 5 and I0BUS 240 (second picture). In BP 245, these signals are processed by I0BUS interface unit 310 including SRAM 320. BP 245 also includes VLC FIFO unit 330, VLC LUT ROM 340, control bark state control 350, and BP core unit 360, the BP core Unit 3SQ includes a register file and an SRAM. The box in the third figure is detailed in Appendix 10.4, Chapter A. Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives (Please close the precautions on the back, and then ^ < This page} ROM 340 contains look-up tables for Huffman encoding and decoding, all of which are commonly used in four standards: MPEG-1, MPEG-2, H.261, and H.263. Although a lot of information is stored in these lists. ROM 34G has only 768X 12-bit size. This size This is achieved by sharing these lists and the techniques described in Section 4 of Appendix B. The present invention is not limited to the foregoing embodiments and appendixes below. In particular, the invention is not limited to such implementations Any circuit, clock rate, or timing of the example. Other practical examples and fees are within the scope of the present invention as defined by the scope of the attached patent application. -1 3-This paper size is applicable to the country of China 椋Quasi {CNS) Λ4 specification (210X297 mm) Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention Mi)

Appendix A MS P-1 EX 糸 铳 Specifications (Instructions) Chapter 1 Technical Overview This chapter describes the technical overview of multimedia signal processors (" HSP-X ") as known to hardware and software designers. 1.1 The multimedia signal processor (MSP-X, Multimedia Signal Processor) constitutes a single-chip VLSI family, which is designed to provide integrated functionalities for personal computers and consumer products. The MSP family is based on a powerful Although the processor architecture, it uses a single instruction multiple data (SIMD, Single Instruction Multiple Data) computing model M for the best cost / performance and cuisine. Its features include: • Full programmability • Based on the ARM instruction set architecture • Integrated 40 MHz ARM7 RISC CPU core 80 MHz to S processor for high performance digital signal processing • 2.56 Gops * for 9-bit integer ALU operations • 2.56 Gops • for 16-bit integer multiply-accumulate operations 6 4 0 M f 1 ο ps for 32-bit IEEE floating-point addition. 1 2 8 (3 H f 1 〇ps for 32-bit IEEE floating-point multiplication & addition • Unused 10 Kgates, use Customizable or Graphic Performance • Based on 0.65 // m3.3v / 5v CMOS technology This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) --------- ^ ------ 1T ------. ^ < Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 67 1 0 a7 * B7 V. Description of the invention (Λ-Z ) -128 pin to 2 5 6 pin package The MSP will initially provide four main functionalities: • Video • Audio / Sound • Telecommunications_ ZD / 3D image (optional) 1-1-1 Video • All functionality is programmable in firmware. • Real-time MPEG-1 decoding and encoding. Real-time MPEG-2 decoding. • Near-real-time MPEG-2 encoding. • Real-time H. 3 2 4 decoding and encoding. • For any screen size Or resolution image ratio • Color space conversion between RGB and YUV • Image wave for image enhancement and noise reduction • 4/3 pull-down conversion 1 * 1-2 Audio / Audio • All functionalities Programmable • Real-time MPEG-1 audio decoding and encoding • Real-time MPEG-2 audio decoding and encoding • Real-time 320 and it.324 audio decoding and encoding Standards are applicable to China National Standard (CNS) Α4 specifications (210 X 297 mm) --------- ^ ------ II ------. ^ (Please read the precautions on the back first (Fill in this page again.) Printed by the Bureau of Economics, Central Bureau of Standards, Shellfish Consumer Cooperatives 436—Η Ο, A7 ----- B7 —I _--. V. Description of the Invention (+3) • Instant G.7 2 8 and G.723 speech coding (SoundBlaster emulation) • Wavetable synthesis (Wavetable) synthesis • FM synthesis 11.3 Dangxun 1 · 1.3. 1 aging capture ( Quasi-asynchronous COM port interface (NS 16550 A UART compatible) • V 34, from 28.8K to 2.4Kbps • CCITT-V.32 bis, K480Q, 9600 uncoded, and 3600bps trellis Code data rate_ Hayes AT command set compatibility • Call process monitor • V.25 bis automatic dialing • DTMF and pulse dialing • Asynchronous error repair agreement • V. 42 error correction 1 · 1.3, 2 Fax V.2 9 * at 9600 bps or 7200 bps V.27 ter, at 4800 bps or 2400 bps • Calling process monitor • Automatic numbering This paper size applies to China National Kneading Soap (CNS) Α4 specifications 210 × 297 mm) --------- ^ ------, 1T ------ line (please read the precautions on the back before filling in this page) A7 4 3 6710 B7 V. Description of the invention (heart 4) • DTMF and pulse dialing • G3 Fu send • T.4 / T. 3 Q operation 1 · 1 · 3, 3 Thunder answering • Recording greetings via telephone or microphone • Automatically Answer the call • and K pre-recorded message as a response • Record the caller ’s message * Broadcast the message left by the caller 1,1.4 2Π / .ΊΠ image ίΐΤ 锇 馆)

• BITBLT • 2D straight line & multilateral drawing and shaded line • Geometry for 3D points, lines and triangles & brightness meter 亮度 3D color calculation, κ suspect mapping method • Dissolve --- ---- ¾ .------ 1T ------ ^ (Please read the notes on the back before filling in the poor page) Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumers Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Employee Consumer Cooperative 4 3 67… a? B7 V. Description of the invention Μ-ί) • MSP-1 is designed to be used as an entry level without external SDR AM. • ^ 卩 -1 £ 丨 Includes a 32-bit memory gambling bus * for interface to external SDRAM. * MSP-1F includes a 64-bit memory bus, using K interface to external SDRAM.. MSP-1G includes an integrated SVGA controller, RAM DAC to accelerate 3D image acceleration. The fifth figure shows a block diagram of a system including an MSP-1E processor. 1.2,2 External ΠΠΠΕΓα f dumping mill) The sixth diagram shows a block diagram of a system including an MSP-1 processor with external codecs. 1 · 2 · 2. 1 MSP-1RX Material Clearance _ The following is a list of recommended materials for MSP-1EX:

-MSP- 1EX

5 1 2 KX 32-bit synchronous DRAM • NTSC / PAL encoder (KS 0119 from Samsung) • Audio & telecom codec (AD 1 84 3 for analog components) • Miscellaneous (capacitor, resistor, amplifier, connection Devices, etc. • • •) • Printed circuit boards and paper sizes are generally in accordance with Chinese National Standards (CNS) A4 (210 X 2S7 mm). Please read the notes on the back before filling in this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 67 1 〇Α7 _______ ^ _ Β7__ V. Description of the Invention (A_tr)

1 ‘3 Toe Frame F MTCRf] -ARCH TTECTIlRfO 1 · 3 · 1 The MSP microarchitecture basically includes a very powerful DSP core (CORE) and a customer-specific memory & I / O subsystem. Referring to the second figure, the DSP core includes: • A 32-bit ARM7 RISC CPU, executed by M40MHZ, and used for general processing _-A vector processor, executed at 8QMHZ, and used for signal processing •-shared The cache memory is 100 million bytes, which is executed at 80MHz, and includes 2KB instruction cache memory, 5KB data cache memory, and 16KB ROM cache memory. This data cache can be controlled by hardware or drink. • A fast 64-bit bus (FBUS, fast bus) «K 80ΜΗζ implementation • and interface to a number of peripheral equipment. • A slower 32-bit bus (I0BUS), implemented by M4QHHZ, and interfaced to several I0BUS peripherals. These internal FBUS devices include: • a 32-bit 33 MHz PCI bus interface • a 64-bit SDRAM memory controller • an 8-channel DMA controller * a customer ASIC editing block. The customer ASIC edit box provides a total of 10 Kgates, which includes two interfaces to different analog codecs and customer-specific I / O components. This interface series supports Samsung ’s KSD119 -6 * This paper size adopts Chinese National Standard (CNS) A4 specification U10X 297 male «) --------- ^ ------ ΐτ --- --- ^ (Please read the notes on the back before filling this page) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

1 · 4-2 CLK RSTL AD [31: 0] C_BEOL C_BE 1 L C_BE 2 L C_BE3 L PAR FRAMEL Low action Low action Low action Low action Low action AD 1843 codec with analog components. • A memory «data mover, which is used for DMA data * from the main memory (Pentium) memory to the MSP area SDRAM memory. The internal IOBUS peripheral equipment includes: a bit stream processor, which is responsible for processing the video bit stream • a 1 6 4 5 UART serial line an 8254 compatible timer • an 82 59 compatible interrupt controller The MSP also includes a special register (MSP control register), which is used for software control initialization and interrupt. 1. 4 MSP-1RX training pin description 1-4-1 Total: 256 pins PΓΤΒ1 (5 word connector) Clock input pin reset input pin | Lower action address and Data bus pin control & byte D enable pin control & byte 1 enable pin control & byte 2 enable pin control & bit sister 3 enable pin polarity Pin cycle information section pin, low position operation -7- This paper size applies to China National Standard (CNS) Α4 specification (210 X 297 mm) --------- ^ ------ ΐτ ------ 0 (Please read the precautions on the back before filling in this page) 4 3 67 1 q 5. Description of the invention

I RDYL TRDYL STOPL LOCKL I DSEL DEVSEL REQL GNTL PERRL SERRL INTAL Component selection input pin, component selection pin, low-position action bus pin, low-position action bus allow pin • low-position action polarity error pin, low-position action error pin • low-position interrupt pin • low-position action Installation-(Please read the precautions on the back before filling this page)

、 1T Printed KSO 1 1 9 by the Central Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperatives 丨. Coder (24 books), synchronously roll out the information section to KS D119_ for serial clock output of the three-line main interface to KS 0119 -8- 1-4-3 TCK JTAG test clock input pin TDI JTAG test data input pin TD〇JTAG test data output pin TMS JTAG test mode select input pin TRSTL JTAG test reset input pin CLK clock chakra, this is a 40MHz clock input pin 1 * 4-4

SFRS

SCLK The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 43f57 1 〇 5. Description of the invention A7 B7

SDAT BGHS BGVS NSSEL PD [15: 0 BGCLK RPOHCSL Serial data I / O Horizontal sync signal • Input to MSP Vertical sync signal KS Oil 9 _ prime clock output to KS 0119 BIOS PROM chip selection

1 * 4 * 5 A43SCLK

A43SDFS Printed by the Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs

A43SDI A43SD0 "1843 Audio & Audio Equipment (6 books) serial clock / input / output. SCLK is a two-way signal, which acts as a bus master (BM, Bus Master) When the pin is driving the high bit (HI), the clock is provided as an output to the serial bus, and when the BM pin is driving the low bit (L0), the clock is accepted as the rotation. The serial data is synchronized in real time (sync) ), Input / output. SDFS is a directional signal that provides an information segment synchronization signal as an output to the serial bus when the BM pin is driving HI * and is accepted when the BM pin is driving L0 Information segment synchronization signal is used as input. Serial data is input to AD 1843 and output from MSP. All control and playback transmission is 16-bit long, and it is based on MSB. Serial data, output from AD184 3, output People to MSP. All -9- --------- # ------, 1T ------ line (Please read the precautions on the back before filling in this page) This paper The standard is applicable to the Chinese national standard (CNS) A4 specification (210x297 mm) 43671〇A7 B7 V. Description of the invention (AHt status & control register read and Discharge line 16 yuan long transmission, and the MSB being the first.

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CAS1L Printing Policy of Shellfish Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs

MVEL MAI [11: 0] HD [63: 0] MA23 HA24 DQM

MCKE

HCSOL remembers that the BS clamps the clamps and the f S7 is the output pin) (low-position action). This series of address strobes M latch the column address from "4 [11: 0] to the selected 31)! 14 {1 internal library address buffer. Output pin (low-position action). This row address strobe M latches the row address from MA [11: 0] to the internal row address buffer of the selected SDRAM library. Output pin (low-position action). This is the write enable to the SDRAM. Output pin. The multiplexing and row address signals to SDRAM. Input / output SDRAM data pin. Turn out the pins. Memory address bit < 23 >. Output pin. Memory address bit < 24 >. Output pin. This makes the SDRAM data output impedance * after the clock and masks the rotation. (This pin is for synchronous DRAM interface only) Output pin. The system clock * K of the SDRAM is blocked from the next clock cycle. Output pin (low-position action). Used for 10 lower 32-bit paper sizes. Applicable to China National Standard (CNS) A4 specification (210X297 mm) --------- ^ ------ 1T ------ line (Please read the precautions on the back before filling out this page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Lithium and Minerals 4 3 6 7 1 〇, a? MCS1L output pin (low-level action). SDRAH chip selection for the upper 32 bits. MR DYH pin out. SDRAM is ready. MEMCLK output pin. This is the clock-output pin to SDRAM. 1 · 4. 7 S box approved VDD 3.3V power pin VCC 5V power pin VSS ground pin list 1 HSP_1 EX pin designation chip TO # Type name description 1 202 IN VDD 3.3 can brocade 2 1 I / O AD31 Obstacles for PCI Calendar 3 2 ί / ο AD30 4 3 I / O AD29 -11- --------- ^ ------ ΐτ ------ ^ (Please Please read the precautions on the back before f this page) This paper size is applicable to China National Standards (CNS) A4 (210X297 mm) The Central Consumers Bureau of the Ministry of Economy Staff Consumer Cooperatives 4 3 671 〇at J B7 (/ Η1) 5 4 I / O AD28 6 5 I / O AD27 7 205 IN GND m 8 6 IN VCC 5 · for Jg 9 .7 I / O AD26 for PCI sleep 10 8 I / O AD25_S09 For PCI sinks and cables zmt & m 11 9 I / O AD24J08 For PCI sinks 繊 12 10 i / o C_BE3l For PCI control / bit flip 13 208 IN VDD 3.3 Surface supply 14 11 IN IDSEL for PCI Zhan 15 15 I / O AD23 S07 -12- (Please read the precautions on the back before filling out this page) The standard of this paper applies the Chinese National Standard (CNS) AJ specification (2 丨0'〆297 mm) Economy Printed by the Central Bureau of Standards Consumer Cooperatives 4 3 671 〇at 4 Β7 V. Description of the Invention (/ Η5) 16 13 I / O AD22 S06 For PC Head Beach / Office_ 鸺 出 之 娜斯 17 14 I / O AD21 S05 18 15 I / O AD20 S04 19 509 IN GND m 20 16 IN vcc 5 Yuanna 21 17 I / O AD19_S03 Used for PCI sleeping chicks / fibers_han out of touch & thanks 22 18 I / O AD18_S02 23 19 I / O AD17_S01 24 210 IN VDD 3.3 side supply 25 20 I / O AD16_S00 used for ((1: mixed with color cut out 26 26 I / O CJE2L for PCLawSCTSdil -13- ------ --- t .------ ΐτ ------ ^ (Please read the notes on the back before filling in this page) This paper music standard uses China National Standard (CNS) Α4 size (210 X 297 Mm) 6 3 4 ο

A. Printed by the Consumers ’Cooperative of the Economic and Standard Bureau of the People ’s Republic of China. 5. Invention i. Mao Ming (A # L) 27 22 I / O FRAMEL PCI Sleeping Lion mffe 28 23 I / O IRDYL Ready for PCI (¾¾¾) 29 211 IN GND 30 24 I / O TRDYl Target ready for PCI (slave) 31 25 IN-vcc 5 For Ji 32 26 1 I / O DVSELL at 33 27 I / O STOPL Stop CI's current transaction 34 28 I / O LOCKL The current transaction latched in PCI 35 214 IN VDD 3_3V for JS 36 29 I / O PERRL in PCI 37 37 I / O SERRL in " 14- -------- -Buttons — (Please read the notes on the back before filling this page) This paper size 'applies to Chinese National Standard (CNS) A4 specifications (2IOX 297 mm) Printed by the Consumers' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs 436 & quot Μ Ο, at B7 V. Description of the invention 〇4-l! 〇38 31 IN TCA «ΒίΜΑ 39 32 I / O PAR in PCI 40 215 IN GND m 41 33 I / O CJE1L for PCI2» / wet Earn 42 34 I / O AD15_S19 for the face of PCI sinks, dirty and sacrifice 43 35 IN VCC 5V lion for J | 44 36 I / O AD14J18 for the face of PC flap valve withdrawal 45 37 I / O AD13 S17 46 38 I / O AD12 S16 47 218 IN VDD 3'3 Noodle Hall 48 39 I / O AD11J15 -15- --------- Buttoning -------- ΐτ --- --- (Please read the precautions on the back first ^^ This page) This paper is suitable for China National Standard (CNS) A4 size (2IOX297 mm) A7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 43671 Ο Λ Β7 V. Description of the Invention (/ Book) 49 40 I / O AD10_S14 is used for PC / Ramp / testing based on scary 50 50 I / O AD09_S13 51 42 I / O AD08_S12 52 221 IN GND 53 43 I / O C .BEOL for PCI ^ M / bowling E 54 44 IN TCB 55 45 IN vcc 5V power supply 56 46 IN TM still 57 57 I / O AD07_S1I for PCI sink / test 5S 48 I / O AD06_S10 Thank you for your PC's late departure / test -16- --------- ^ ------. 玎 ------ 0 (Please read the Note: Please fill in the X page again) This paper size is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) Λ7 43 671 Ο, 87 V. Description of the invention F 59 222 IN VDD 3_3V power supply 60 49 I / O AD05_MT5 for Ra swollen / istiiisra material enzymes 61 50 I / O AD04JT4 used for PCI sleep current Nana 62 226 IN VDD 3.3 surface should 63 227 IN GND Na 64 51 IN vcc 5V power supply 65 52 I / O AD03-MT3 66 53 I / O AD02JT2 used for PCI sink beach 66 53 I / O AD02JT2 used for PCI sleep sleep 67 227 IN GND Lion 68 54 -17- I / O AD01JT1 used for PCI sink beach / 1 have been shown! ^ 4 ( Please read the notes on the back before filling in this page) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 43 671 Ο λ V. Description of the invention 04) Α7 Β7 Employees ’cooperation with the Central Standards Bureau of the Ministry of Economic Affairs 'Du printed beer 69 69 I / O AD00.MT0 used for PCI sinks 70 228 IN VDD 3.3V power supply Na 71 229 IN GND m 72 56 OUT MA11 SDRAM address sinks 73 57 OUT MA10 74 58 OUT m 75 59 OUT m 76 60 ΟϋΤ HA7 77 230 IN VDD 3.3_Na 78 231 IN GND Chi-18 * --------- Private clothing ------ IT ------ ^ (Please read the precautions on the back before filling this page) This paper size uses the Chinese National Standard (CNS) A4 size (210 · × 297 mm) 6 3 4 ο 5. Description of the invention Mw) Central standard of the Ministry of Economic Affairs Printed by the Associate Bureau employee consumer cooperative 79 61 OUT MA6 80 62 OUT MA5 SDRAMSfahM away 81 63 OUT MA4 82 64 OUT MA3 83 232 IN VDD 3.3V supply 84 233 IN GND Lion 85 65 OUT m 86 66 OUT HAl SDRA »fS6tM beach 87 67 OUT MAO 88 68 OUT RAS1L SDRAi address status §1 89 234 IN VDD 3.3V power supply for J® 90 235 IN mm -19- --------- Private clothing-(谙 Read the back first (.If. Italian matters again ^^ this page) This paper music scale is applicable to the Chinese National Standard (CNS) A4 specification (2! Ox 297 gong) Printed by the Ministry of Economic Affairs and Central Standards Bureau Off-line Consumer Cooperatives 436 " Π Ο, α7 Β7 V. Description of the invention) 91 69 OUT CAS1L SDRA0lj ^ fil 92 70 OUT HEMCLK SDRAM (80 Mhz) 93 71 OUT MWEL SDRAM write ASill 94 72 OUT DQM SDRAM DQH 95 73 OUT MCSOL SDRAM chip Si (low block) 96 74 OUT MCSIL SDRAM chip (high block) 97 236 IN VDD 3.3_ instrument 98 237 IN GNU m 99 75 OUT HCKE SDRAM ^ HtS ^ 100 76 IN HRDYH SDRAM ready 101 238 IN VDD 3.3 facet -20- pack- (Please read the precautions on the back before filling out this page) NS > A4 specification ('210X 297 mm) 43 671 Ο λ Α7 Β7 V. Description of invention (/ Η 丨) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 102 239 IN GND 103 77 I / O MDO 104 78 I / O mi SDRAMM? «Stream 105 105 I / O HD2 106 80 I / O MD3 107 240 IN VDD 3.3 雠 Supply 108 241 IN GND m 109 81 I / O MD4 110 82 I / O HD5 SDRAM data bus 111 83 I / O MD6 112 84 I / O MD7 113 242 IN VDB 3.3 Source supply-21- (Please read the precautions on the back before filling out this page)-The paper size applies to the Chinese national standard {CNS) Α4 size (2ΙΟχ 297 mm) 6 3 4 ο

B. Description of the invention (m) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 114 243 IN GND m 115 85 I / O MD8 sDRjmmm 116 86 I / O HD9 117 87 I / O MD10 118 88 I / O HD11 119 244 IN VDD 3.3 surface is 120 245 IN GND mt 121 89 I / O MD12 suRimtmm 122 90 I / O MD13 123 91 I / O MD14 124 92 I / O MD15 -22- installed-{Please read the precautions on the back first (Fill in this page) This paper size is in Chinese National Standard (CNS) A4 (210X297 mm) A7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 43671 Ο 4 Β7 5. Description of the invention (^ -¾) 125 246 IN VDD 3.3 tank supply 126 247 IN GND ship 127 93 I / O HD16 128 94 I / O MD17 SDRAM * i4ffiW 129 95 I / O MD18 130 96 I / O MD19 131 248 IN VDD 3.3 Suspended 132 132 249 IN GND 133 97 I / O HD20 134 98 I / O MD21 SDEAMli «Miscellaneous 135 99 I / O MD22 136 100 I / O MD23 -23- --------- t .------ IT ----- -^ (Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 size (210X 297 mm) Z13BT 1 〇 4 Α7 Β7 V. Description of invention (Au) Printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 137 250 IN VDD 3.3 »酺 138 251 IN GND Ship 139 101 I / O MD24 140 102 I / O HD25 141 103 I / O MD26 142 104 I / O MD27 143 254 IN VDD 3.3 face Na 144 255 IN GND 145 105 I / O MD28 SDRA dump swollen 146 106 I / O MD29 147 107 I / O MD30 -24- --------- install-{Please read first Note on the back page, please fill in this page),-° The size of the paper is applicable to China National Standards (CNS) A4 (210X297 mm) Α7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Consumption · Social Printing C4〇148 108 I / O HD31 149 256 IN VDD 3.3 side supply 150 257 IN GND m 151 109 I / O MD32 152 110 I / O MD33 153 111 I / O MD34 154 112 I / O HD35 155 258 IN VDD 3.3V power supply for Jg 156 259 IN GND m 157 113 I / O MD36 158 114 I / O MD37 sdram ^ m beach 159 115 I / O MD38 -25- I! -------- Kunyi-- ---- IT ------ ^ (Please read the notes on the back before filling in this page) This paper applies the Chinese National Standard (CNS) A4 standard (210X297 mm) Λ 3 6] '〇 λ Α7 Β7 V. Invention Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 160 116 I / O MD39 161 260 IN VDD 3.3V for Jg 162 261 IN GND Lion 163 117 I / O MD40 164 118 I / O MD41 165 119 I / O MD42 166 12α IN MSPCK MSP 糸 System auxiliary g 167 262 IN VDD 3.3V power supply for Jg 168 263 IN GND 169 121 I / O MD43 SDRAM ^ f® »170 122 I / O MD44 --------- Kunyi- -(Please read the precautions on the back before filling out this page)-β The size of the paper is applicable to China National Standard (CNS) Α4 size (210 X 297 mm) Α7 Central Standards Bureau of the Ministry of Economic Affairs 67 1 〇 B7 V. Description of the invention un) 171 123 I / O MD45 172 124 I / O MD46 173 264 IN VDD 3.3 side supply 174 265 in GND 龇 175 125 I / O HD47 176 126 I / O HD48 smmm ^ 177 127 I / O KD49 178 128 I / O MD50 179 266 IS VDD 3.3vm «i 180 267 IN GND m 181 129 I / O HD51 182 130 I / O MD52 -27- --------- batch- ----- ΐτ ------ ^ (Please read the notes on the back of vg before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Central Ministry of Economic Affairs Bureau of Standards Printed by I Industrial Consumer Cooperatives Λ3 67 1 Ο, at Β7 V. Description of the invention Uw〇183 131 I / O MD53 SDRAM data pool 184 132 I / O HD54 185 269 IN GND M 186 133 I / O MD55 SDRA Web S雠 187 134 I / O HD56 188 135 I / O MD57 189 136 I / O MD58 190 270 IN VDD 3.3V power supply 191 271 IN GND 192 137 OUT HD59 193 138 I / O _ -28- ------ --- Seeds ------ ΪΤ ------ (Please read the precautions on the back before filling out this page) This paper is suitable for China's National Loulou (CNS) A4 size (210X297 mm) ) 41 A3 67 '0 is the fifth, description of the invention U-called A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 194 139 I / O MD61 SDRAMM ^ Beach 195 140 I / O HD62 196 141 I / O mm 197 273 IN GND m 198 142 OUT MA23 memory address bit < 23 > 199 143 OUT MA24 memory warm address bit < 24 > 200 144 OUT RESET0 service chip 201 145 OUT TCS0L tile chip 202 146 OUT TCSIL turn Tile chip 203 147 OUT PD15_PA15 204 148 OUT PD14.PA14 舫 11 骊 ^ * »Out® Streaming BIOS PROHfiat 205 149 OUT PD13JA13 -29- (Please read the back first (Please fill in this page again)

* 1T (Chinese paper standard (CNS) Α4 size (210 × 297 mm)) Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs 4367 1 Ο, at Β7 V. Description of the invention (A flat) 206 150 OUT PD12_PA12 207 276 IN VDD 3_Lanna 208 277 IN GND Lion 209 151 OUT PDllJAll KS119S ^ * ™ Out of the PRO BIOS address 210 152 OUT PD10JA10 211 153 OUT PD9JA9 212 154 OUT PD8_PA8 213 278 IN VDD 3.3 Erna 214 279 IN GND Na 215 155 OUT PD7.PA7 KS113 | ^^ «Outgoing β BIOS P_Posing 216 156 OUT PD6_PA6 ---------- xiang ------ 、 玎 ------ ^ (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy 4 3 67 1 〇 * Α7 Β7 5 Description of the invention 217 157 OUT PD5JA5 218 158 OUT PD4_PA4 219 281 IN GND 220 159 OUT PD3_PA3 221 160 OUT PD2_PA2 ILS PROM mt 222 161 OUT PD1_PA1 223 162 OUT PDfLPAO 224 282 IN VDD 3.3 surface supply 225 163 IN vcc 5 Fiber supply Jg 22δ 164 IN C7 227 165 IN C6 BIOS EPROMS 228 166 IN C5 -31- --------- ^ ------ IT ------ ^ (Please read the precautions on the back before filling this page) The paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Λ36 ^ ° ^ Α7 Β7 V. Description of invention Mπ) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 229 167 IN C4 230 283 IN GND mt 231 168 IS C3 BIOS EPROMS ^ 232 169 IN C2 233 170 IN Cl 234 171 IN CO 235 286 IN VDD 3.3V power supply for the 236 172 OUT PROMCSL BIOS PROH chip_ 237 173 IN BGVS KS11 Zen alfalfa sync 238 174 IN BGHS KS119 horizontal sync 239 175 OUT MSSEL KS119 ^^ ®5 -32- --------- ^ ------ 1Τ ------ ^ (Please read the precautions on the back before writing this page) This paper Dimensions are applicable to China National Ladder Standard (CNS) Α4 specifications (21 〇 × 2mm) 6 3 Δ ο

7 B V. Description of the invention (4-Instructions to the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 240 176 IN BGCLK 241 177 Spare 242 178 IN vcc 5V power supply 243 289 IN GND m 244 179 OUT SCLK rib 11_ toilet 245 180 I / O SDAT KS11 array ^ brain 246 181 OUT SFES KS11 burst synchronization 247 182 spare 248 183 IN SERIALJN Lai Xian 249 184 OUT SERIAL.O towards output 250 185 IN A43SDFS 1843 CODEC ^ flgl ^ step 251 292 IN V0D 3.3V power supply For JS-33-pack-{Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (ΪΚΤ〆29 ·? Mm) 4367 1 Ο ^ Λ7 Β7 Economy Printed by the Ministry of Standards and Staff's Consumer Cooperatives 252 293 IN GND 253 186 IN A43SCLK 1843 CODECSfilS 254 187 OUT A43SDI 1843 CODEC ^ Ijg material output 255 188 IN A43SD0 1843 C0DEC ^ M »A 256 189 IN vcc mmm 257 190 IN TDI mommmx 258 297 IN GND m 259 191 IN TCK 260 192 OUT TDO JTA «» ^ Out 261 193 IN TRSTL JTAGSSliM 262 194 IN TMS JTAGiiit Fu-34- --------- Choose clothes ------ 1T ------ (Please read the note on the back first Please fill in this page for more information.) This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) 436 ^^ °, A7 B7 V. Invention description 263 195 OUT INTAL interrupt for PCI A 264 196 IN RSTL PCI reset 265 298 IN VLD 3.3 surplus 266 197 IN PCICLK PCI side 267 198 IN GNTL PCI rigid tower should be 268 199 OUT REOL PCI 266 299 IN 6® mt 270 200 spare (Please read the precautions on the back first Zai Su $: This page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 1, 5 Gambling racks 1 * 5 · 1 The makeup concept uses a highly optimized combination vector ib DSP library (executable by the vector processor) ) And system management functions (performed by ARM7), MSP provides its powerful and open environment. MSP separates signal processing development from main application software development, making it capable of -35- this paper scale is applicable to China National Standard (CNS) A4 specification (210X 297 mm) printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 4367 1 〇Α7 ___ «_B7 V. Description of the Invention (4 Seoul) Provide multimedia & communication with separable performance and effective cost, and easy to use and manageability. In addition, it will reduce application software development and maintenance costs. 1 * 5 * 2 The architecture of the MSP system is shown in Figure 7. The thick line area represents the part of the MSP system. The thin line area represents the internal pc application software and operating system: 铳 Ο 1 * 5 · 2 · 1 Μ 0 SA (Η υ 1 t. Impdia Operating S vstrm A γ π hi t. Rf: t. Ur fi 1 The operating system is called "MOS A", which is a subset of Microsoft's real-time operating system MM0SA. M0SA is a real-time, robust, multitasking, preemptive operation system, which is optimized for multimedia applications implemented on MSP. It performs the following main functions: .Interface to main window (ind 〇ws) 9 5 & window NT • Download selected firmware from the host • MSP tasks scheduled for execution in ARM7 and vector processors • Manage all MSP fault resources including memory & I / O components • Synchronize communication between MSP tasks • Report MSP-related interruptions, exceptions, and status situations-3 6-(Please read the notes on the back first (Fill in this page and write this page) This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 43 67 1 〇 Α7 body _ Β7 _ 5. Description of the invention M0SM is limited to ARM7 implementation. For more details, please refer to the MM 0 S A Instant Core Specification. 1 * 5. 2. 2 Media style: The Miaomo Mo multimedia library module provides a module of Dafanyuan, which performs such functions as information communication, MPEG video & audio, voice encoding and synthesis, sound card Compatible with audio and more. Each module is optimized for the MSP environment, and the system and design are executed in a multi-tasking environment. 1-5-3 Dangtian Temple. (TKUCQM I. TRRARY, 1-5-3-1 Make-up cracks on employee consumer cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before completing this page) With a suitable DSP body, MSP can be used to support sound applications with intercept, answer incoming calls, and store messages on the hard disk. The system speaker can be shared with a microphone to provide half-duplex hands-free listening SpeakerPhone (speaker phone) service * without the use of a telephone handset. The processing of incoming and outgoing calls is detected and used by the system. Phone processing tones can also be heard through the phone, the system speaker, and stereo headphones Or audio output channels, as if selected under program control. 1 · 6 Cheng Cheng Duo Ji Model 1-6-1 From the perspective of hardware, the MSP system contains two CPUs and several integrated peripherals. -37- The size of the paper method is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 OX 297 mm) 43 67i A7 Printed by the Central Consumers ’Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives. 5. Description of the invention 0r? The solution to this kind of cricket chip. From a software point of view, MSP is a high-performance digital signal processing (DSP, D i g i t a 1 s i g n a 1 P r 0 c e s s i π g) component that exists on the PCI bus. The MSP is achieved by the host CPU's control system as follows: • Pass through the PCI bus K to grab & write the MSP control & state register The shared data structure of the MSP region memory MSP program execution always starts with the ARM 7 CPU, which can then start a second independent execution flow in the vector processor. By using some shared processors (STARTVP, INTVP, TESTVP) in ARM7 and specific instructions (VJOIN, VINT) in vector processors, control synchronization between ARM7 CPUs and vector controllers can be achieved . Through the data movement instruction executed in ARM7, data transfer between ARM 7 and vector processor can be realized. The ARM7 CPU is typically responsible for the main interface, resource management, I / O component processing *, and most interrupt & exception handling. The vector processor is responsible for all your digital signal processing and some special interrupts, such as coprocessor interrupts (issued by the AKM7 to the vector processor) or hardware stack overflow (in the vector processor). The MSP also includes several integrated peripheral devices to interface to different I / O components. The addresses of all peripheral components are memory maps, and therefore can be accessed from the 檷 quasi-memory load & save instructions (by the ARM7 CPU or the halo processor). -38- This paper uses China National Standards (CNS) Λ4 specifications (210 x297 mm) --------- ^ ------ ΐτ ------ ^ (please first Read the notes on the back and fill in this tile) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs' 4 3 67 1 〇, at _Β7__ V. Description of the Invention (々 竹) 1 * 6-2 After power-up, the MSP will automatically enter a self-test sequence, and K fully verifies its functionality. The self-test sequence includes: • Initialization of all internal MSP registers • Self-test on the chip Diagnostics to verify all components of the MSP. 0 This self-test sequence is expected to yield approximately < 1 ^ (1 > seconds.) At the end of the self-test sequence, the MSP will be ready to perform the MS P? | Will include the loading and execution of the initial software of the MSP • The MSP's real-time operation system, the core of MMOS A, and the execution of the MSP support three types of resets: • Reset the hardware control system of the PCI bus • Reset through the control system of the PCI system reset bit in the MSP control register. • Reset via ARK7 & am also in the MSP control register. p; Restart to the control of the new boot bit. 1-6-3 The PC TBH register is like an I / O element on the PCI bus. The MSP contains a set of configuration registers. Defined in the PCI Rev. 2.1 specification and described in Listing 2-39- This paper size applies to the Chinese National Standard (CMS) A4 specification (2I0X297 mm) --------- ^ ----- -ΐτ ------ ^ (Please read the notes on the back first and then f this page) Consumption Cooperation by Employees of Central Bureau of Standards, Ministry of Economic Affairs, Du Printed 43671 05. Invention Description Μ 氺 0 中 〇 List 2 PCI configuration temporary storage Device offset description 0x00 Component & Vendor identification 0x04 Status & command 0x08 Class code & Version identification OxOC Miscellaneous register 0x10 MSP basic address register (MSP_BASE) 0x14 Virtual information segment buffer basic address temporary Device 0x18 basic address register 2 (unused) OxlC basic address register 3 (unused) 0x20 basic address register 4 (unused) -40- ------- --1 ------ it ------ Exercise (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (21OX 297 (%) 4 3 a: I " V. Description of the invention '丨 Bu A7 B7 one by one. -U—f) 0x24 Basic address register 5 (unused) 0x28 Reserved 0 X 2 C Reserved 0x30 Expansion ROM basic bit Address 0x3C Interrupted line-please refer to 6. Please refer to 6. Please print it from the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. • Please refer to 6 3 · 1 Yuan 侔 Srffi Merchant Register Register PCI Revision 2_1 to Get more details. 3.2 Current Status Register For the PCI bus specification revision 2.1M, get more details. 3.3 Interpolation HI & Revision Identification Temporary 考 Examine PCI Bus Specification Revision 2.1K for more details. M S P-1 E X, the category code is defined as 03, and the sub-category is 0. 3 .4 Miscellaneous g storage device 4 1-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ ------ 1T ------ line (please read first Note on the back, please fill out this page again) w 4 3 6 " Π 〇,: 7 Β7 V. Invention Description OrW) Please refer to the revision 2.1 of the PCI bus specification for more details. 1-6-3-5 MSP BASE address temporary storage path (MSP BASE) This register contains the basic address for the SP component. It is written by the host system (Windows 95 / NT) and is used by the MSP hardware for memory addressing. 1. 6. 3. 6 VFR address is too large 1. This register contains the basic address for the VGA virtual information segment buffer. It is written by the host system software (Windows 95 / NT) and is used by the MSP hardware used for the emulation of the VGA segment punch. 1,6.3.7 Show a certain address of MROM Please refer to PCI bus specification revision 2.1 for more details. 1.6, 3-8 Interruption, Elimination, and Evil Please refer to .E CI-bus specification revision 2.1R for more details. Printed by the Central Standards Bureau, Ministry of Economic Affairs, Consumer Cooperatives (Please read the notes on the back before filling in " this page}

1-6-4 ARM7 CPU ARM 7 RISC CPU is the main control processor of MSP. It contains a 32-bit data path and is suitable for the standard ARM7 instruction set architecture. ARM7 also includes special protocol processor instructions, and M and the vector processor interface. -4 2 — This paper is in the size of China National Standard (CNS) A4 (210X297mm). It is printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. .5 iSi vector processor is the DSP core of MSP. It contains a 28δ bit data path > and functions as a coprocessor to ARM7. Its functionality is described in the vector processor architecture literature. The vector processor M80MZZ implementation "includes six levels of wiring: fetch, decode, issuer, register access, execution and writer. It is optimized for DS-related processing. 1.6-6 Virtual Memory Management MSP-1EX does not support virtual memory management. 1-6-7 Interrupts & Riley's rationale Interrupts & exceptions in MSP are mostly achieved by ARM 7. All internal input / output component interrupts are entered into the internal 8254 interrupt controller. This interrupt is given priority judgment * and the highest priority 将 is sent to the ARM7K for further processing. 1.6.8 Official Mapping W Address Mapping ARM and vector processor programs use all MSP input / output element companion views as memory maps, which are rooted in the actual memory shown in Figure 8. Please note _, MSP address mapping (as in ARM7 or vector processor), starting from zero and extending to areas up to 2GB to 4GB, these addresses are mapped to the host (- 43- The size of this paper applies to China National Standard (CNS) A4 (210X297 mm) --------- ^ ------ ^ ------ ^ (Please read the Cautions will be scolded on this page) 4 3 6 Π Ο, at ____ _Β7_ V. Description of the invention (/ Ηθ

Pentium) pci address, from 0 to 2GB * according to the following relationship: (weight hex) main PCI address: = ARM7 address-80000000 This mapping allows the use of ARM 7 (or vector processor) from 2GB to 4 GB address to host PCI memory address with access range from 0 to 2GB. All host PCI memory addresses exceeding 2GB cannot be accessed by ARM 7. The main program (PentiuB) also considers all MSP input / output components as memory mapping, but it is based on a more limited actual address mapping as shown in Figure 9. Please note that from the perspective of the host program: • MSP_BASE is the beginning of MSP address mapping • HSP_BASE + 7DFFFFF is the end of MSP address mapping * This MSP address mapping is limited to this 128MB range only. Listing 3 MSP I / O component address mapping (please read the precautions on the back before filling in this page). Install the ARM7 address printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative [31: 0] (in hex) Host Address [26: 0] (in hex) Element-〇〇〇〇〇〇〇〇000000 0000000 internal ROM 0040 〇〇〇〇040040 0000 internal erase pad SRAM -44 'line paper paper scale applicable to Chinese standards (Cns) A4 size (210x297 mm)

6 3 A ο

7 7 AB V. Description of the invention Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Pui Gong Consumer Cooperative 00800000 080 0000 External synchronous DRAM 0480 0000 480 0000 Internal DR AM memory controller 0490 0000 490 0000 Internal virtual information segment buffer controller 04AO 0000 4A0 0000 Internal DMA controller 0 4 B 0 0 0 0 0 4B0 0000 KS0119 CODEC serial line 04 C 0 0 0 0 0 4C0 0000 KS0122 CODEC serial line 04C0 0200 4C0 0200 A01843 CODEC serial line 0400 0000 4D0 0000 Memory Volume data mover 04D0 A000 4D0 A000 to reserved 07BF FFFF 7BF FFFF 07C0 0000 7C0 0000 internal bit roll processor 07D0 0000 7D0 0000 internal 8259 interrupt controller-45- (Please read the precautions on the back before f this page) Binding. The paper size of the book is applicable to the Chinese National Standard (CMS) A4 (2 丨 OX 297 mm) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 43 67 1 〇, at Β7 V. Description of Invention 〇 ') 07D0 0010 7D0 0010 Internal 82 54 Timer 07D0 0020 7D0 0020 Internal 16540 UART 07E〇 0000 7E0 0000 to reserved 07DF FFFF 7DF FFFF 07DF FFF0 7DF F FFO MSP host control register 07DF FFF4 7DF FFF4 MSP ARM7 control register 07DF FFF8 7DF FFF8 Reserved 07DF FFFB 7DF FFFB Reserved 07E0 0000 to Reserved FFFF FFFF 8000 0000 Other main PCI devices (mapped to host to PCI memory 0 To 7 FFFF FFFF) -46- (Please read the notes on the back before filling in this page} This paper size applies to the Chinese national standard '{CNS) A4 size (210 × 2 ~ 7 mm) Printed by the consumer cooperative " 43 67 1 Ο, Α7 _________ Β7 V. Description of the invention (4 · ν〒)

FFFF FFFF 1-6.9 m. MSPilEX contains a special register. It is used for initialization and interruption by the host (Pentium processor). List 4 HSP host control register boundary locator # Description 0 PCI system reset 1 ARM7 & vector processor restart 2 MSP interrupt request from master (Pentium) 3 PCI host interrupt request from MSP 4 PCI host Interrupt confirmation 3 1: 5 Reserved bits < Q > PCI system reset. This bit is used by the host (Pentium > to completely reset the tilting MSP system hardware, which includes all MSP phases-4 7-This paper is scaled to China National Standard (CNS) A4 specifications < 210X297 mm 〉 II-:: «I install! [N ^ III line (please read the precautions on the back before completing this page) —43 6Ή 〇, A7 ____ B7 Printed by the Consumers’ Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Explains "Introduction of Art" Guan's internal & external input / output components. After a PCI system reset, MSP will perform its standard reset sequence, including execution for ARM 7, CPU and I / O bits All self-diagnostics on the chip. This reset has the equivalent effect of a hardware system reset. The bit < 1 > ARM 7 & vector processor restarts. This bit image is hosted by the host (Pentium) The M used restarts the ARM7 and vector processors. This restart is somewhat different from a complete PCI system reset. That is, the MSP has not performed any normal reset sequence and has not performed any self-tests on the chip. Diagnostics. When this bit system is set * ARM7 will start It runs at address 0, and the vector processor will enter the idle horizontal mode. It will not affect any internal or external I / O components. Bit < 2 > MSP interrupt request from Pentium . This bit is directly used by the anchor (Penti U ·), K is directly lip MSP, and it is connected to the internal 825 9 Programmable Interrupt Controller (PIC) Programmable Interrupt Controller ^. ^ M — It is then used to interrupt ARM7. This bit is set by the host .. 槺 (Pentium) * and cleared by ARM7. Bit < 3 > PCI Master 榇 interrupt confirmation. This bit is determined by the host ( Pentium) is used to confirm a PCI master interrupt request generated by MSP. This bit is set by the host (Pentium) and cleared by ARM7. -4 8-Install-(Please read the precautions on the back before filling This page), 1T '竦 This paper size is applicable to Chinese National Standard (CNS) Α4 size (210 × 297 mm) Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4367 1 Ο * Λ7 V. Description of invention ; 3l: 4 > Reserved 1 · 6 1 0 tLSP OM7 control register msp_iex contains one Special register, which is used to interrupt the host {by ARMT processor). List 5 MSPAR Μ7 Control register boundary bit # Description 0 Request from PCI host in HPS 3 1: 1 reserved bit < 〇 > The PCI master interrupt from MSP. This bit is used by the M interrupt host used by the MSP, which is announced through the action of the PCI INTA # pin of the PCI bus 1. This bit is set by ARM and is cleared by the main stream (Pent iuB) through the PCI stream.

Bits < 3 1 ·. 1 > Reserved 1.6.11 MSP ^^ g »ROM Internal ROM includes a total of 16K bit sisters, and includes: • ROM initialization software • Self-test diagnostic software • Different management systems System • Different library subroutines-4 9-This paper size is applicable to China National Standard (CNS) A4 specification (210X: J97 mm) --------- Seed clothing ------ , η ------ ^ ί Please read the notes on the back before filling in this page)

U 7 1 ϋ Α7 Β7 Printed by Shellfish Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of Invention (々phenomena) • The address mapping of high-speed yuan memory for certain instructions and data constants is described in Listing 6 , As later. List 6 internal ju ROM address mapping --------- '^ ------ ΤΓ ------ it (Please read the notes on the back of the product before filling in the spirit) Shift (hexadecimal) Description ARM7 Set & Initialize Address Vector Processor Reset & Initialize Address FALU Macro Cell Self Test Diagnosis SRAM Macro Cell Self Test Diagnosis Vector Processor Core Self Test Diagnosis High Speed Yuan Chongji billion body controller self-test diagnosis memory controller self-test diagnosis PCI bus self-test diagnosis-50-This paper size is applicable to the Chinese national standard (CNS) A4 (2IOX297 public) 4 3 67 iq 5 、 Invention note (Ay 丨) A7 The self-test diagnosis of the bit stream processor printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs --- DH A controller self-test diagnosis 8254 internal timer self-test diagnosis --- — 8259 Interrupt controller self-test diagnosis 1 6 4 5 0 UART register self-test diagnosis KSG122 serial line self-test diagnosis KS0119 serial line self-test diagnosis A01843 serial line self-test diagnosis ARM 7 input & output element interruption Device ARM 7 input & output interrupt processing device 1 ARM 7 round input & output output interrupt processing device 2 ARM 7 input & output output interrupt processing device 3 -5 1- equipment ---- order ------ Baht (please read the notes on the back before filling this page) This paper standard is in accordance with the national standard (CNS M4 specification (2! 0X297 mm). Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy 4367 10, A7 B7 __—- '> Description of the invention-^ ARM7 instruction exception handling device vector processor interrupt (by ARM7) ----- vector processor breakpoint exception --- vector processor DSP library Example MPEG-1 video library subroutine example MPEG-1 audio library subroutine example MPEG-2 video library subroutine example MPEG-2 audio library subroutine example Line program V.34 DSP library sub-routine phone application sub-routine phone-52- --------- ^-(Please read the precautions on the back of 8a before 'This page) Order The size of this paper is in accordance with China National Standard (CNS) A4 (210x297) 4367 1 〇 5. (05) 2D image library subroutine travel type 3D image library subroutine travel type H. 261 library subroutine travel type H.263 library subroutine travel type G. 7 28 library subroutine travel type G . 7 2 3 library sub-routines ARM7 selling material constant vector processor data constants --------- ¾ ------ 1T ------ ^ C Please read the tears on the back first (Notes on this page again) This page is printed by the Central Bureau of Standards of the Ministry of Economic Affairs and printed by the Cooper ’s Cooperative of 1.6.12 MSP Meat Department SR AM depends on the status register (VCSR, V ect) 〇r & C ο π tr ο I & Statusregister), the internal SRAM can be used as a high-speed memory or area memory. In the area memory mode, its address space is mapped to the internal SRAM part, which starts at the position < H C P _ B A S E >: 0 4 0 0 0 0 0. 1.6.13 HSP Meat Department Adjuster-53- This paper uses Chinese National Standard (CNS) A4 (2 丨 0X297 mm) 43 67 1 〇, Α7-~~~ -___ ^ __ 5. Explanation (Seven Seals) (Please read the notes on the back before ^ r on this page) «sp also includes thousands of peripheral equipment • Existing in its two internal busbars: 64-bit 80MHZ F? Busbars, The 10 and 32-bit 40MHz 10 丨 components that should be streamed on the FM stream include: • Memory controller for external synchronous DRAM • A virtual segment buffer interface • One for external PCI / streamer PCI 擓 rolling controller • customer ASIC interface • —an eight-channel DMA controller • —a memory device for moving data (used to transfer data from / to SDRAM) • KS0122 codec serial line • KS0119 钃 brick decoder serial circuit • KS1843 encoder / decoder serial circuit components on the 10 stream line include: • 8254 compatible programmable interval timer • 8259 compatible programmable Interrupt controller (eight levels). 1 pt 1 64 50 compatible UART serial line central standard of the Ministry of Economy Printed by the Consumer Cooperative of the Quasi Bureau • A Bit Stream Processor for MP P EG Video Bit Stream Decoding & Agitated Bit Stream Processor The address map of the registers of these peripheral devices is shown in Listing 7. List 7 Internal Peripheral Device Address Map -54- This paper size applies Chinese National Standard (cns) a4 specification (2ι〇χ 297 mm) 〇 〇! !! 7 6 3 4 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of invention (a «) Description of component address offset (hexadecimal) 4A0 0000 Current address register 0 (bit < 31: 3 >) 4A0 0008 Current address register 1 (bits < 31: 3 >) MAP 4A0 0010 Current address register 2 (bits < 31: 3 >) DMA 4A0 0018 current address Register 3 (bits < 31: 3 >) Controller 4A0 0020 Current address register 4 (bits < 31: 3 >) 4A0 0028 Current address register 5 (bits < 31 : 3 >) 4A0 0030 Current address register 6 (bits < 31: 3 >) 4A0 0038 Current address register 7 (bits < 31: 3 >) 4A0 0050 Stop address register 〇 (bit < 31: 3 >) 4A0 0058 stop address register 1 (bit < 31: 3 >) 4A0 0060 stop address register 2 (bit < 31: 3 >) 4A0 0068 Stop address register 3 (bits 01: 3 »4A0 0070 Stop address register 4 (bits < 31: 3 >) 4A0 0078 Stop address register 5 (bits < 31: 3 >) 4A0 0080 Stop address register 6 (bit < 3i : 3 >) 4A0 0088 Stop address register 7 (bits < 31: 3 >) 4A0 00A0 Status register -55- I Xiang-(Please read the precautions on the back before this page) This Paper size is applicable to China National Standard Vehicle (CNS) A4 specification (210X297 mm) Customized 43 67 1 Ο Α7 V. Description of the invention (ΐβ) Printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economy 4A0 00A8 Control register A 4A0 00B0 Mask register memory data mover 4D0 0000 MSP current address register 4D0 0008 Host destination address register 4DO 0010 MSP stop address register 4D0 0018 Host stop address register 4DO 0020 4D0 0028 Control Register 56- ^ — (Please read the precautions on the back before washing this page) The size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm) ^ 43 67 1 〇, 5 Description of the invention (consumption cooperation between employees of the Central Standards Bureau of the Ministry of Economic Affairs and Du printed VFB component address offset (hexadecimal) description KS0122 serial line 04C0 2000 information segment size register 04C0 2001 Π) 04C0 20 02 Control / data byte-57- --------- 1 clothing ------ 1T ------ ^ (Please read the precautions on the back before filling this page) This paper Dimensions are applicable to China National Standards (CNS) AO Grid (210X297 mm) 4367 1 〇, Λ7 Β7 V. Description of the invention 〇κ〇 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 04CO 2003 Index / Data 0 04C0 2004 Suo Gong 1 / Information 1 04C0 2005 Cable bow 丨 / Data 2 04CO 2006 Cable Bow 丨 / Data 3 04CO 2007 Reserved 04C0 2008 Read data serial interface Q4C0 2009 Reserved 04C0 200A Logic control register 04C0 200B Reserved 04C0 200C Reserved O4C0 200D Reserved-58- --------- 1 ------ IT ------ ^ (Please read the precautions on the back before continuing on this page) This paper applies Chinese national standards according to standards (CNS) Α4 specification (2! 0 × 297 mm) Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, A7 Β7 V. Description of the invention (/ 4) 04C0 200E Status register 04C0 200F Reserve 04B0 2000 Information section size register KS0119 04B0 2001 ID Serial Line 04B0 2002 Control / Data Bit Sister 04B0 2003 Cable Bow 1 / Zeke 0 04B0 2004 Cable丨 / Information 1 04B0 2005 Index / Data 2 04B0 2006 Cable Bow 1 / Data 3 04B0 2007 Status Register 04B0 2008 Snap data serial interface 04B0 2009 Read PROM data -59- -------- -Install ------ Order ------ Line (Please read the precautions on the back before filling in this page) The standard of this paper is applicable to China National Standard (CNS) Α4 specification (2 丨 0 乂 297 mm) 6 3 4 ο 5. Description of the Invention (Ik) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 04B0 200A Logic Control Register 04B0 200B HS, VS Polarity 04B0 200C HS Offset O4B0 200D VS Offset 04C0 200E Reserved 04CQ 200F Reserved component address offset description (hexadecimal) AD1843 04C0 4D00 DAC1 control register write data input CODEC (for writer only) Interface 04C0 5000 DAC2 control register write data input (for write only) 04C0 6000 ADC left control register write data input (for writing only) 04C0 7000 ADC right control register write data input -60- ^ .-- (Please read the precautions on the back before filling this page )-The size of this paper is applicable to Chinese national standards (CN S) A4 size (210X297 mm) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives 4 3 67 1 Ο 4 V. Description of the invention (for writing only) 04C0 4000 + 2 04C0 5000 + 2 O4C0 6000 +2 04C0 7000 + 2 DAC1 control block input DAC2 control block input ADC left control block input ADC right control word sister input 04CO 4000 DAC1 control register write to physical output (for capture only) 04C0 5000 DAC2 control register Write data output (read only) 04C0 6000 ADC left control register Write data output (only grab) 04C0 7000 ADC right control register Writer data output (read only) 04CO 6000 AD_C left Flag Register + 2 04C0 7000 ADC Right Flag Register -61- --------- Seed Clothing ----- 1T ------ ^ (Please read the Note: Please fill in this page again) This paper size is applicable to Chinese National Standard (CNS) A4 (2 丨 〇 X 297mm) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 43 1 Ο Λ Α7 Β7 V. Description of the invention U ) + 2 04C0 6000 ADC left first data + 10 04C0 6000 ADC left second data ten 12 04CQ 6000 ADC left Three data + 14 04C0 6000 ADC left fourth data + 16 04CO 7000 ADC right first data + 10 04C0 7000 ADC right second data + 12 04C0 7000 ADC right third data + 14 04C0 7000 ADC right fourth data + 16 04C0 4000 DAC1 control flag register + 20 04C0 5000 DAC2 control flag register -62- --------- ^ ------- ΐτ ------ Huai (please first Read the notes on the reverse side and reprint this page) This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 4367 1 Ο Α7 V. Description of the invention 〇Κ3〇 Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs + 20 04C0 6000 + 20 04C0 7000 +20 ADC left control flag register ADC right control flag register 7D0 0000 Initialization command block 1 Undefined initialization command block 2 (unused) 8259 Undefined initialization command Block 3 (unused) is made by the ίFang Ripper 7D0 0004 initialization command block 4 7D0 0004 job control block 1 7D0 0000 job control block 2 7D0 0000 ticket control block 3 7D0 0010 counter # 0 Register (R / W) 7D0 0014 Counter Π Register (R / tf) -63- Pack-(Please read the precautions on the back first, then this page)

, tT 涑. This paper size applies Chinese national standard (CNS > A4 size (2iOX297mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 43 6 ”0, V. Invention description U-8254 timer 7D0 0018 counter # 2 Register (R / tf) 7D0 001C Control Block Register U) Component Address Offset (Hexadecimal) Description 7D0 0020 Receive Register Issues Register Divisor Register 7D0 0024 Interrupt Identification register 16450 UART 7D0 0028 Interrupt enable divisor register 7D0 002C Line control register 7D0 0030 Modem control register 04CO 0034 Line status register -64- --------- 1 ------ IT ------ (Please read the precautions on the back before ^^^ this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards 4367 1 〇, Α7 Β7 V. Description of the Invention (/ β) 04CO 0038 Modem State Register 7D0 003C Cursor Register 7C0 0000 to 7C0 0003 PB Processing Floor Register 7C0 0004 to 7C0 007 ΒΡ control register 7C0 0008 to 7C0 000Β input Buffer Q start address bit stream processor 7C0 000C to 7C0 000F input end address 7C0 0010 to start position of input element 1 -65- ------ --- ^ ------ ΐτ ------ ^ (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) Α4 specification (210X 297 mm) Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China 4 3 67 1 〇, A7 B7 V. Description of the invention (, 40 7C0 0013 7C0 0014 to 7C0 0017 Input end address of buffer 1 7C0 0018 to 7C0 001B Output element punch 0 Start address 7C0 001C to 7C0 001F End address of output buffer 0 Bit stream processor 7C0 0020 to 7C0 0023 Start address of output buffer 1 7C0 0024 to 7C0 0027 Output end address of output buffer 1 7C0 0028 -66- This paper size applies to Chinese National Standard (CMS) A4 (2 丨 0 '乂 297'mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 67 1 〇 Α α7 B7 V. Description of the invention (Cantonese) to 7C0 002B This article stores the start address 7C0 002C to 7C0 002F for the line The byte address of the last data of the double bracelet guard is 7C0 0030 7C0 0031 The least significant bit of the BP status register. The least significant bit is 7C0 004E 7C0 004F. The next most significant bit is the BP status register. Highest effective unit 7C0 0050 to .7C0 0053 BRitim register TC0 0054 to 7C0 0057 BP interrupt mask register and image vertical and horizontal size (number of macro blocks) 7C0 0058 ARM7 interrupt request pin -67- (Please read the precautions on the back of this page before this page.) This paper uses the Chinese National Standard (CNS) A4 size (210X 297 mm) 4367 1 Ο Λ7 Β7 V. Description of the invention 4-Wf) 7C0 0059 to 7C0 005F Reserved Address offset (hexadecimal) for future expansion components Description Bitstream processor 7C0 0060 to 7C0 19F B? Cache area 7C0 01AO to 7CF FFFF Reserved for future expansion (please first (Please read the notes on the back and fill in this page again.) The Central Standards Bureau of the Ministry of Economic Affairs—Industrial and Consumer Cooperatives Co., Ltd. printed 1.6.14 ΤΠ Asahi row fixed edge borrowing 1.6.14.1 S2R4 phase-capable BK device MSP includes a Standard 8254 compatible program The interval timer is used by the software and has the following functions: • Includes three independent 16-bit counters • Supports six programmable counter modes. All counters are written into the control register and initialized by Count _ 6 8 _ This paper size is in accordance with Chinese National Standard (CNS) A4 specification (2 丨 0X 297 mm) A7 d 3 \ ^ B7 V. Program description for invention description. Copy Register This register contains different control information for the timer. Its bit definition is described in the list 8, as follows: List 8 control block register bit # Description 0 BXi) Count selection (default: binary) 3: 1 Count mode: 0 0 0: Mode 0 0 0 1: Mode 1 X 1 0: Mode 2 X 11: Mode 3 1 〇0: Chess 4 1 0 1: Horizontal 5 5: 4 Pick / write selection: 0 〇: Counter latch command 01: Only 謓Get / Write Least Significant Byte 10: Only grab / Write Most Significant Byte 11: Read / Write Least Significant Byte First, Read Later (CNS) Α4 specification (2 丨 0 × 297 mm) --------- ^ ------ 1T ------ (Please read the precautions on the back and write this page) Printed by the Central Standard Consumer Work Cooperative of the Ministry of Economic Affairs 136 ~ Π Ο Α7 ______87 V. Invention Description Writer Most Significant Byte 7: 6 Select Counter: 00: Select Counter 〇01: Select Counter 1 Η: Select Counter 2 11: Select counter 3 status register. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. This register contains the status information of the timer. Count 0, 1 2 This three counter is the main counting element of the timer. Each counter is 16-bit wide, can be preset first, and counts down in binary or BCD mode. The inputs, gates, and outputs are configured by the mode selection stored in the control block register. These three counters are completely independent of each other. 1.6.14.2 S25Q Phase Interruptible Beech 5S (PTT) MSP Programmable Interrupt Controller is the standard 8259, which is used in all X86-based personal computers. Its functionality includes: • Supports eight levels of precedence order • Programmable interrupt mode • Individual request mask capacity in MSP-1EX, these eight levels of interrupt input are temporarily assigned to different I / O components * such as After: -70- --------- Meal ------ ΪΤ ------ 't (Please read the precautions on the back before writing this page)' This paper size applies China National Standard (CNS) A4 specification (21 〇X 297 mm) 43671 〇, Α7 Β7 V. Description of invention (Α_ / ΐί) Level 0 (highest) is assigned to 8254 timer • Level 1 is assigned to virtual information Duan Yuan Chong (VFB) (please read the notes on the back before going to this page). • Tier 2 is assigned to the customer ASIC edit block, including DM A controller. • Tier 3 is assigned to the bit stream processor. 4 Series Assignment to PCI? Grip Interface • Level 5 Series Assignment to Ubd > • Tier 6 Series Assignment to < 0 (1 >

• Layer 7 is assigned to 16 5 5 0 The output signal of the UART interrupt controller is connected to the ARM7 RISC CPU interrupt request line (n FIQ). Register Description The three 8-bit registers are used to initialize the PIC by using K. * Initialization command block 1 (ICW 1) • Initialization command block 2 (ICW2): Not used for MSP-1EX • Initialization command word Group 3 (ICW3): Not used for MSP-1EX • Initialization command word 4 (IC ¥ 4) The other three 8-bit registers are used to control PIC operations by M: Plough • Job Control Block 1 (0 CW 1) • Job Control Block 2 (0 CW 2) • Job Control Block 3 (0 CW 3) Please note that the addressing of all these registers is specifically in place The address portion (bit < 0 >) is encoded with the data portion. Please refer to standard 8 2 5 9 size M for more details. -71- This paper size applies to China National Standards (CNS) A4 (210 X 297 mm) 43 67 1 〇, A7 B7 Printed List of Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 9 8259 Register Description Name Description IGW1 < 7: 0 > Initialization command byte 1 bit < 0 >: ICW4 system required bit < 1 >: Must be "1" (Junyi 8259 only) bit < 2 > : Undefined (calling address range) Bits < 3 >: Must be "1" (Level trigger mode) Bits < 4 >: Must be "1" Bits < 7: 5 >: Undefined (interrupt vector address) ICW2 < 7: 0 > Initialization command word 2 (unused) ICW 3 < 7: 0 > Initialization command block 3 (unused) ICtf1 < 7: 0 > Initialization Command Yu group 4 bits < Q >: Must be "1" (8 086 chess style) Bits < 1 >: Interrupt auto-end bit < 2 > ·. Unbounded positioning element < 3 >: Must be (unpunched mode) Bits < 4 >: Special full nest mode -72- This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ----- --- -^-(Please read the precautions on the back before writing this page)> The work of the Central Standards Bureau of the Ministry of Economics and the Ministry of Economic Affairs and Consumer Cooperation. Printed by the agency L A7 B7 Invention Description kW)-Bit < 7: 5 > : Must be "0" OCW 1 < 7: 0 > Operation control block 1: Interrupt enable mask bit < ιι > Enable interrupt 0CW2 < 7: 〇 > for input request # π Job control block 2 bits < 2: 0 >: Interrupt level to be applied < 4: 3 >: Must be "(T bit < 7: 5 >: 001: Non-specific Ε0Ι Command 011: Specific EOI Command 101: Rotate to non-specific EOI Command 100: Rotate human automatic EOI Mode (set) 0 0 0: Rotate into automatic EO0I Mode (clear) 111: Rotate to specific EOII Command 110: Set priority Sequence command 010: No job 0 CW 3 < 7: 0 > Job control block 3 bits < I: 0 > 10: Read interrupt request register (IRR) 1 1: Read service temporary Device USR) 00: No effect -73- This paper wave scale is applicable to China National Standards (CNS) A4 specification (210X297 mm) --------- ^ ------ 1T ----- -^ (Please read the notes on the back first Complete this page) 43 6/1 square ~ - V. invention described! ^ _ 丨 Shoulder A7 B7 〇1: Inactive bit < 2 >: Polling command bit < 4: 3 >: Must be bit < 5 >: Special mask mode bit < 6 >: Enable special mask mode bit < 7 >: Must be "0" Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 1 6 1 4 · 3 164fi0 Phases: > ΠΑΡΤ tandem road MSP includes a 16450-compatible UART serial line, which is used as an interface to external serial I / O components. Please refer to the standard 16450 size M for more details. 1-6-14.4 Bit Clamp The bit stream processor is a dedicated logic block that processes video bit stream data. Its functionalities include: * Variable-length Huffman decoding and encoding • Unpacking and packaging of video data in the M-Zig (ZIG-ZAG) storage format • Other miscellaneous bit-level calendar processing A Concurrent processing unit operates and is under the software control of a vector processor or ARM7. For more details, please refer to the bitstream processor section. 1.6.15 ΠΒ 涪 棑 Fixed F? Calendars and peripherals include • Customer ASIC fun interface 74- This paper 怅 size is applicable to China National Standards (CNS) M specifications (210x29 * 7mm) ---- ----- ^ ------ 1T ------ Beam (Please read the precautions on the back again?! · This page) A7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 43 67 1 Ⅴ. Description of the invention 〇 () • Tilt eight-channel DMA controller. To Samsung KS (H19 video encoder serial line interface • To analog component AD1843 audio & telecommunications serial line interface 1.6. 15.1 ASIC and General Interface This section contains the interface logic for all external codecs and customer-specified AS 1C logic blocks. This block is implemented entirely in hardware and has no registers for visible programs. Please refer to the chapter of the ASIC interface for more design details. 1.6.15.2 Π Μ A Controller MSP-1 EX includes a DMA controller on the chip, which has the following functions:. Eight independent DMA channels • Enabling / disabling control of individual DM A channels • 10 components to memory transfer, or vice versa • Address increase or decrease For more details, please refer to chapter M of the AS 1C interface. 1.6.15.3 Ji understands that all routers MSP-1 Ε × also contains another special memory data mover, which is used to move between the master and the master.楗 （Pent iue） The spring material between the memory and the SDRAM memory in the MSP area. The memory data mover is basically a special DMA controller. It contains the following registers: * MSP current address register • · This 32-bit register is defined as the address of the SDRAM memory at the beginning of the memory data transfer. This register -75- installed ------ iT ------ '' (Please read first (Notes on the reverse side of this page are reproduced on this page.) This paper size is applicable to national standards (CNS > A4 specifications (2toX 297 mm) A7 B7. 5. The description of the invention can be read or written by ARM7, and its initial value is determined by Loaded in ARM 7 ° This address will be incremented based on the size of the asset transfer. Please read the notes on t6 and fill in it first. Write. The host's current address register on this page: this 32-bit register This register is defined as the host memory address at the beginning of the memory data transfer. This register can be retrieved or written by arm 7. Person * and its initial value should be loaded by ARM 7. The address should be incremented based on the data transfer size. MSP stop address register: This 32-bit register is defined at the end of memory data transfer SDRAM memory address. This register can be read or written by ARM7 and will be used to compare with the MSP current address register. If they match, the memory data mover will generate a signal that the MSP processing is complete. Master / Stop Address Register: This is a 32-bit register that is defined by the host to remember the hip address at the end of the memory address transfer. This register can be retrieved or written by ARM7, and M will be compared with the host's current address register. If it is matched, the memory hip equipment mover will generate a signal that the main processing is finished. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economy Status Register: This register contains the status information of the memory data mover. The bit encoding will be as follows: < 0 >: MSP ΕΟΡΟ This bit specifies whether the memory data mover has reached the MSP stop address. If ARM7 initializes the resource current address register ’this bit will be reset to 00800000 (hexadecimal). This bit should only be read by Α ί Η 7 and not written. 76 The paper size applies to China National Standard (CNS) A4 (2! OX297 mm) w Δ3Β1 A 〇. A7 B7 V. Invention Explanation 〇 »,) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs < 1 >: Host EOP. This bit specifies whether the memory data mover has reached the main stop address. If ARM 7 initializes the host's current address register, this bit will be reset to 80000000 (hex). This bit should be read by ARM7 only and not written. • Control Register: This register contains information about the memory data mover. The bit encoding will be as follows: < 〇 >: Fang Shang. This bit specifies the direction of data transfer. If this bit is "0" (default), the data transfer direction will be from the memory of the host (Pentiun) to the HSP SDRAM memory. If this bit is "1", the direction is from SDRAM to main memory. This bit should be written by ARM7. < 1 >: Interrupt enable. This bit specifies whether the Memory Skeleton Data Mover should interrupt ARM7 at the end of data transfer. This bit is not written by ARM7. < 2 >: DMA is enabled. This bit enables the memory data mover to operate. This bit should be written by ARM7. < 3 >: Data transfer size. If this bit is "0" (not set), the size of each memory data transfer will be 32 bytes. If this bit is "1", the size will be 64 bytes. This byte is written by ARM7. 1.6.15.4 KS 0119 Xun 16 reef installation string? II 路 路 介 而 -7 7- --------- ref -------- ir ------ ^ (Please read the notes on the back first to save this page) This paper size is applicable to China National Standard (CNS) A4 specification (2tOX297 mm) 4 3 6/1 〇 Α7 Β7 V. Description of the invention (y! | -Finance) KS 0119 video encoder serial line interface includes: The data buffer register 1 contains the read data from the codec. • A two-stage buffer sending buffer register containing data written to the brick decoder. • One-time control & status register, which contains different control & status information for serial lines. List 10 KS0119 video encoder serial line interface register (Please read the precautions on the back before writing this page) Address offset (hex) Bit width description 00 8 Receive data Yuan punch register 0 1 8 Transmission data buffer register 02 8 Control & status register The Central Code Bureau of the Ministry of Economic Affairs and Consumer Cooperatives printed the bit code of the control & status register as follows: Bit < Q > The receive data buffer is full. This bit is set when the serial line has received eight-bit data from the KS 0113 codec. If the interrupt enable (bit < 7 >) is set, an interrupt request will also be issued to ARM 7. -7 8-This paper size applies to the national standard of the country {CNS) A4 is now available (210X 297 mm) A7 d3 67 1 〇, ____B7_____ V. Description of the invention bit < 1 > The sending data buffer is empty (Empty). This bit is set when the serial line is ready to send data to the KSQ119 codec. If the interrupt enable (bit < 7 >) is set, an interrupt request will also be issued to the ARM 7. Bit < 7 > interrupt enable. This bit is used to enable the interrupt request to the A RM 7 〇1.6.15.5 A Π 1 8 4 咅 ί Thunder Xun Li Tan Road broker AD 1843 serial line interface includes: • A set of double buffer temporary Register, which contains data retrieved from the codec. • A set of registers for the Shuangyuan puncher, which contains the data written to the code resolver. • A control & status register containing different control & status information for serial lines. Please refer to chapter K of the AD 184 3 codec interface for more details. 1,6.16 Point of view Listing 11 shows the performance of instructions in the vector processor cycle count, where each cycle is equal to 1 2 · 5 n s. The width of the external memory bank is assumed to be 64-bit and clocked in the paging mode of 4QMHZ. All instruction performance is provided in a 32-bit direction. The protocol is as follows: ras: the number of cycles required by the external memory for the first access. It is typically equal to 75ns or 6 cycles. -79- This paper size is applicable to the National Standard for Difficulties (CNS) A4 (210X297 mm ')' ~~ ----------------------------- Please read the notes on the back before printing this page.) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. The number of cycles used to execute the first instruction. Rate (rate): The number of cycles between execution of similar consecutive instructions. When the waiting time is the same as the rate, only one number will be shown. Recall sign byte (8 / 9-bit) Half-word (16-bit) Word (32-bit) Floating point (32-bit) VCACHE VLCB Wait time = 4, rate = 2 VLCB. off wait time = row address strobe +9, speed kill = row address strobe VLR wait time = 3, rate = 1 VLR.off wait time = row address strobe +8, rate = row address strobe VL waiting time = 3, rate = 1 VL.off waiting time = row address strobe +8, rate = row address strobe -80- This paper music standard is applicable to Chinese national standards {CNS) Α4 specifications ( 210X 297 mm) I Binding. Thread (please read the precautions on the back before ^ this page) Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4 3 671 Ο, α7 Β7 V. Description of the Invention VLD wait time = 4, rate = 2 VLDoff wait time = row address strobe +12, rate = ES VLQ wait time = 6, rate = 4 VLQoff wait time = row address strobe +20, rate = 6 VPFFCH Row address strobe + (cache line #) X4 mnemonic sign byte half-byte character floating point (8 / 9-bit) (16-bit) (32-bit) (32 -Bit) VLWS wait time = 4, rate = 1 VLWS.off wait time = row address strobe +8, rate = row address strobe VLI 1 VSTCB wait time = 4, rate = 2 VSTCBoff wait time = row Address strobe +9, rate = line address strobe -81- --------- ΐ 衣 ------ ΐτ ------. Line, (Please read the back (Notes again ^ private page) This paper size applies to China National Standard Soap (CNS) Α4 specifications (210 × 2ί &7; 7 mm) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ 3 67 1 〇, at Β7

VST wait time = 4, rate = 1 VST.off wait time = row address strobe + 8, rate = row address strobe VSTD wait time = 5, rate = 2 VSTD.off wait time = row address strobe +12, rate = 8 VSTQ wait time = 7, rate = 4 VSTQoff wait time = row address strobe + 20, rate = 16 VSTR wait time = 4, rate = 1 VSTR.off wait time = row address Strobe +7, rate = line address strobe VtfBACK line address strobe + (high-speed buffer memory line #) x 4 CFC -82- CTC --------- ^ ----- -ΐτ ------. ^ (谙 Please read the notes on the back before v- ^ this page) This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210 X 297 mm) 43 67 1 Ο, at Β7 5. Description of the invention (/ -to)

~ 83-This paper size applies to Chinese National Standards (CNS) A4 (2 丨 0297mm) A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ^ 4367 1 〇Β7 V. Description of the invention Cal) FORK 6 RESUME 6 SYNCH 4 VCBR 2 VCBRI 2 VD1CBR 2 VD2CBR 2 VD3CBR 2 VCJSR 2 VCJSRI 2 VCJSR 2 VCINT -84- 4 Gutter (please read the precautions on the back before this page) This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297) (B) Printed by the Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 4367 1 〇 λ Α7 Β7 V. Description of Invention (VC) 0 VCJ0IN 4 VCCS 2 VADD 2 (waiting time) VADDH 1 (speed) VAND 1 VASL Undefined VASA VAAS3 VASS3 VASUB 2 (waiting time) VAVG 1 (speed) • 85— Thread setting (please read the precautions on the back before ViC page) This paper size is applicable to China National Standard (CNS) A4 specification (210 '乂 297mm) Employees' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs, India and India 4 3 671 Ο 』Α7 Β7 V. Description of the invention VAVGH VAVGQ VCVTIF Not Meaning 2 (Wait time 1 (rate) Undefined VCMPV 1 2 (Wait time 1 (rate) VCNTLZ Undefined VCVTB9 VCVTFF Undefined 2 (Wait time U rate) Rib memory symbol byte (8 / 9-bit) half Word group (16-bit) Word group (32-bit) Floating point (32-bit) VDIVI VDIVS -86- installed ----- 1T ------ ^ C Please read the back (Notes on this page again) This paper size applies to China National Standards (CNS) Α4 size (2! 0 × 297 mm) Α7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 43 67 1 〇 Β7 V. Description of the invention CaW )

Thread setting (please read the precautions on the back before this page) This paper size is applicable to the Chinese National Standard (CNS) A4 size (210X297 mm) A7 Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Off-line Consumer Cooperative, w 4 3 67 1 〇, B7 V. Description of Invention (Person)

--------- I ------. 11 ------ line (please read the precautions on the back first>. Gas page) This paper size is applicable to Chinese national standards ( CMS) A4 specification (2Ϊ0 × 297 mm> 4 " 436/10 A7 B7 V. Description of invention Uw) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

V0R 1 Undefined VR0UND Undefined 2 (Wait time 1 (Rate) Rib Sign Byte Halfword Block Float (8 / 9-bit) (16-bit) (32-bit) (32 -Bit) VSHFL

VSHFLH

VSHFLL --------- install ------ order ------ Vi (Please read the precautions on the back before copying this page)

VUSSHFL

VUNSHFLH

VUNSHFLL VSUB 1 -89- Undefined 2 (waiting time) This paper size applies to the Chinese national standard (CNS) A4 (2 丨 OX297 mm) 5 4 3 67 1 0 Λ Α7 ----- ^ ___ Β7, invention Description

------- VSUB2 1 (Rate) ------ VSUBS VXN0R VX0R Undefined VX0RALL --------- ^-(Please read the precautions on the back before icing " this page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Chapter 2 DSP Core (C 0 RE) This chapter describes the specifications of the DSP core as known by the hardware and software designers. 2.1 Overview The DSP core is the basic building block of the MCP and is only more expensive than all calculations. It contains: • a 32-bit AR Μ 7 it ISCCPU, K 4 Q Μ Η z execution, and is used for general data processing such as real-time OS, interrupt and exception handling, round-in / out-component management, etc. . • One-time XI processor, executed at 80MHz. It is used for applications such as male and female cosine transformation, FIR chirp, convolution, and Vision-90. This paper standard applies to China National Standard (CNS) A4 this grid (210X29 ? Mm} Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 4 3 1 〇 Α α7 Β7 _____ V. Description of the invention (+ $) Digital signal processing such as mobile estimation, etc. The processor is designed by ARM7. Started, and can be parallel to ARK7 operation and through special control instructions to synchronize with ARM7. ~ ~ High-speed memory memory subsystem 'M8QMHZ execution, and contains 1KB instructions and 1KB data for ARM7 high-speed slow memory of billion Zhao, 1K.B instruction and 4KB data cache for vector processor, K and 16KB shared instruction & asset cache ROM shared by ARM 7 and one of the processors. Used for The high-speed data memory of the vector processor can be controlled by hardware or software. This high-speed memory system uses the 32-bit data stream K interface to ARM7, and the 128-bit data stream Row M interface to Xiang Dong processor. • One 3 2-bit 40MΗZ input & output block (I0BUS), its interface to different internal peripherals such as bit stream processor, interrupt controller, timer and UART. One 64-bit 80MHz fast input / round Out of Panbus (FBUS), its interface to the logic area of PCI Panbus controller, memory controller, DHA controller and customer ASIC. A block diagram of the DSP core is shown in the tenth figure. 2.2 ARH7 RISC CPU 2.2.1 Overview The ARM7 RISC CPU is a general-purpose 32-bit KISC processor core. Its standard is described by a standard coprocessor interface. 9 1---------- ^ ------ ΐτ ------ ^. CPlease read the notes on the back before 13 ^ this 萸) This paper size applies the Chinese National Standard (CMS) A4 specification (210 X 297 mm) Ministry of Economic Affairs Printed by the Central Bureau of Specimen Shellfish Consumer Cooperatives, 4 3 67 1 〇, at _ Β7 ____ V. Description of the invention (1) Surface to vector processor, and most of the non-computation-intensive functions in MCP are processed by M, Such as the real-time OS, U0 components interrupt the processor, and communication with the host CPU. The features of ARM 7 CPU are: • Completely static operation • Ideal for power sensitive applications • Low power consumption: 0.6 bA / MHz e 3V manufacturing. • High performance: 25MIPS e4flMHz (40 MIPS peak 3V * Large and small Endian operation mode) • Fast interrupt response for real-time applications (22 clock cycles at 4UMHZ). • Simple and powerful instruction set with very tight layout , Approximately 6mia2. 2.2.2 1 register ARM1 has a total of 37 registers, which includes 31 general purpose registers and 6 status registers. At any time, it has 16 general purpose registers and one Or two state registers can be seen by programmers. In all user modes: User), Supervisor, IRQ, FIQ, Abort and Undefined. Both R0 and H15 are directly accessible. All registers except R15 are universal and can be used to store data or address values. The register 15 stores the program counter (PC, PrograB C u n t e r). The current program register (C P S R, Cu r r n t P r o g r a a Status Register) contains these ALU flags and current chess bits. -9 2-This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297mm). I ------------ Install -------- Order ------ 朿 (Please read first Note on the back, please fill in this again)) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives 4 3 6/1 〇 』7 B7 V. Description of the invention 〇 3) R14 is a sub-routine link register • and Receive a copy of R15 when executing a Branch and Link instruction. It can be used as a general purpose register at all other times. List 12 Universal Register and Program Counter User FIQ Supervisor IRQ Undefined Horizontal Mode Mode Break Mode Mode R0 R0 RO RO RO RO R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 E3 R3 E4 R4 R4 R4 R4 R4 R5 E5 R5 R5 E5 R5 & 6 R8 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 E8 _ _fiq RS R8 R8 R8 R9 R9 R9 _ _fiq E9 R9 R9 R9 R10 R10, • fiqIO RIO RIO R11 R11. Rll Rll Rll Rll R12 R12- _fiq R12 R12 R12 E12 R13 R13_ .fiq R13_ _abt R13 one irq R13 one irq R13_ ”und R14 R14_ fiq R14- .abt R14_irq R14_irq R14_” und E15 (15 PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) -93- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 4 3 671 ο A7 V. Description of the invention ... ) Listing 13 Program status register user FIQ Supervisor exception IRQ undefined mode Horizontal mode Broken mode Horizontal mode CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR.svc SPSR.abt SPSR_irq SPSR_und 2.2.3 Basic constant) ( Please read the back first Notes dome reloading the page) Ministry of Economic Affairs Bureau of Standards employees consumer cooperatives printed abnormality occurs in the command processing means abnormal condition of the course, which will be made to control the flow of change. As shown below, there are seven types of ARM7 exceptions from higher priority to lower silly order; reset (highest priority) exception interrupt (data) FIQ IRQ exception interrupt (pre-fetch) undefined instruction Traps, software interrupts (lowest priority) ° List 1 4 Exception Vector List Address Exception Entry Mode 0 0 0 0 0 0 0 0 Reset Supervisor 0 0 0 0 0 0 0 4 Undefined instruction trap not Definition 0 0 0 0 0 0 0 8 Software Interruption Supervisor-94- This paper size is applicable to China National Standard for Ladder Standards (CNS) A4 "Grid (2 丨 0X297 mm). system

43671〇 V. Description of the invention 0000 oooc 0000 0010 0000 0014 0000 0018 0 0 0 0 0 0 1 C A7 B7

Exception interrupt (pre-fetch) Exception interrupt (data) IR7 FIQ reserved by ARM7

Abnormal interrupt IRQ FIQ 2. 2. 4. All ARM7 instructions are executed conditionally, which means that these instructions are determined by the values of the N, Z, C, and V flags in the CPSR register. Happened or not. ARM7 instructions can be divided into several categories: • branches and branches with connections (B, BL) • data processing (AND, EOR, SUB, RSB 'ADD, ADC, SBC, RSC, TST, TEQ ^ CMP' CMN, ORR, MOV 'BIC' MVN) • PSR transmission (MRS, MSR) • Multiplication and multiplication accumulation (MtJL, MLA) • Single data transmission (LDR, STR) • Block data transmission (LDM, STM) * Single data Swap (SWP) • Software Interrupt (SWI) • Coprocessor Data Operation (CDP) (this is a group of instructions) • Coprocessor Data Fusing (LDC, STC) * Coprocessor Temporary Register Transfer (HRC) 、 MCR) -95 This paper size is universal Chinese national standard (CNS > A4 size (2 丨 0X297mm) (Please read the precautions on the back before filling in this page) 43 67 1 ο Α7 _____ Β7 5. Description of the invention ( 2) ^ Processor 2 * 3 direction processor is a powerful digital signal processor * which uses military-instruction multiple data (SIMD) architecture to get the highest performance. It contains a pipeline of RISC devices. Its operation The highest performance is achieved by paralleling the materials in the multi-element. These multiple data elements It is encapsulated in a 576-bit vector, which can be calculated at the following rates: • 32 8 / 9-bit fixed-point arithmetic operations per 12.5ns-period • 16 16-bit fixed-point arithmetic operations per 12.5ns-period * or • 8 32-bit fixed-point or floating-point arithmetic operations per 12.5ns-period 2-3.2 execution "j pipe 璁 f P; D ρ π nas) As shown in the eleventh cycle, the vector processor uses a 6-level pipeline to Used for instruction execution. Printed by the Central Laboratories of the Ministry of Economic Affairs and Consumer Cooperatives (please read the precautions on the back before filling out this page). Most 32-bit scalar operations are pipelined at the rate of one instruction per cycle. • Most of the 576-bit vector operations are pipelined at the rate of one instruction every 2 cycles. All Loads & Stores are overlapped K arithmetic operations, and are individually loaded &; Save hardware and execute independently. In order to balance design complexity and performance, the vector processor can issue and execute out-of-order instructions' It borrows hard limbs from each other_ Resource and data dependency check. This feature can greatly change the nature , Especially during high-speed buffer memory misses due to loading and storage of data. -96- This paper size applies to China National Standard (CNS) A4 (210X297 mm). "436 ^^ 0 at B7" printed by the Industrial and Commercial Cooperatives V. Description of the Invention (A · ^) 2.3.3 The hardware processor gg broadcast vector processor contains four main functional blocks, as shown in Figure 12: • Instruction retrieval unit (IFU) • Instruction decoder & issuer • Instruction execution data path • Load & library storage unit (LSU) This instruction retrieval unit is responsible for fetching instructions in advance using M and processing such as branches (Branch) and jump to the sub-routine (J u β ρ Τ 〇 〇 〇 〇 〇 tine) control flow instructions. The IFU includes a 16-entry queue for the pre-fetch instruction of the current execution flow, and an 8-entry queue for the pre-fetch instruction for the branch target flow. The IFU can receive 8 instructions from the instruction high-speed memory at each cycle. The instruction decoder & issuer is responsible for decoding and ordering all your instructions. The decoder can process ^ instructions at each cycle and always follow the order of instruction arrival; although, the issuer can sort most of the out-of-order instructions, which depends on the execution source and operand (operand ) Data availability. Through different 288-bit data paths (Figure 3), the vector processor can achieve many of its performance. These paths can be executed at M12.5 ns / cycle, and include: • Four-port register file, which Supports 2 reads and 2 writes per cycle. -97- (Please read the precautions on the back before filling this page} This paper size applies to Chinese National Standard (CNS) Α4 size (210X297 mm) 4 3 A7 B7 、 Explanation of the invention Uq *>. Eight 32X32 parallel multipliers, which can generate eight 32-bit multiplications (in integer or floating-point format), or sixteen 16-bit multiplications, or thirty-two at every 12.5ns. 8-bit multiplication. • Eight 36-bit ALUs, which can produce eight 32-bit ALU embeddings (in integer or floating-point format) every 12.5ns, or sixteen 16-bit ALU operations, or thirty Two 8-bit ALU operations. The loading & storage system is designed as the interface between the high-speed data and the high-speed data storage system, which is transparent and unique. As shown in the fourteenth figure, these buses are all 288 bits wide. 2.3.4 Interrupts The vector processor can only recognize two special cases: • CPINT (Coprocessor Interrupt) instruction, such as by the ARM7 program Executed. • Hard Stack Stack Overflow * as if multiple & embeds were executed by a vector processor program. A result of the “jump to sub-routine” instruction. For details on how the vector processor handles these two unique cases, please refer to the documentation of the vector processor architecture. All other interrupts and exceptions generated by the MCP are The system is only handled by ARM7. 2.4 High-speed Broadcasting and Gradual Recording System "Article System 2.4.1 Makeup Cache Control Unit (ecu, Cache Control Unit) The interface to the ARM7 core, vector execution unit (LSU, IFU) 、 Memory plant -98- (Please read the precautions on the back before filling in the tiles) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 67 1 〇 Α7 ___ Β7 ___ V. Description of the invention 〇4- Ming) (HCU, PCI, DMA 'CODEC) and 10 components (BP, UART, timer, interrupt controller) CCU interface to one frame rate (80MHz) F bus and a low speed (20MHz) 10? Grip bus. In fact, CCU has become a central data transfer unit between all internal CPU core units and peripheral 10 components. For a better understanding of the CCP of the MSP chip, please refer to the block diagram of the MSP-1E system specification. In order to support a very high-performance high-speed buffer register system, ecu design has used a transaction-based protocol (pro tocol) K to support all fetching and writing operations. Any military unit that needs access to memory can place this request in the CCU control unit. The arbiter in the control army can respond to a request based on a fixed priority and send a transaction ID (transaction_id) to the requester. The requester should keep this transaction identification brick to identify the information returned when the spring material actually arrives. When the CCU control is processing a request from a unit (if high-speed memory is lost, it will take multiple cycles) * A new request from another unit can be a different transaction in the next cycle Identification code. In this way, the processing request will not block any subsequent requests from other units, and can achieve high performance. Currently, the CCU can simultaneously accept and promise a grab request and a write request in a cycle. The interface element * to (F bus) is composed of a four-table address queue and a one-table write-back latch. The best is that it can support a refill (refill) request from the ARM instruction high-speed register memory, and _ processing from the VEC instruction cache -99- --- ------ ^ ------ 1T ------ ^ {Please read the notes on the back before filling out this page) This paper size is applicable to China National Standard (CNS) Α4 specification (210X297 Millimeter) Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4 3 67 1 〇 A7 ----- —_ Β7__ V. Modification (read) request of the invention description M-Ιοο), one from VEC data high-speed Write request from the rush memory, write request from the VEC data cache, and a write back from the VEC data cache due to improper high speed flush memory circuits ( write_back) request. The high-speed flush memory itself is also optimized for high performance. The HSP high-speed title memory system includes on-chip cache memory SRAM and high-speed cache memory ROM. The high-speed cache memory SRAM is further divided into four different libraries to avoid data thrashing between the ARM CPU and the vector core, or between instructions and data. The high-speed buffer memory RGM provides a high-speed and high-density storage area for one of the ARM7 and vector cores. Although the tag cannot be changed for the cache memory 80H, the effective bits can be disabled, so the data can be sent back from the external memory. In short, the cache memory on the chip contains the following blocks: • A 1KB direct-mapped instruction high-speed memory, and a 1KB direct-mapped write-back data cache, which has 32 bits to ARM7 Metadata bus interface. • A 1KB direct-mapped instruction cache with a 256-bit bus interface for vector instruction fetch units. • A 4KB direct mapping write-back data high-speed memory, with a 256-bit bus interface to the vector execution unit. The data cache memory is dual-port: its K80HHZ can provide 256-bits of fetched data per cycle. • It can support 256-bits of written data. -100- This paper applies Chinese National Standard (CNS) A4. Specifications (210x297 mm) '--------- install -------- order ------ thriller (please read the precautions on the back before continuing to write this page) 4 3 67 1 Ο α7 ---- 1 ___ ΒΤ ____ 5. Description of the invention Q-lol) 0 _ 4KB of VEC high-speed cache memory hip, which can be constructed like the operation of scratch-pad under software control. • A shared integrated instruction & data RQM high-speed punch memory for ARM 7 and vector processors. The interface to AMR7 passes through the same 32-bit bus as its instruction high-speed memory, and the interface to the vector processor passes through the same 256-bit bus as its instruction high-speed memory. • Fifth:-For ARM7's fetch / write port ~ for vector instructions to find military yuan's fetch port-for vector manned / storage unit fetch / write-for vector IJ0 confluence Fetching / Writing Ports-Fetching / Writing Ports for F-bus • For ARM7 CPU instruction high-speed 绶 ® memory 32X 256-bit SRAK (~ 1KB) Central Ministry of Economic Affairs — Industrial and Consumer Cooperative Cooperatives (please read and read the notes on the back and fill in this education) • 3 2 X 2 5 6-bit SRAi ((~ 1KB) for ARK7 CPU data cache) • For processing to Dong 128 X 2 56-bit SRAM (~ 4KB) for device data cache memory 32X256-bit SRAM (~ 1KB) for vector processor instruction high-speed memory

512X 256-bit ROM for data & instruction high-buffer memory -10 1- i ▲ Zhang Newcom General China National Standard (CNS) A4 threat (210X297 mm) Employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the cooperative 4 3 67 1 〇a? _____ ^ _ Β7__V. Description of the invention (/ -ΙοΖ) (~ 16KB) Control of vector data high-speed flush memory can be achieved under hardware control or software control. 2.4.2 Gao Xinxin's preparation system details The fifteenth figure is a block diagram of one of the MSP high-speed memory systems, which includes the following blocks * · Instruction data 髙 Cache memory UDC, Instruction Data Cache), high-speed buffer memory RMO, CCU_ DATA_DP, CCU_ADR_DP, CCU_CTL, and CCU_SM. Each sub-block will be described in more detail later. 2.4.2.2 LDJL instruction and data High-speed memory (IDC · Refer to the 16th figure) is the SRAM memory on the chip * which uses M to make instructions and data cache memory access. There are four memory libraries in one array: ARM_IC (1KB)-ARM_DC (1KB) 'VEC_IC (1KB), and VEC_DC (4KB). It can accept one read request and one writer request in any cycle. Tag RAM has two yield ports. The read port address and write port address can be compared with the internal high-speed buffer memory used for hit or miss conditions. The data RAM has only one capture port, which is the read port address for access. Both tag RAM and data RAM can also be written using a different set of writer addresses. Yes K, there must be four sets of cache memory library selection signals and three sister line index K to access the cache memory array. I DC has the following characteristics: • K write-back policy is directly mapped. -1 02- The scale of this paper is applicable to China National Standard (CNS) A4 size (210x297 male thin) '' (Please read the precautions on the back before filling in this purchase) 4367 1 Ο λ ^ 436/10 Λ Α7 ______ Β7__ 5. Invention Explanation U + 3) • The high-speed balance memory size is 64B, but the data width is only 32B, which is also the vector data size of the MSP chip. • Each media path has two significant bits, one for the high vector and the other for the low vector. In addition, the data high-speed M-pulse memory has * two dirty bits, one for each vector. • The mark size is 22 bits (address bits 10 to 31) for ARM_IC, ARM_DC, and VEC_IC; and has 20 bits (address bits 12 to 31) for VEC_DC. • The line index bit is 5 bits (address bits 5 to 9) for ARM_IC, ARM_DC and VEC_IC; 7 bits for VEC_DC system (address bits 5 to 11). • VEC_DC (4KB) can be reconstituted as if the pad was erased under soft palate control. • The V_CLEAR signal is used to reset the effective bits of the high-speed bus line at the same time. After K, this signal will only selectively reset individual libraries. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Notes on the back of the poem before reading this page, and then fill out this page) 2.4.2.3 The audio material is turned off Refer to the seventeenth figure. 2.4.2.4 Copy site block The data path used for the address processing pipeline is shown in Figure 18. 2.4.3 and 2.4.3.1 audio-type glycosides are shown in Listing 15. · The CCU handles the differences from various request units. -103- The paper size is in accordance with China National Standards (CNS) A4 specifications (21 × 297 mm). ^ 3671〇Α7 Β7 V. Data type of the description of the invention (/ Η #). List of 15 C C U operations

ARM Bytes Data Type

c CU operation: Take advantage of the employee cooperation of the Card Standards Bureau of the Ministry of Economic Affairs · Printed ARM bitcoin, word group 1 Enter the size of the paper This paper is applicable to the China National Standard (CNS) A4 specification (2 丨 0X297 male > bit The tuple address is in the range of the bit sister | The block address is in the range of the word, there is ui_cache and ud_cache between Αβ Μ and ID C 〇 Any error u_cache will always bring back 32B (location) data K and then full u_cache. IDC miss will cause IDC to be refilled by external SDRM. Two write back (double_WB) operations are possible if the two vector systems are not correct. Only 32B data is brought back to M and refilled (single fill) ARM high-speed memory address location is the same as reading. Any hit to ud cache (please read the precautions on the back before filling this page) Printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 43 67 1 Ο λ The description of the invention (A · ^) by the ARM writer will invalidate Με ache. Before the writer writes to IDC, the appropriate byte of K will enable the announcement, and the data will be able to be positioned properly. Memory write miss, write data will Stored in wr ^ data.bufl. If both vectors are not correct, DouU-'WB operation system is possible. After 3 2 B science department is retrieved from the memory, CCU will start writing to IDC and mark This vector is inappropriate. For writes that are removed from the high-speed memory, the tribute will be stored in mem_wr — fat (64B). The request will be transmitted to one of these address queue locations. Because the data system If it is less than 8B, the part of the F bus write protocol will be used. (Please read the notes on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification {2 丨 OX 297 mm) -105 -5. Description of the invention (A ^) IFU reads the most IFU address system. It is K-word positioning. Each request will bring back 32B (location) data, either by I DC or by external SDRAH. LSU scalar (position tuple, half-word, word) 10 (Please read the notes on the back before writing this page) Printed by the Consumer Cooperative of the Central Standard Bureau of the Ministry of Economic Affairs 2.4.3.2 ARM and ARM7 CPU The core is a half frequency UO MHz of the M MSP chip, and the CCU is a full frequency K 3MHz. Synchronization between these two clocks is important in the design. As a general rule, the clock generator unit will only switch MCLK on the rising edge of CLK1. In addition, the general reset signal * connected to ΑΜΜ7 will be de-asserted only when both CLK1 and MCLK are low. In this way, the second unit will be properly synchronized. Although the ARM7 only has one round-trip bus (ARM_DATA < 31: 0 >) K for instructions and data | The rough board (rasp) chip is equipped with a dedicated instruction High-speed Yuan Chong billion billion URM_IC, 1KB) and data髙 Speed Buffer Memory-1 0 6- This paper is suitable for medium and poor countries (CNS) A4 size (210x297mm) Printed by the consumer cooperation department of the Central Standards Bureau of the Ministry of Economic Affairs 43671 05. Invention Description (/ Μ, UKM_DC, 1KB). By borrowing ARM_NOPC, the CCU can distinguish between these two requests. To further improve performance, the CCU system adds a micro-instruction high-speed cache memory (UI-CACHE, 32B) and a micro-data high-speed cache memory (UD-CACHE, 32B). Between memory and ARH 7 core. These high-speed Yuanchong memories contain 8 blocks, each block has a sequence of codes and resources. These micro high-speed memory chips include their own tags, tag comparators, and valid bits. During the system reset, these valid bits are cleared. The actions of these ARM 7 micro-speed high-speed registers are similar to those of a pre-fetcher, rather than a true high-speed register of billions. During ARM 7 capture, the address (ARH_A < 31: 0 >) is always compared to the standard. A hit will return the instruction or data via ARM_DA1: A < 31: Q >. A micro high-speed buffer memory miss will send a request to the CCU * which is accompanied by the address, data type, and other control information. The ecu arbiter series will respond to requests from all units, and K will make a fetch request. At present, ARM7 has the highest priority K over other blocks and is approved. This is due to the fact that ARM made the request very rare, unless its micro-cache has a miss. However, ecu can have internal save cycles, and K is used for multiple cycle requests or address queue full. During this period, no external requests will be granted. If the address hits UD_TAG, writing from ARM7 will always invalidate UD_CACHE. There is no plan to design the UD „CACHE as a write-through or write-back high-speed flash memory. By -1 0 7-This paper standard is common in China. Standard (CNS) M specification (210x297 male |) Packing — t Please read the notes on the back before filling in this education) Order, 涑 _ Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 67 1 〇 ^ at Β7 五The invention explains that the UD_CACHE compulsory invalidation of the writer's hit is to maintain the consistency of data between ARM_DC and UD_CACHE. When making a grab or writer request to ARM_IC or ARM_DC, the CCU controls arm_nwait. Generally speaking, the CCU Arm_nwait will not be saved during the writer. Once the writer agrees to the request without CCU_WRITE_ H0LD2, ARM7 only moves the data in ARM_DATA < 31: 0 > in the following cycle. The CCU has a fake internal write The buffer M stores the data. The ARM can continue to execute the instructions. However, the CCU always saves ann_nwait—a cycle * even if the data exists in the main high-speed memory bank. If the read request misses the main high-speed memory bank | Will save more cycles until resources The data is returned from the main cache memory in vitro. As shown in Figure 19, the ARM_CCU interface state mechanism describes how CCII controls the condition of arffi_nwait. In Figure 19: START: The starting state of the state mechanism, if No request, or read data is returned, or write request without saving. HOLD (Save) ... The CCU allows ARM7 to request K to read or write. However, the K save signal cancels the promise. TAG: CCU Check. MISS (Missing): There is an error in the read address, and the CCU sends a refill request to the outside of the DRAM. DATA (Information): The read data is returned, and the CCU drives it to the micro material. Memory. 2.4.3.3 F 陏 涪 — 介 -108- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) Central Standard of the Ministry of Economic Affairs The production of “43 6 " Π Ο, a? _Β7_ by the local shellfish consumer cooperation. V. The description of the invention (the CCU_FBUS interface state mechanism (F_SM) is shown in the twentieth chart. In the twentieth chart: IDLE (Set): REQ status: Make a _fetch or write request to the F bus arbiter GRT1: Promise size is greater than 8B GRT2: Promise size is greater than 16B GRT3: Promise size is greater than 24B GRT4: Drive data is used for the last cycle. The data receiver status mechanism (D_SM) is shown in Figure 21. In the twenty-first figure: IDLE: Idle state ONE: Receive the first 8B from Fdata < 63: 0 > TWO: Receive the second 8B from Fdata < 63: 0 > THREE: Receive from Fdata < 63: 0 > 2 the third 8B FOUR: receive the fourth 8B REFUU from Fdata < 63: 0 > refill): refill IDC before returning the data to the requester ° RDY: prepare to return the data to Solicitor. 2.4.4 Please take it with others. The mechanism of reading and writing the bark state is shown in the twenty-second figure. 2.4,4.1 The IDC (instruction and data high-speed buffer memory) read in the MSP is operated at -109- (Please read the precautions on the back before filling this page) The paper scale is applicable to the Chinese national standard ( CNS) A4 is now (210X297 mm) 436710, A7 ______B7__ V. Description of the invention (/ MI〇) Level 3 pipeline cycle: request cycle, standard cycle, and data cycle. In the case of high-speed title memory hits, IDC is able to send back instructions or data every cycle. Μϋ (cache controller unit) performs arbitration among ARM 7, vector processor unit, F bus, and I 0 bus for high-speed memory SRAM access. The CCU monitors the sleep bus requests from these four main controllers and promises the bus to the winner with a specific ID number. The CCU also generates a high-speed memory address bus, and the read / write control signal M accesses the high-speed buffer memory and performs a comparison comparison. 0 If there is a high-speed balance memory hit, it will be judged optimally. The bus master will be able to access the cache memory for fetch / write operations. If there is a high speed memory miss * CCU will be used to make a request to the next bus master without waiting for the missed data to be returned from the main memory. Therefore, the bus master controller with a high-speed balance memory must retain the ID number. Then, if the requested information is in the high-speed buffer memory, the CCU will send a promise signal to the missing data with the same ID number for printing by the Ministry of Economic Affairs Central Standardization Bureau Off-line Consumers Cooperatives (please listen first (Read the notes on the back and fill out this page). This bus master can accept the data, or ignore it 〇 When there is a cache memory failure, a line search will be performed to get the data from the master memory. The circuit size is defined as 64-bit bytes *. Therefore, the CCU will perform memory access (each 64-bit) of the Hachiran Mine, and M will obtain data from the main memory to the high-speed cache memory. -110- This paper size is applicable to China National Standard (CNS) A4 specification (210 × 297 mm) 43 67 10 A7 Employees ’cooperation with the Central Bureau of Standards of the Ministry of Economic Affairs Du Yinzhuang B7 V. Description of the invention (, ...) • Request cycle: The CCU will accept requests from various elements (ARK, IFU, LSU, 10) in CLK1. The requester will announce the request signal (lsu_req) and the read / write signal (lsu_rw) at the beginning of CLK1. Before the end of CKL1, the CCU will agree to one of these read requests by driving out ccu_grant_id [9: Q] M. If ccu „grant_id [9: 6] matches the requester's unit_ud, the request is granted. The requester should latch ccu_grant_id [5: 0] because it is the transaction identification (id) associated with the request. If If the request is accepted, the requester should drive the address (isu_adr [31: 0]) and other control information to the CCU, such as cache_off operation (lsu_ccu_off) and the type of data in CLK2 (lsu_vec_type [l: Q], lsu_data_type [2: 0]) ° If ccu_rd_hold_2 was not declared before the end of CLK2, the request was completely obtained by CCU, and the requested data will be returned later. However, if ccu_i * d_hold_2 is announced, the requester should keep Drive this address and control information | If the answer request in CLK1 is taken. In the next cycle, because all previous grant _id information is still valid. • It is not necessary to make the same read request. Ccu_rd_hold_2 It will remain unchanged in CLK1 until it is de-announced by the CCU in CLK2. Ccu_rd_hold2 is a timing critical signal that informs the requestor with M. The CCU is busy processing other in the current cycle Matter and answered The request cannot be processed yet. • Standard cycle: -111- (Please read the precautions on the back before filling this page} This paper size applies to Chinese national standards (CNS > A4 size (210X297 mm) A7 43671〇 β 5. Description of the Invention (Απ) If the request is accepted and not cancelled later in the request period *

(Please read the precautions on the back before filling in this page. J will enter the stage of chain comparison of this fast memory access. CCU will use the address (lsu-adr [ll: 5]) and the program temple selection Signal (requester) to make a route selection for tag capture. The shovel hit signal (ccu_lsu_hit_2) will be known until the end of CLK2. For hits, this data will be sent back in the next cycle. Read The port flag will be sent out no matter what, and it is latched by CLK2. The address queue status is also obtained in this cycle. The tag miss and an almost_f \ ill_addiiess_tiueue will announce the ccu_rd_hold_2 signal. The CCU status mechanism will not process any A new capture request, but the tag comparison that has been interrupted abnormally will be retried. Since each high-speed memory hip line (64B) contains two vectors, the effective bit of the access vector should be valid, and M gets the signature Hit. For double vector (64B) data reading, the second valid bit must be valid and M gets the tag hit. The cc_off operation will always force a tag to be missed, and the request will be sent out of the address queue • Data cycle: Printed by the Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs during this cycle, CC II sends the data back to the requester. The data will be set at 16B low driven by CLK1 and 16B high driven by CLK2. ccu_d〇ut [127: 0]. For 64B data requests, an extra cycle is used to complete the transfer. CCU will always drive ccu_data_id [9: 0] half a cycle earlier (CLK2) • To inform the requester that the data will be It will be sent back after CLK1. The requester should always -1 1 2-This paper size is in accordance with China National Standard (CNS) A4 (210 × 2Ϊ »7mm) '" ι · 4 3 67 1 〇 Λ Α7 _____ Β7_ 5 The invention description compares ccu_data_id [9: 〇] to properly return the data. In addition, the label hit is also used as an indication of the returned data. If there is a label error in the label cycle and the address queue is not full 'ecu will send the missed address, identification (id) information, and other control information to the four entry address queues of CLK1, and M will start to find high-buffered memory circuits. At present, each The address queue contains about 69 bits of information. At CLK2, The memory address latch will be loaded, so the F bus request can be made in the next CLK1. 2.4.4.2 The writing operation of the wide-person operation in IDC also operates in the three-stage pipeline cycle: request cycle, simulation cycle , And data write cycle. In the case of a write address hit, IDC can write human data to the cache data array in each cycle. • Request cycle: Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs (Read the notes on the back of the poem before filling this page.) CCU will receive write requests from various units (ARM, LSU, 10) of CLK1. The requester will announce the request signal (lsu_req), read / write signal (lsu_rw), and vector type (lsu_vec_type [l: 〇]) at the beginning of CLK1. Before the end of CLK1, the CCU will agree to one of these writer requests. By directly announcing a promise signal (ccu_lsu_wr_grant) to the request, it can be agreed to by the writers in different units. Since there is no data to be sent, the request unit does not need to receive the transaction ID (transact ion_id) from CCU. CLK2, the requester should provide the address Usu_adr [31: 0]), cc „〇ff 信号 -11 3- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 4 3 67 1 〇 A7 ___ '' · ____ Β7 ___ V. Description of the invention (lsu_ccu_〇ff), and data type (lsu_data_type [2: 0 ]). As in the case of grabbing, the CCU may declare ccu_wr_hold_2 near the end of CLK 2. M notifies the requester that although it has agreed, it cannot be processed in the previous cycle. The requester should maintain the drive address, CC_ 〇if signal, and data type information until the announcement of ccu_wr_hold_2 has been released. Then in the next cycle, the requester writes data to ccu_dout [127: 0]. • Signing cycle: 系 The request was approved and not in The request cycle is then canceled, and it will enter the standard chain comparison phase of the cache memory access. This is the comparison of the written port address and address. The CCU will use the address (lsu_adr [ll: 5]) and the program Bank selection signal (requester) · M work The line selection for high-speed punching and recording of billions of bodies. The signing hit signal (ccu_lsu_hit_2) will not be known until the end of CLK2. Ccu_off will always force a tag to be missed, and the written data will be placed for external writing The F bus is imported. It is printed by the shellfish consumer cooperation department of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this education). The requester should start at 16B lower than CLK1 and 16B higher than CLK2. Drive data to ccu_din [143: 0]. For S4B data transfer, the requester will drive the data in an extra cycle. It should be noted that * CCU has an internal write data latch to save this data. Regardless of this The write system hits the cache memory (actually writes data to the high-speed memory with M in one or two cycles) or misses the cache memory (possibly κ writes data to multiple cycles), 謓Applicants should now regard this writing as completed. • Data writing cycle: -1 14- Chinese paper standard speed (CNS) Α4 specification (210 × 297 mm) 4367 1 〇. Α7 Β7 _ 5 ,hair Explanation (/ 4) For the case where the high-speed buffer memory hits, ecu actually writes data to the cache memory during this cycle. If there is a jitter miss during the label cycle, ecu will be different depending on the data type If the data type is 32B and the line is clean (both vectors are appropriate), the CCU will only write the new label and new data to the existing line repeatedly. It will also identify that the vector being accessed is valid and dirty, and leave another vector on the same line as invalid. If the data type is less than 32B, this becomes part of the data writing. This part of the data will be stored in a temporary register. The CCU will find the missing half line (32B) from the memory and load it back to the Su Suyuan Chong memory. Then, this part of the data will be written into the high-speed buffer memory circuit with the appropriate byte enable signal. Printed by a member of the Central Standards Bureau of the Ministry of Economic Affairs and a Consumer Cooperative (please read the precautions on the back before filling this page). For all write errors of a dirty high-speed Yuan Chongji billion circuit, the CCU will first copy the improper circuit . As the improper data is not yet available, ecu will keep the declaration in the promise logic so that no new snatch or writer request will be promised. An internal fetch will then be initiated, using the improper line address to find improper cache line data. Finally, the writeback address and data will be sent to memory. 2.4.5 Programming Method This high-speed memory system is completely controlled in hardware through the use of load & store instructions, so it does not need any register to show any soft questions. 2.4.6 ΤΠ [饵 Rfll · (份 til · 榇 忒) This format is as shown in the twenty-third figure. —1 1 5- This paper size applies to China National Standards (CNS) Α4 size (210 X 297 public) } 43 67 1 〇a A 7 ____ Β7 ____ 5. Description of the invention (Mount A-I) Chapter III 10 Bus description This chapter describes the specifications of the 10 bus as known to the hardware designer. 3.1 About the 10 bus system Designed for "low-speed" standard peripherals: the component 'which is used by the system. This bus will serve as a buffer between the MSP cache control unit (CCU), bit stream processor (BSP), M and The main interface between all other 10 peripherals such as timer / interrupt controller and UART. The format of this bus is very similar to Intel's 10 calendar bus. It has a bus arbiter Controller control series • It continuously monitors the bus M for requests. • Borrows a circular signature book (not showing the signer sequence) (round-robin) framework M to generate appropriate request consents. Potential bus master control The device should always announce the bus request and replace the existing bus Waiting for the bus to be announced. The bus master should always drive the address and control the media path used during the cycle according to the agreement. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the notes on the back first) Fill out this page again} The 10 bus pseudo-synchronous bus that executes on the constitution of 4βΜΗZ. After the request is sampled, all promises on the MSP 10 bus occur in one cycle. This bus can be in four cycles ( Four pulses) processing data transmission of up to 16 bytes. This is achieved by borrowing two size bits. The two size bits indicate to the bus arbiter that the transmission requested by the bus master Dimensions. The industrial bus has a 32-bit address and data multiplexer. The address always appears before the data appears. The receiving component uses the IOB_ALF (address latch enable) signal to latch the address. Even The 8-bit device is embedded on the busbar * -116- The paper scale is applicable to the Chinese National Standard (CNS) ΑΊΜ (210 X 297 mm) 43 67 1 0 av f Β7 V. Description of the invention U "?) All Remittance ^ access will be false Set to 32-bit transmission. M—Generally normal. 8-bit devices will use the lowest 8 bits of the bus [7: 0], while 16-bit devices will use the lowest 16 bits of the bus [15: G ]. If a 16-bit device wants to communicate with an 8-bit device, the correct data should be placed in the lowest 8-bit · M of the bus used for the 8-bit device. The data is found and latched, etc. If in the same period There are multiple requests * Unaccepted requesters should keep their requests until they are approved by the 10 bus arbiter. Each allowed request in this architecture has many "bus access cycles" • Up to 4X3 2-bit transmission (16 bytes). Block transfer should be divided into multiple 32-bit transfers. All bus promises are generated by 10B bus arbiter. However, there is a parallel decoding S series, which constantly monitors the address (when it is valid) and generates an appropriate chip selection (in the next clock cycle) to the destination. The wafer selection will always be valid for only one cycle, and thereafter the address is declared for all read and write requests. Each bus node will have a dedicated chip selection as input. Please refer to the pin description and timing circle. Printed by the Central Bureau of Standards, the Ministry of Economic Affairs, Beigong Consumer Cooperative (please read the notes on the back before filling in this S). After the bus arbiter agrees, the 2-digit size information should be provided by the main controller ( master), and shall be valid for the next two bus cycles. When CS is announced, the selected slave must capture the size information K to determine whether the bus transmission cycle is written or snatched; before starting to notice the new request, the 10-bus deterrent also keeps track. For the transmission size, M determines when the bus is completed. Please note that there is no "GAP" between the data transmitted by the pulse bus (regardless of reading or writing). -117- This paper size applies to the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 (Mm) Printed by the Consumers' Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs 4367 1 〇, Α7 Β7 V. Description of the Invention (λ4) For the transmission of data, a ready signal is used to instruct the requester of the data When is valid and when is the data latched from the beginning. This ready signal is generated by both the bus master and slave. In order to comply with this agreement, all 10 bus nodes must be designed to process one of the requests. 10 Bus interface. This interface should meet the following specifications. Size description 2'bOO Default (Transfer size). Transmission size = 4 bytes (one 32-bit period) 2 'bOl Fu size = 8 bytes (two 32-bit period) 2. bl〇 transmission size = 12 bytes (three 32-bit cycles) 2. bll transmission size = 16 bytes (maximum size of four cycles) 3.2 Footprint description The following is the system 10 confluence Definition of address, asset and control signal, Seen with the bus master. See also Figure 24, which shows the definition of the 10-bus architecture. As mentioned earlier, the 10-bus is a multiplexed address / data bus. -1 18- This paper Standards apply to Chinese national standards (CNS> A4 now (2 丨 OX297 mm) ^-(Please read the notes on the back before filling this page) Ding Dong 4 3 67 1 0 A1 Λ Β7 V. Description of the invention (≫ || ί?) »Xxx" is a three-pronged alphabetic code that identifies the requester (ecu, bsp, urt, tan ,, int) with M. The Central Ministry of Economic Affairs, Ministry of Economic Affairs, Employee Consumption Cooperation, DuPont System 10 Bus signal definition 10 Bus signal name Size direction annotation 10 Bus [31:01 32 Bi-directional 32-bit dual quotient and multiplexed address and data bus. IOB_rd-1 1 1 input / low-position action. Main controller output , Output slave input. IOB_wr_l 1 input / low-level action. Master output, output slave input. IOB_ready_l 1 input / low-level enable. Notify the master when the output data is available for grabbing (when in slave mode) Hours.) Main organ Input / slave output. I〇B_CS_xxx_l 1 Input component selection | Low position operation. This -119- --------- install-(Please read the precautions on the back before writing this page) Paper size is applicable to China National Standards (CNS) A4 scale (210X297 mm) A7 43671〇87 V. Description of the invention 夬 Ministry of Economic Affairs, China Standards Bureau, Employee Consumer Cooperative Printing is used to process requests once the address is latched . I0B ^ ale_l 1 Input low action, indicating when the address is fixed. Arbiter output, master / slave input. 10B_req_xxx_1 1 round-out low-level action, requesting control of 10 buses, and M becomes the main controller. IOB_tsize [l: 0] 1 input / output Fu send size = 4/8 11 21 1S bytes. Master output * Slave input. I0B_grant_xxx ^ l 2 Input 10-bus from 10-bus arbiter promise. M allows this request device to become the master of the 10-bus. Low post action. Reset 2 Enter the low position and the system resets. * " 120- (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) d36 Ί A7 B7 V. Description of Invention (aW)

Turn in

3.3 Description of the episode The 10-bus arbitration control unit is shown in the 25th intestine. 3.4 τ η 皤 clamp timing 10 bus read timing (Fu sent size = 1 byte (4 bytes)) is shown in the 26th figure. 10-bus write timing (Fu send size = 1 character (4 bytes)) is shown in the twenty-seventh figure. The 10-bus capture timing (transmission size = 4 bytes (16 bytes)) is shown in the 28th figure. The 10-bus write timing (transmission size = 4 bytes (16 bytes)) is shown in the 29th figure. Chapter 4 Description of the Fast Bus This chapter explains the specifications of the F (Fast) Bus as seen by the hardware designer. Please read the precautions on the back before writing this booklet and order it. The device is connected to the system bus " F bus " via a non-multiplexed address and data bus line * memory controller, PCI, customer ASIC and cache subsystem. There will be a central F-bus arbitration control series, which will monitor the request and borrow some prioritization framework K to generate a promise. Hui-121- The standard of this paper is applicable to Chinese national standard (CNS > A4 specification (2t〇X 297mm)) 5. Description of the invention (/ HR) The main controller (address and data source) of the flow will be-straight Declare the bus request 'and wait for the promise. Normally, if the request made by the bus is not used by another master / slave machine (the promises used are generated in combination), it will be the same An answer occurs during the cycle. Once the master receives the bus answer, the address / data / control line will be sent out in the subsequent cycle. A "data ready" signal will always process the actual data | M instructs the receiver to start The subsequent cycle is latched. To use the maximum bus level, four consecutive requests can be received / sent in a back-to-back pipeline, and a "request FIFO" must be used Handles all four requests. The memory control will have a four (4) deep request FIFO and a two-deep data FIFO. Due to the nature of this agreement, an "AF-FULL" and " DF-FULL "signals, which are the address FIFO full and data respectively. FIFO is full. F bus data width will be 8-byte (64-bit) and 32-bit address. F sink bank will use the bus that promises to count and request size, and will support 8, 16 and 32 Byte data transfer. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative (please read the notes on the back before writing this page). Each F bus unit will have a control unit M request bus. This Recording will vary depending on the application of each unit (memory / PCI / high-speed buffer memory ... etc.). However, the actual bus priority army in each army will be the same, and will Duplicated in all sub-horizontal groups. This unit will act as an intermediary between the external bus master / slave and the internal unit memory. For example, in the case of a memory controller, Once the CAS system terminates the "action", the memory pass controller will announce a time within -12 2- This paper size is used by the Chinese national standard (0 Yang) 8 4 grid (210 father 297 mm) ~~ Ministry of Economic Affairs Consumer Standards of the Central Bureau of Standards Yin Fan ^ 367 1 〇 λ Α7 ___ Β7 V. Explanatory note (Heart | 1 >) Our PS seeks the F-bus rollout arbitration logic via an internal signal indicating that the F-bus is used. In response to this request, the F-bus controller will declare an @Request 至The external system outside the memory controller and waiting for an answer. Once the promise is received, the address / data / control will be sent out by the first entry of the response data FIFO in the memory controller. To the memory controller The system request can be the largest size from 1 byte to 32 bit sisters. For the requested size of more than 32 bit sisters * the resource / requester will borrow the F bus "size" bit M Kai Begin multiple requests. This will be implemented due to the limitation of the SDRAM memory bus (1 or 2 Samsung SDRAM 1M X 16). SDRAM will program the multiples of eight (8) bits to achieve the full 32-bit size required by the rest of the system. For requests with less than 32 bits, all 32 bytes will be found by SDRAM | but only the required number of bytes will be sent to the destination. There will also be a ten (1 (3) -bit requester ID bus, which will be enabled by the M " chip selection "signal. (Same as the address / data cycle) 0 All F bus nodes will Generate a three-bit "destination ID" to F bus arbiter. These three bits will be valid by request * and indicate the destination of the request ° destination ID bits [1: 0] Decoded by entering the requester ID • As follows: Requester ID [9: 6] Source destination IDil: 0]

0 0 0 0 Reserved N / A -123- This paper size is applicable to the Chinese National Standard (CNS) A4 now (210X.297 foot) --------- seed coat ------? Τ ------ 'i (Please read the precautions on the back before writing this page) 436710 A7 B7 V. Invention Description (A Code) 0 0 0 1 ARM7 N / A 0 0 10 FU N / A 0 0 11 LSU N / A 0 100 CCU 0 0 010 1 ASIC 11 0110 HEM 0 1 0111 PCI 10 1 XXX Reserved (Please read the notes on the back before filling out this page) Printed by the Central Laboratories Bureau of the Ministry of Economic Affairs The destination ID bit U) will indicate the read / write request status with K. This will help the F bus arbiter M to distinguish between an address-only request (capture) and an address / asset request (write). Normally, the promise count bit egrCNT [l: G] " indicates the number of F bus cycles of the requester m to bus. For back-to-back requests, these requests will indicate the length of the request to the bus master. F bus will announce the promise based on the two promise count bits. F bus is a separate transaction bus that supports the reads sent. This means that when a requester makes a request for a bus and once agreed, it will drive the address and complete the transaction. Later • The slave / source will borrow the destination ID to send the data back, and send the same request back to the requester. This feature effectively changes the bandwidth of the bus and allows other masters to use the F bus faster. For more details, please refer to the timing diagram. -124- The size of this paper is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs Λ2 Consumer Cooperatives 43 67 1 0 a7 Λ ___ _B7__ 5. Explanation of the invention (/ \ 也) 4 2 The address, data and control signal of the F bus of the system according to Jjj are as follows. As mentioned earlier, the F bus is a non-multi-site address / data bus. "Xxx" is the name of the requester (raem, pci , Asc, ecu). List 16 糸 System F bus signal definition F bus signal name size direction note Fadr [31: 0] 32 32-bit address bus bidirectionally on separate address lines . Fdata [63: 0] 64 64-bit data bus with double changes in both directions. Frd_wr_l 1 Both directions "1" == > Snatch, "〇" == > Write Fxxx_cs_l 1 Enter chip selection, low-level action Fdrdy_1 1 Two-way 125- Data Futu signal, valid for the period before the inter-spring data. Only the paper wave scale applies the Chinese national standard (CNS 丨 Α4 specification (2KJX297 mm) --------- ^ --- --- tr ------ 1. (Please read the precautions on the back first -This page) 6 3 Δ ο 5. Description of the invention (A-Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs prints the low-level action announced by the data source. Freq_ID 10 Two-way request ID, which precedes the data. These signals Has the same timing as Fd_rdy signal bits [9: 6]-θ Requester ID bits-Transaction Η Fxxx_req_I 1 Output source F bus request. Low-level action Fxxx_grCNT 2 Output F bus promise count * It is valid as M request Use K to indicate the number of cycles required for approval F xxx_grant_1 1 Enter the F bus promise from the central arbitration unit, the low-level action Fxxx, did 3 will output the 126- F bus destination ID. This signal is driven by the request * indicates the main F Which CS is generated by the bus arbiter? (Please read the precautions on the back before writing this page.)

、 1T 朿. This paper size applies to Chinese National Standard {CNS) A4 specification (210X 297 mm) 6 c 5. Description of invention (" milk)

Fxxx_did [l: 0} == Destination ID * Fxxx_did [2] == Capture / write status. (G = > Writer, 1 = > Let) Fxxx_af u11 1 Output Address FIFO is full. This signal will be announced when there are (n-1) drawing entries in the FIFO. High-level action Fxxx_dful1 1 Output The data FIFO is full. This signal will be announced when there are (n-1) entries in the FIFO. High position action F.reset ^ l 1 input low position action, synchronous F bus reset F c 1 k 1 input 80 MHZ bus clock Fpr—wr_l 1 input 127- part of the write indicator, the receiver borrows this signal Can be distinguished in the size of each 8-byte byte --------- button clothing — {Please read the precautions on the back first, then the potential home page)

11T 涑, this paper size applies the Chinese National Standard < CNS) A4 specification (2 丨 OX 297 mm) ^ Α7 __ Β7 V. Description of the invention. This signal is used in combination with Freq_size [7: 0]. Freq_size 8 Bi-directional transfer size (< 32-bit, 32-bit, 64-bit, 128-bit) * * Decoding list definition M must be used for RMW ° --------- install — (Please read the notes on the back before writing this page) Figure 30 illustrates the process of requesting the F bus for this memory. Figure 31 illustrates the flow of the memory write request F bus. The third and second diagrams illustrate the flow of the master / slave "non-memory" request F bus. Thirty-three gardens describe the centralized F-bus arbiter controller unit. The thirty-fourth to thirty-sixth diagrams are timing diagrams of the F bus. Figure 34 illustrates the memory bus write request F bus timing. (The 8-byte data transmission system shows that it can be used for 16/32/64/12 8-byte multi-data cycles.) The thirty-fifth figure illustrates the timing of the memory capture request F bus (transmission size = 8-bit (Tuples) ° The third and sixth figures illustrate the back-to-back write request (transfer size = 32 bytes). Chapter 5 PCI Bus This chapter describes the specifications of the logic between the PCI core and the PCI (g 1 ue) logic, which is the interface with the internal F bus. -1 28- This paper scale is applicable to China ’s national standard (匚 奶 ^ 4 size (21〇 father 297 male |) Dingdong Central Bureau of Standards of the Ministry of Economics and Printing Cooperative Print 4 3 6 " Π Q: 436M 〇, A7 ______________B7_____ V. Description of the Invention (/ HM) 5.1 Viewpoint ~ MSP _ IEPCI controller is designed to comply with pc I bus specification revision 2.1. For details, please refer to this standard specification. The PCI unit contains two main parts : The PCI core is connected to the 卩 bus * and embedded. The PCI core is mainly used as an interface with external PCI components running at the PCI bus speed of 3 Μ Η ZO. The F-bus * connection * Samsung F bus at 80M HZ. This connection series interface is between the PCI core and F bus. By using FIFOs at the two ends of these sub-blocks, speed synchronization can be achieved. Samsung's PCI core is also Includes the Virtual Information Segment Flusher (VFB) series, and all VFB registers that need to be interfaced to ARM 7 through the F bus. One unique feature of this PCI unit is * from the host MSP CPU chip and MSP The chip is processed in the host CPU. This will be discussed further in this chapter. 5.1.1 Although the core PCT chart is shown in Figure 37, it is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the note on the back first) Matters will be continued on this page) 5.2 PCI F confirms the flow and complies (Figure 38) This sub-block of the PCI core is interfaced with the MSP internal F bus and the micro-PCI core. Address and data Stored at both ends of the FIFO (that is, from the PCI core and F bus). This sub-block is also a negative cost to synchronize the PCI signal with the F bus clock, and vice versa. The PCI core series can be One F bus master and slave element -129- This paper size is applicable to Chinese National Standard (CNS) A4 (21〇 > < 297mm) 4367 1〇, A7 B7 Employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative. 5. Description of the invention (house-call «most of the access is through the 64-bit F bus to the area of SDRAM memory. For the description of the F bus protocol, please refer to the F bus section Ο PCI F bus control logic also contains virtual information Registers and controls. These registers are designed to be connected to ARM7 via the bus. Please refer to the square chart of this party. 5.3 ΠΠ TV FR «1§ The MSP PCI core is fully compliant with the PCI 2.1 specification. The only addition This is the number of registers, which is used for interruption and software MSP reset. By setting the MSP (bit < 3 >) of the MSP control register to the PCI host 榇 Interrupt request • Software in ARM7 can interrupt the host CPU. This will cause the PCI core editor to interrupt the host CPU by declaring the interrupt pin (INTA #) of the PCI bus. The host CPU will then acknowledge the interrupt, which is recognized by the PCI host interrupt in the MSP control register (bit < 4 >). This will make the interrupt line inactive. The MSP PCI core can also accept an interrupt from the host CPU, which is basically an interrupt to ARM7. Since the PCI specification does not support any interrupt input pins, the MSP interrupt request from the master (bit < 2 >) in the MSP control register is provided by K. The host CPU can set this bit K to indicate an interrupt to ARM7. Once the main interrupt is recognized, ARM 7 will then clear this register. Refer to the block diagram in the 41st painting. Regarding the fortieth circle, there are three registers, which are mapped to the MSP area instead of the PCI space. 0 -1 30- This paper size applies the Chinese National Standard (CNS) A4 specification (210X W7 mm) (please first (Please read the notes on the back and fill in this page). Binding printed by the Central Standards Bureau of the Ministry of Economic Affairs, Printed by the Consumers Cooperative of A7 B7 _ V. Description of Invention (/ η) 1) For details of the actual PCI core, please refer to PCI 2.1 specifications. Chapter 6 Memory Controller 6.1 This chapter describes the specifications of the memory controller as seen by hardware and software designers. 6,2 makeup concept MSP memory controller will have a variety of features and programmable levels of trade-offs between cost and performance. The memory controller will interface between the main system bus " F bus " (which will be implemented at 8GM HZ) and the DRAM chip. To achieve an 80M HZ clock frequency, synchronous MAM will be used for the initial design steps. In the end, the memory subsystem will support standard fast paged DRAM, extended data output (EDO), and synchronous DRAM. Memory library size will be limited to two external libraries, which will be interleaved. The initial synchronous DRAM memory controller will have only the minimum holdover required to operate such DRAM. The "basic" features of the memory controller are as follows: • Samsung ’s synchronous DRAM support • Use of one of the two SDRAM chips (1MX 16) β (1) Cas library before ras ( Cas-Before-ras) Update (CBR) support • Partial write support, which starts the capture-correction-write operation • Internal library interleaving support (via MAUI) ping-pong effect • 8 G Μ Η Z memory and processor bus (1: 1) frequency matching -13 1- The paper size is applicable to China National Standard (CNS) Α4 specification (2! 〇 × 297 mm) II HI H 1 n order. I ~ [ ί '" (Please read the precautions on the back before filling in this page) 4 3 67 Fly 〇4 A7 B7 Printed by the Consumers' Cooperative of the Standards Bureau of the Ministry of Economic Affairs. 5. Inventory Description U-Speaking) Transportable updates Speed • Address and data queue, M better use the system bus • Manual “Dual library pre-charge” support MSP memory controller will have two main components: data controller and address control Device. The data controller will have a queue of fetching and writing data * K to store the fetching data from the DRAM and the writing data from the processor bus. The data controller will also include all RMW series for byte writing. The address controller will generate all control to the data controller. The address controller will have a request queue, a reply ID queue, a memory address decoding decoder, a paging comparator delay, a RAS / CAS status mechanism, an update status mechanism K, and all of the materials used by the selling controller The necessary control signal 0 SDRAM memory block will be the same as the system clock. The SDRAM will receive a copy of each control signal. 6,2.1 Recording Fang Yuanyuan, a capture controller This block diagram is shown in Figure 42. 6.2.2 SP. Anger Control System This process is shown in Figure 43. The address controller part of the 6.3-bit faf · Address Controller (JI) body controller will be responsible for generating all DRAM control with K, and managing the data controller with K. This part of the MSP memory controller will also be more expensive than the address and control path of the F bus interface. Each sub-block of the address controller is described in the following block diagram. -132- (Please read the precautions on the back before continuing on this page) -Package., 11 This paper size is applicable to China National Standard (CNS) A4 (210X 297 mm) " 4 3 67 1 Ο Λ Α Α7 ____ Β7__ 5. Description of the invention (M? Q 6 · 3 · 1 bit _ address system is hereby dragged i ns This square picture is shown in the 44th figure.

The FTFO MSP memory controller will be equipped with four deep request FIFOs, which will store all F buses for later allocation to the actual memory controller state mechanism. Address and control information. Each entry in the request FIFO will have a "valid" bit to indicate the validity of that particular entry. The record controller status control will always serve the lowest entry in the FIFO, which is EJJTRY_〇. Once the request has been serviced and the row address is gated (CAS *

Column Address Strobe) is made, the memory controller will announce a clear signal to clear this entry. Depending on the full / empty state of the FIFO, a barrel shift can be initiated to move the payload to entry 0. The MFIFO memory controller request FIFO format is shown in the 45th chapter. 0 6.3.3 Recording of lazy gambling system, gun address decoding / mapping, printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back first) Fill out this page again) This address decoding logic will be the main negative bit MA [I 0: 0] 2SDARM column address, and the 8-bit MA [7: G] row address. These address lines will be driven directly to the SDRAM address input [11: Q]. In order to obtain better performance and use of the memory address, the memory address bit [11] will be toggled between the internal SDRAM library with M. This memory address will be generated by the use of a programmable multiplexer. It will be fed through a register and indicated by M: -Current system cache memory line size -133- This paper size is common in China National sample standard (CNS M4 specification (2 〖οχ297mm) Reminders are displayed at a low speed to show the high display system. Figure 26, 10g) No. avgl0le memory element er of the fourth line of the In line is wrong. The intersection of the speed five and the high is a library library system. The system shifts the distance of the part. The internal part of the road is 0. The internal memory of the line is 436. Α7 Β7. , Generated by the F bus system address for 16 megabit DR AM. This multiplexed memory address will be valid for a period of time, by remembering the controller status control system. The R AS and C AS strobes indicated. The MCU has the capacity to perform 8-byte writes without having to initiate a read-correction-nesting (RM10 operation. However, the bits of the F bus address [2] should always be zero, which is only for the even starting address. This bit is mapped to bit [0] of the SDRAM address, which is Κ address indicating one of the three start bits, such as after the start address:

Faddr [4: 2] Write order (WRAP = 8) 000 0-1-2_3-4-5 ~ 6 ~ 7 010 2-3 ~ 4-5 ~ 6-7-0_1 1 0 0 4-5 -6 -7-0-Bu 2-3 110 6-7-Q-1-2-3-4-5 These are the writing sequences supported by the MCU, which are all even starting addresses. The assignments will be assumed to be 32 bytes, and the starting address should be (000) = rna [2: 0] = Faddrl4: 21 〇-134- This paper size applies to Chinese national standards (CNS > A4 specifications {2 ! OX 297 mm) --------- 1 ------ il ------ ¾ (Please read the notes on the back before filling in this page) Employees of the Central Standards Bureau of the Ministry of Economic Affairs Consumption Cooperatives Printed by the Ministry of Economic Affairs, Central Standards Bureau, Consumer Co-operation. Du printed d36 ”0, A7 _________ B7_ V. Description of Invention U Bing) 6 3 · 4 Memory Device Assembly MSP Memory Controller will Controller status control with a master control. This status control will be responsible for all timing used to generate SDRAM control signals (RAS / CAS / WE / CS / DQM). This status mechanism will continuously monitor for A valid entry in the entry 0 requests the FIFO. Once a valid bit is detected * the state mechanism will start the SDRAM sequence. The page-hit signal from the pager comparator will also be monitored to determine whether RAS pre-charging is required. RAS pre-charging will be performed by the current action / open library. Manual pre-charging sequence includes the announcement of CS , RAS, WE and MA [1G] to the operating state (which is zero). The internal library selection bit MA [1U will be used to select the library to be precharged. For the reading situation: the precharge command will be in The SDRAM has been announced after receiving the data to avoid data errors. For the writing situation: the precharge command will be issued after the last bit of the data has been written to the memory. Once a precharge command is completed * specific data The bank will be in an interleaved state. The M is ready for the next memory operation. According to the SDRAM specification, the precharge command can be issued at any time after tRAS (min) has been satisfied (60 ns for this example). However, since the wrap length is four (4), the memory controller will issue a precharge command after the data has been retrieved / written to the memory. SDRAM for MSP memory hip controller The number system is indicated as follows. List 1 7 SDRAM parameters -135- This paper size is applicable _ national standard (& ^^) 6 4 specifications (210/297 mm) --------- ^- ---- 1T ------ Brigade (I read the precautions on the back and then write this page) 4367 1 0 Α7 Β7 V. Description of the invention (/ Η, DRAM tRAS tRRD tCCD tRCD tCAC tRP 80HHZ ( 12.5ns) -10 Part 6 cycle 75ns 2 cycle 1 cycle 2 cycle 3 cycle CAS Lat en. 3 cycle 83HHZ (12ns) -12 Part 6 cycle 2 cycle 1 cycle 2 cycle 3 cycle CAS Laten. 3 cycle IT * tRAS can be It takes 5 cycles to reach the 60ns ROM access time of SDRAM | ----------- ^-(Please read the precautions on the back before writing this page) Staff of Zhongli Standard Bureau, Ministry of Economic Affairs Consumption cooperation. Please refer to the memory controller timing diagram. 6-3.4. 1 State Control System

The forty-seventh figure is a SDRAM memory hip controller RAS / CAS state machine I spring drawing. | 6.4 Recording the System and Envying Synchronous DRAM must be updated every 32ms (15.6ws) * to maintain the data in each cell. Synchronous DRAM also supports two update modes: AUTO REFRESH and SELF REFRESH. | 6.4.1 SI) RA Μ ”White 勖 Ψ new” borrowed standard automatic update mode • Both internal libraries are made by one | -136- This paper standard is common Chinese National Standard (CNS) Α4 specification (210 × 297 mm) A7 B7 printed by Zhengong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention U-ιn) internal counters are updated alternately. Since the number of columns is 4096, this automatic update mode will require 204 8 automatic update cycles M to update the entire DRAM. The automatic update command is issued by declaring that the low position is CS, RAS & CASM, and the high position is CKE and WE. This command will be announced only when both internal libraries are idle. (Samsung Corporation SDRAM Specification Revision 5) The time to complete the automatic update of the box is: tRC (min) 100ns (Specification)--8 cycles (80MHZ) Cycle time 12.5ns 6.4.2 SDRAM " White Me F New "Self Update Mode is another update mode available in Samsung SDRAM. For data retention and low-power operation, this is summarized as a better update mode. Here, SDRAM will disable the internal clock M and all except CKE Input buffer. When CS, RAS, CAS, and CKE are low and WE is high, they will enter the self-renewal horizontal mode. Because they must clear the SDRAM clock and use the CKE signal to restart, the MSP memory controller This update mode will not be used. 6.4.3 Fengdongzhengxin This is the third option for this update, which requires a state mechanism / counter design. The counter will time out every 15.6W s and announce -13 7-The size of this paper is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before writing this page) Zhuangquan A7 B7 Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumption Cooperation 衽 Printing To) An update strobe to the memory controller logic. The memory controller will then complete the current request * and immediately start the SDRAM update cycle. This cycle will be completely similar to the automatic update cycle without having to be in an idle state. Restrictions 0 6.5 DD »Data Control ler The data controller part of the memory controller will be mainly used as a data queue. K writes data to the processor from the processor or reads data from SDRAM. This control The device will also have a writer merge editor * which is used for all parts of writing (byte writers). Note | This part of writing starts with a DRAM read first, then merges the data | Finally, it will completely modify the word The group writes back to the memory. Therefore> any request after a partial write sequence will have to hit that performance. 6.5.1 Audio Material Processor This block diagram is shown in Figure 48. 6 This controller has the following package pins: RAS_I output pin (low-level action). This is a row address that is latched from the row address of MA [11: Q] to the selected one. DRAM library internal line address balancer. CAS_ I round-out pin (low-bit action). This series of address strobes is used to latch from the column address of MA [11: 0] to the internal column address of the selected DRAM library. WE_I output pin ( Low-position action • Used for writing). Used to drive the writer enable input pin of DRAH. -1 38- (Please read the precautions on the back before each page) Write '丁 -'a Travel paper size Applicable to China National Standard (CNS) A4 (210X 297 mm) Λ367, A7 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The invention is called MAfll: G] output pin. Multiplexed column and row address signals to DRAM. D9M output pin. Make the SDRAM data output high impedance * after the clock and mask the output. (This pin is only used for synchronous DRAM interface 0.) CS — I output pin (low-level operation). Used to disable or enable the selected SHRAM action. (This pin is for synchronous DRAM interface only.) CLK pin. This is only to the clock output pin of synchronous DRAM. This pin is for SDRAM only and has the same phase as the system clock of MSP. 6.7 捽 剌 SS 眭 庠 diagram This timing diagram is shown in the 49th to 51st diagrams. Notes on the fourth and ninth pictures: —Suppose it is Samsung SDRAM. -Memory and system are implemented at 80MHZ. --Or two external (1HX 16) SDRAM. The length of a programmable package is 4/8, and M finds a line from the memory. , TRCD = 3. -tCAS = 3o-internal delay = 2 cycles. —Memory wait time = 8 cycles (8X 12.5 = lQQns). A conventional data from memory will be delayed for two cycles1 for arbitration (retrieving data). 6.8 Program Vibration Cutting Type-1 3 9- This paper is suitable for Chinese National Standards (CNS) A4 (210X297 cm) (please read the precautions on the back before filling this page) Printed by the Central Bureau of Standards Consumer Cooperatives A7 _____ B7_______ V. Description of Invention (A.) As the programmer knows • The control register related to the memory controller is as follows. 6.8.1 SDR AM Stress Register fR / lM This register should be reset whenever the system is reset. This is a 1-bit register that sends a reset-sdram signal to start the SBRAH power in sequence. When the system is reset, this register is set to one (1). The body must clear this register K to enable SDRAM. Bit 0 is set as the system resets * and will be cleared later. Start SDRAM ° Programming address Faddr [31:20〗 = 12'h010 Faddr [3: 0] = 4'bl011 6.8.2 SDRAM Window material group glycoside temporary storage fR / ίΜ This register is programmed SDR AM data set type. This is a 1-bit register, which should be designed to be zero for the sequence of data sets. Programming address Faddr [3l: 20j = 12, h010 Faddr [3: 0] = 4, bl010 bit Q is reset with system reset, and set later to start SDRAM New Fe Store 51 (g / U) This register is the updated value of the programming SDRAM. This is a 12-bit register. It should be designed by F bus. Program Design Address-140- This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm): (Please read the precautions on the back before writing this page) A7 ^ Λ367 ^ 〇 λ __Β7 ____ V. Invention Explanation U,)

Faddr [31:20] = 12, h010 Faddr [3: Ο] = 4 'b 10 11 (Please read the precautions on the back before filling this page) Bit 11-Q is reset when the system resets. And it is designed to be the updated value of 4E0. 6.8.4 SDRAM PAS box is first filled with lightning ft: RP) temporary storage evil (R / W) This register is the pre-charged value of SDRAM RAS. This is a 3-bit register, which should also be designed via the F bus. Programming address

Faddr [31: 20] = 12, hO 10

Faddr [3: 0] = 4 'blOOO Bit 2-Q resets and resets, and is designed to be 1 or 2 or 3. 6.8.5 SDRAM HAS Memory Register (R / W) This register is the programmed SDRAM CAS wait time. This is a 3-bit register that should be designed via the F bus. Programming address

Faddr [31:20] = 12, h010

Faddr [3: 0) = 4 ^ 0011 Bits 2-0 are reset when the system resets and are designed to be 1 or 2 or 3. Printed by Shellfish Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs 6.8.6 shram m; This is a 3-bit register, which should also be designed via the F bus. Programming address

Faddr [31:20] = 12, h0 10

Faddr [3: 0] = 4 'b0010 -14 1- This paper size is in accordance with China National Standards (CNS) A4 specifications (2 丨 0X297 mm) Printed by the China Industrial Standards Bureau of the Ministry of Economic Affairs I7 Consumer Cooperatives A5 B7 Description of the Invention (^ 姐) Bit 2-Q system _ system reset and reset, and is designed to be 1 or 2 or 3. 6 8 * 7 SiLR AM Sentence. Hui 苒 This register is a package length of SDRAM for data. This is a 3-bit register that should be designed via the ρ bus. Programming address

Faddr [31:20] = l2’h010 Faddr [3: 〇] = 4, bOOO 1-bit 2-0 is reset as the system resets, and is designed to be 1, 2, 4, and 8. 6-8.8 S_DRAM NIP Flash Memory Register (R / W) This register is the NOP time that the SDRAM is used to send the sequence. This is a 16-bit register, which should also be designed through the F bus. Programming address

Faddr [31:20] = 12 ^ 010

Faddr [3: 0] = 4 'bOOOO Bit 15-Q is reset when the system is reset, and it is designed to 200 iiS depending on the clock frequency. Chapter t ASIC Interface This chapter describes the specifications of the ASIC interface unit. 7.1 槪 觏 This ASIC interface unit (Figure 52) will have a programmable 32-bit DMA, several FIFOs and control blocks. This ASIC interface unit will interface between: the main system bus (FBUS) and the C 0 DEC interface block-1 2 4-This paper size applies to China National Standard (CNS) A4 (210x 297 mm)- -------- ^ — {Please read the notes on the back 4-. Fill out this page)

11T Quan A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention 0 μ〇) 1 1 f The main system bus is implemented at 80 MHz. This ASIC interface unit interfaces the 1 1 I system to MSP, AD 1843. (Audio call) KS C 122 (Video 1 ί 1 Capture), KS 0119 and VGA. The current assumption is that »All 1 1 m I CODEC interface and DMA controller are implemented at F bus full speed > borrow read back 1 Ι © I to avoid any synchronization problems 0 Note 1 i Customer ASIC The block will have three main parts = F bus master controller note 1 I / slave interface, MSP eight-channel DMA controller Λ and actual coding solution 1 1 decoder (CODEC). The actual material will be streamed from the F bus to the encoder / decoder and written on this page. 1 and vice versa. However, the address will only be generated from the DMA controller 0. This address 1 1 will then map the F bus to the F bus interface. 0 All writes from other F 1 l bus nodes will be only -Program the register in the benefit part of the code solution 1 order code S2. All other dealings »Answers should be read along with the size and ID! | Please refer to F bus specifications. 0 1 1 The features of the AS 1C interface unit are as follows: 1 1 • Supports 32-bit basic DMA function (8 channels —'— one channel uses 1 涑 1 J in one codec) 2. 4 deep (de ep) X 64-bit data FI F0 1 1 _ One 1 deep X 52-bit data FIFO 1 1 «1 涸 2 deep X 52-bit reply FIFO 1 1 • Support for P bus and encoding Decoder interface block master 1 I / slave 1 1 | Oh supports internal arbitration for eight codec interface blocks 1 1 • Operating frequency: up to 80HH Z 1 1-143- 1 1 Paper standard: Chinese National Standard {CNS) A4 specification (2 丨 OX297 mm) r 4367 1 〇, A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention 1 1 J Support between I 0 Access to Memory 'Memory to 10 1 1 1 • Support Codec Initialization II «Support KS0 1 1 9 The highest priority of channel 0 is used first \ 1 Read I • Support special address bus U to achieve KSU 1 9 High-performance back II This customer interface logic will support three different incitements Code decoder: Note 1 1 • Audio and telephone codec (AD1843), this codec will have the meaning 1 I has a two-way 64-bit data bus, which will fill in a message with the DMA controller. 0 ( Channel 4 == > D AC 1-channel 5 == > DAC2, channel 6 = = > write this page and install 1 ADC left parameter channel 7 = = > ADC right) ° 1 1 • Video capture codec (KS0122), this codec also has 1 1 with bidirectional 64-bit data bus, and can start H-) 10 1 order and 10 — &M; M request to DMA (channel 2). i I «Video back-end codec (KS0 113), this codec will directly receive data from the memory controller (channel 0) 0 1 1 7. 2 Education r, Indignant (DMA ) Controller 1 Λ II DMA controller will have registers for address generation and translation 0 This DHA controller will have eight independent channels, each channel will have -1 '1 1 current address Register and stop address register. The start and stop address I 1 register will be pre-programmed through the configuration block. As long as there is a 1 1 DMA request to one of the eight m-code decoders, the current address register! I will be loaded. Once the F bus promises to access, this DMA address will be Every 1 t | cycle increments »until the current address is matched with the stop address register 0 at 1 1 > The DMA controller will generate a signal" E0P "(Processing complete! 1-144- 1 1 This paper size is applicable to China National Standard (CMS) A4 (210X29? Mm> A7 B7 Printed by the Consumers' Cooperative of the Central Standard Soap Bureau of the Ministry of Economy

End of Process). This signal will cause an interrupt to the processing. All eight DHA channels will have a common arbitration unit that will control these address comparison blocks. This DMA controller will support access between 10 to memory, memory to 10, M and memory to memory. As long as a codec has to talk to the DMA, it will announce a DMA_REQ signal and wait for a DMA acknowledgement 'DACK' from that DMA. Once it has been confirmed • the memory hip-10 signals and data will be driven. Depends The agreed DACK · DMA controller will select the appropriate channel. Please refer to the block diagram. 7.3 DMA register description 7.3.1 Current address register: Each channel has a 29-bit current bit The address register (bits < 31: 3 >) requires that all address systems be adjusted to 8-bit sisters. In fact * This register is a 29-bit countera This register can be used by ARM 7 The initial value will be loaded from the ARM7 through the F bus. This address will be increased based on the transmission size of the data. The address in the current address register will be sent to the address to generate Block to load the address on the F bus through the multiplexer. The current address register will maintain the address value during the interleaved state. 7.3.2 谆 1 Address rotation path: each The channel has a 29-bit stop address register (bits < 31: 3 >), which requires all addresses to be adjusted It is an 8-bit sister. This register is written by ARM7 through the F bus. These values will be guaranteed in the comparison area-1 4 5-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 Mm) --------- t ------ ΐτ ------ A (Please read the notes on the back before filling out this page) ^ 436T 1 Ο 4 Central Bureau of Standards, Ministry of Economic Affairs Printed by Bei Gong Consumer Cooperative Association Α7 _______ Β7_ 5. Description of the Invention (^-丨 Private) Compare the current address with the current address. If the current address matches the stop address, the DMA controller will generate a signal for each channel "ΕΟΡ". 7.3.3 Glucosamine: SS: This register contains information on whether each channel has reached the stop address. Bits < 7 · 0 > indicate which channel reaches the stop address. If ARM 7 Initialize the current address register via ecu and it will be reset. This register can be retrieved by ARM7, but ARM7 cannot write to this register. Contains control information for DMA controller action. The address < 7: Q > indicates which DHA channel is enabled for action. These bits are only required when corresponding When the track reaches the stop address, it will be reset, and ARM 7 can set these bits K to restart the operation. If any channel is enabled bit system "* Even if the corresponding code decoder sends DMA_REQ to DMA, the DMA will not provide DMA_ACK to the codec. Bits < 19: 16> indicate which pair of DMA channel strips are tied together as a double buffer. For example, if channel 0 and channel 1 are connected together as a double-element punch, when the current address of 埴 0 reaches its stop address, the DMA controller will automatically switch to channel 1: and when the channel When the current address of 1 reaches its stop address, the DMA controller will automatically switch to channel 0. Bit < 28: 21 > contains information about the capture / write mode of each channel. If any of the bits is set to "1" by ARM 7, the corresponding channel will be used for the capture operation. ; Other bits will be used for writer work. Bit < 3 1 > indicates whether DMA sends EO signal -14 6 " --------- batch of clothes ------ 1T ------ ^ (Please read the note on the back first Please fill in this page again for this matter) This paper size is applicable to China National Standards (CNS) Α4 size (210 × 297 mm) Printed by the Bayer Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy y r- ί 1 M A7 '___B7 _V. Description of the invention ( 々 ') to the lunch controller; if this bit is 〇', even if there is any channel to the 逹 stop address, the DMA will not send EOP. 7.3.5 General register: Each bit in the control register is related to one mask bit in the mask register. If the mask bit is *, it prevents M from updating the corresponding bit in the control register. Initially, this register < 31: 0 > will be set to Ffffffff (hexadecimal) ° 7.3.6 Program specification M: Start and stop addresses will be used to program MAKH7 through F bus 0 F bus mapping values are as follows: CCU ==== > 0〇40_0000-007F_FFFF, MCU ==== > 0080.0000-047F_FFFF, PCI = = = = > 08 0 0.0 0 0 0-FFFF.FFFF «For address programming * Address [26:01 should be set based on list 18. Listing 18: DMA register address mapping ----------------------------- Travel (Please read the precautions on the back before filling this page) Shift < 26: 0 > (hex) Number of bits 4AO_0000 29 Current address register 0 -147- This paper size is applicable to Chinese National Standard {CNS) 4 specifications (210X297 mm) 4367 t 〇 A7 B7 V. Description of the invention Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4A0_0008 29 Current address register 1 4AO_QO 1 0 29 Current address register 2 4AO_0018 29 Current address register 3 4AO_0020 29 Current address register Device 4 4A0_0028 29 Current address register 5 4A0_0030 29 Current address register 6 4AO_0038 29 Current address register 7 4A0.0040 Reserved 4A0_0048 Reserved 4A0_0050 29 Stop address register 0 4A0_0058 29 Stop address register Register 1 4A0_0060 29 -14 Stop address register 2 8- --------- install -------- IT ------ J- {Please read the precautions on the back before (Fill in this page) This paper size is in accordance with Chinese National Standard (CNS) A4 (210X 297 mm) ΑΊ Α 负 Ministry of Economic Affairs Central Standards Bureau Off-Work Consumer Cooperative System B7 Five 'Invention Description (/-岣 4Α0_0068 29 Stop address register 3 4ΑΟ_〇〇70 29 Stop address register 4 4Α0_0078 29 Stop address register 5 4Α0_0080 29 Stop address register 6 4Α0_0088 29 Stop address register 7 4A0.00S0 Reserved 4Α0_ 0 0 9 8 Reserved 4Α0.00Α0 32 Status register 4Α0_00Α8 32 Control register 4Α0_00Β0 32 Mask register list 19: Code of status register --------- Ziyi ----- 1T ------ Λ (Please read the precautions on the back before filling out this page) -149- This paper size is applicable to Chinese storehouse guidelines (CNS) Α4 specifications {210X297 mm) Α7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 6Ή 〇 Β7 V. Description of the invention

(Please read the notes on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) Λ4 size (210X 297 mm) Printed by Zhengong Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs 4 3 67 1 Q, Α7 Β7 V. Description of the invention Smart list 2Q: Control the encoding bit of the register and explain 0 Enable the channel for DMA transfer 0 1 Enable the channel for DMA transfer 1 2 Enable the channel for DMA transfer 2 3 Enable channel for DMA transfer 3 4 Enable channel for DMA transfer 4 5 Enable channel for DMA transfer 5 6 Enable channel for DMA transfer 6 7 Enable channel for DMA transfer 7 8 Reserved -15 1- --------- install ------ order ------ 1 (please read the precautions on the back before filling in this purchase) This paper size applies to China National Standard (CNS) Λ4 specification (210 × 297 mm) d ό b! \ 0. -Ϊ́ A 7 _____ Β7 V. Description of the invention 〇ΗΗ) 26 Channel 5 is used for reading (if this bit system is "1") 27 Channel 6 is used for capturing (if this bit is Bl ”) 28 Channel 7 is used for capturing (if this bit is“ 1 ”) 29 Reserved 30 Reserved 31 Please read the notes on the back first and then the home page.) -Installation, \ 3β Consumption cooperation with the Central Ministry of Economic Affairs of the Ministry of Economic Affairs. Du printed 7.4 CflDRn Initialization: The customer ASIC unit will support the initialization of each CODEC. In fact, ARM7 is responsible for CODEC initialization through the customer ASIC unit system. The customer ASIC army will have an address decoder > to generate a request signal for each CODEC. As long as the customer ASIC unit has to talk to any CODEC, it Will send the request signal to CODEC, and wait for the confirmation signal from the CODEC. After receiving the confirmation signal, the customer ASIC unit will send the data and address to the CODEC. When ARM 7 wants to obtain the configuration data of any CODEC through the CCU · The customer ASIC unit will send the address to CODEC. If the customer ASIC unit receives -1 53- This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) A7 B7 _ __ ____ _ — — ' '' " 丨 · " " " S, Invention Description (A ^) Data from CODEC will return the transaction ID to "11". At this time, the data will be sent to AHM7 through CCU. Listing 21: CODEC configuration register F bus address mapping and allocation to members of the Central Standards Bureau of the Ministry of Economic Affairs and consumer cooperation Du printed addresses < 31: 0 > (hex) Description To 04CO—1FFF C0DEC1 configuration register 04C0_2000 to 04C0_2FFF C0DEC2 configuration register fl4C0_3000Mfl4CO_3FFF C0DEC3 configuration register 0 4 C 0 _ 4 0 0 0 to 〇4 C 0 _ 4 FFF C0DEC4 configuration register 04 CD_ 5 0 0 0 to 04C0_5FFF C0DEC5 configuration register O4CO_6OO0S 04C0_6FFF C0DEC6® register 04CO_7000 to 04C0_7FFF C0DEC7 configuration register [J4C0_80 0 0 to 〇4C (J_8FFF reserved ---------- install-(please first (Read the notes on the back and fill out this page)

A This paper size is in accordance with the Chinese National Standard (CNS) 厶 4 grid (2! 0 X 297 mm) '4 3 6 Flying Α Ο Α Α7 —________ Β7 5. Description of the invention (Λ · 丨 04C0_9000 to 04Cfl_9FFF Reserve the fifth The thirteenth figure illustrates the customer ASIC circuit. List 22: Definition of I / O pins used in customer AS 1C unit Pulse input f_reset_l Input F-bus reset signal (low-order action) F_asc_grant_l Input F-bus promise from F-bus arbiter for ASIC unit (low-order action) F_asc_cs_l Input ASIC chip selection signal (low-order action) C0- size [7: 0] -C9_s ize [7: 0] Input CODEC data transmission size: 8'h08 = > 8 bytes, 8'hl0 = > 16 bytes, 8'hl8 = > 24 Bit-155- This paper is again applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) --------- ^: ------ ΐτ ------ Λ ( (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, V7 .J. A7 I · B7 V. The description of the invention is called group, 8 'h 2 (3 = > 3 2 bytes DMA_REQ 0 -DHA_REQ7 Input DMA from CODEC 謓 request signal ref.full input for screen update full signal FIFO (from MCU) F drdy _ 1 Input F bus ready signal, valid one cycle before the actual data Fdata [63: 0] Enter F bus data F addr [3 1: 0] Enter F bus rank Address F req _ ID [9: 0] Enter F bus request ID: [9: 6] = > Requester ID, [5: 0] = > Transaction ID Freq_size [7: 0] Rotate into F bus Data transfer size Frd_wr_l Input read / write instructions: "1" = > capture, " 〇 "= > write 156- --------- t ------- IT ------ ^ (Please read the note on the back first to fill in this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) ^ ^ * A7 ____B7 V. Description of invention UJ) Economy Printed by the Shell Standard Consumer Cooperative of the Ministry of Standards

Fpr_wr_ 1 input part write instruction (low-order action) CO.DATA [63: 0] -C9-DATA [63: 0] input codec data Fasc_dfull output ASIC unit data FIFO is full (to F bus arbiter) Fasc_aful1 output ASIC Unit response FU0 full (MF bus arbiter) Fasc_grCNT [1: 0] Outputs the F bus answer board counter, which requests a valid M to indicate the number of cycles allowed (to the F bus arbiter) Fasc_did [2 : 0] Output F bus destination ID to the request from ASIC unit Fasc ^ rec 1_ 1 Output F bus request signal from AS 1C unit (low-order action) CODEC output C 0 DEC address, which is only used for- 157- This paper size applies to the Chinese National Standard (CNS) A < t specification (210X297 mm) --------- t ------ IT ------. ^ (Please read first Note on the back, please fill in this page again.) 5. Description of the invention (MS?) Printed by ADDR [31: 0] CODEC configuration register grab / write (to CODECs) DMA_ACK0-DMA_ACK7 Output D Μ A confirmation signal (to C 0 DEC s) Crd_wr_l output for CODEC configuration register access Fetch / Write refers to CODEC.REQO-COD E C.REQ 7 Output CODEC request signal • — EOP output processing is completed. This signal to the interrupt controller · One Ref ^ addr [31: 0] output is used for channel 0 bits Address (to the MCU) addr „valid Output channel Q address valid signal (to the MCU) Fmeni.grant_l Input MCU promise signal, from the F bus judgment device Chapter 8 AD 1843 codec decoder (CODEC) mediation- 1 58- (Please read the precautions on the back #Fill this page first) Installation, 'r This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 29? Mm) C'l 1 〇A7 B7 Ministry of Economic Affairs The sample of the quasi-station Shellfish Consumer Cooperative Co., Ltd. V. Description of the Invention (A-ICD 8.1 This chapter describes the AD1843 CODEC interface. 8.2 View AD 1 S 4 3 C 0 DEC interface The block system interface is in AD 1 8 4 3 series Between the bus and the MSP DMA unit, the AD1843 sends and receives data and control / bark information through its serial itM. AD1843 has four pins for serial interface: SDI, SDO, SCLK, SDFS. The SDI pin is used for serial data input to the AD 1843, and the SD0 pin is used for serial data output from the AD1843. The SCLK pin is the serial interface clock. The communication of the AD 1843 must cause these data bits to be transmitted after the rising edge of SCLK, and sampled at the falling edge of SCLK. The SDFS pin is used for serial interface frame synchronization. The AD1843 CODEC interface is based on the master control mode. This means that the SCLK and SDFS signals are generated by AD 1 8 4 3. The default (default) SCLK frequency will be 12.288 MHz, and once the duty cycle is 4 8 κ Η z. The basic architecture of the CODEC interface is based on DMA. The AD1843 interface specifies 4 different channels: Channel 4 to DAC1, Channel 5 to DAC2, Channel 6 to ADC left, and Channel 7 to ADC right. The channel size transferred to or from DMA is 64 bits at a time. So * DM A channel 4 and channel 5 send two different 32-bit data (16-bit for left and 16-bit for right) data from SDRAM to CODEC interface. On the other hand, DMA channels 6 and 7 send out four different 16-bit data from the C 0 D C E interface to S DR A Μ. When the flag bit of each channel is set, the DAC1 and DAC2 interfaces can know that the data is available. The DAC1 and DAC2 interfaces request -159- --------- meal after checking the flag bit-(Please read the notes on the back before filling this page) The paper size of the book is applicable to the Chinese national standard. (CNS) A4 specifications (210X 297 mm) 43 671 0 Λ Α7 Β7 DAC 1 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, left, right DAC 2 right, right ADC left ADC right 5th, invention description 1) ^. If the flag bit system is reset, the 0 ^ (: 1 and 1) ^ 2 interface cannot generate a 1 ^ 4 request. The immediate operation of this flag bit is controlled by the DMA block. If the flag bit is reset, the DMA block cannot generate a DMA acknowledge signal. If the ADC's left and right FIFOs are not full, the DMA request will not be generated. The software should check the AS3C flag register and encounter the data bus to retrieve the remaining data. After reading these assets through the data bus, the FIFO is empty, and a D M A request is generated when the FIFO is full. By issuing a read / write request bit and the control register address in the control block input, the AD1S43 control register is used for reading and writing. When a capture is requested * the contents of the addressed control register are issued during the subsequent data segment. When a writer is requested, the data to be written must be sent to AD 184 3 slot 1. In order to modify the performance of MSP, the programmer should check the control flag register before fetching or writing the control register in CGDEC. If the flag bit of the control flag register is set > the capture and write operations of the CODEC register will be available. 8.3 DMA Channel Assignment (DMA Assignment) DMA Channel 4 DMA Channel 5 DMA Channel 6 DMA Channel 7 8.4 S Thanks to the breeding materials of DHA The data transmission size is 64 bits, and the allocation is as follows: -160- The paper scale is applicable to China National Standard (CNS) Α4 Specification (21〇χ297mm) * 1! Seed clothing I order — 1 I line (please read the precautions on the back of Jing before filling this page) 9 \ · Λ: ·. Η Α7 Β7 V. Description of the Invention (Α 儿 丨)

Bit < 63: 48> bit < 47: 32> bit < 31: 16 > element < 15: 0 > DMA CH4 DAI LEFT 2ND DAI RIGHT 2ND DAI LEFT 1ST DAI RIGHT 1ST DMA CH5 DA2 LEFT 2ND DA2 RIGHT 2ND DA2 LEFT 1ST DA2 RIGHT 1ST DMA CH6 ADC LEFT 4TH ADC LEFT 3RD ADC LEFT 2ND ADC LEFT 1ST DMA CH7 ADC RIGHT 4TH ADC RIGHT 3TH ADC RIGHT 2ND ADC RIGHT 1ST --------- ¢! (Please (Please read the notes on the back before filling this page) Address printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (RASF) address Q4C0_4000 DAC1 BASE 04C0_5OOO DAC2 BASE 0 4 C 0 _ 6 0 0 0 ADCLBASE (left channel) tHC〇_ 7G〇〇ADCR BASE (Right channel) Device co-location address offset description Capture or write DACI base + ο Control register write data input -161- This paper standard is applicable to China Solid State (CNS) A4 specification (210X29 * 7mm) 6 3 4 ο 5. Description of the invention DAC2 BASE + 0 ADCL BASE + 0 ADCR BASE + 0 DAC1 BASE + 2 DAC2 BASE + 2 ADCL BASE + 2 ADCR BASE + 2 control block input W DAC1 BASE + 0 DAC 2 BASE + 0 ADCL BASE + 0 ADCR BASE + 0 Control register data output R ADCL BASE + 2 ADCR BASE + 2 ADC flag register R ADCL BASE + 10 ADC left 1st data R ADCL BASE + 12 ADC left 2nd Data R ADCL BASE + 14 ADC left 3rd data R -162- installed-{Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 male f) B7 V. Description of the Invention (A-㈣ Printed by the Consumers' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs

ADCL BASE + 16 ADC left 4th data R ADCR BASE + 10 ADC right 1st data R ADCR BASE + 12 ADC right 2nd data R ADCR BASE + 14 ADC right 3rd data R ADCR BASE + 16 ADC right 4th data R DAC1 BASE + 20 DAC2 BASE + 20 ADCL BASE + 20 ADCR BASE + 20 Control flag register R 8.7 Reservoir Zeiss 8.7.1 Tzu-made register input data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dl5 dl4 dl3 d! 2 dll dlO d9 d8 d7 d6 d5 d4 d3 d2 dl dO This paper size applies to Chinese national standards (CNS > A4 size (2! 〇 X 297 mm) (Please read the notes on the back first (Fill in this page again) -163- 43 67 1 Ο 4

1- i_L

1 J_I_I_I__I J_t 1 The most significant bit (MSB) is the first data input bit to be transmitted 8.7.2 Control _ Li Yanlun λ 15 14 13 12 11 Please read the notes on the back 4 · -k '' X: ί r / tf ia4 ia3 ia2 ial

iaC order r / w capture / write requirements. A fetch from the control register or a write to the control register occurs at each information segment. Set to "1" to indicate the capture of a control register; resetting this bit to " 0 "will initiate the writing of a control register. Λ Printed by the Consumer Cooperative of the Central Standards Bureau, Ministry of Economic Affairs The person holding the temporary address control ^ Write, lose, or take the pipe for II to use? Ο ® 4: 捽

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dl5 dl4 dl3 d! 2 dll dlO d9 d8 d7 d6 d5 d4 d3 d2 dl dO 64- This paper standard is applicable to the China National Standard (CNS) A4 specification (210X297 mm) 4 3 67 1 〇, Α7 Β7 V. Description of the invention (Α 艰)

I _] _ I_I_I_I_I_I_I_I_I_I_I_i I_i_L 8.7.4 Ai) Please read the flag register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0:-i r4v r3v r2v rlv I4v 13v 12v llv r > ' , R4v-rlv The effective ADC right data is in the punch. Point out which data in the buffer is valid. The 14v-llv ADC is actually left in the buffer. Indicate which asset in the Yu Yuan punch is valid 8.7.5 ADC left first window is ordered by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Consumers Cooperative 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d! 5 dl4 dl3 dl2 dll dlO d9 d8 d7 d6 d5 d4 d3 d2 dl do ADC left first data in the buffer. -1 6 5-This paper size is applicable to China National Standards (CNS) Λ4 specification (210 X 297 male) Α7 Β7 -43 671 Q, V. Description of the invention (Α-ί &) 8.7.6 ΑΠΓ2nd left For information, please 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0; (1 \ Ϊ: dl5 dl4 dl3 dl2 dll dlO d9 d8 d7 d6 do d4 d3 d2 dl dO-in the left of the ADC in the balancer Second data 8.7.7 ADC left third data _ Ί Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 i 0 dl5 dl4 dl3 dlZ dll dlO d9 d8 d7 d6 d5 d4 d3 d2 dl dO Yu Yuan 8. 7. ® ADC left third RAD f: left fourth breeder information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -166- this paper Standards apply to China National Standard (CNS) M specifications (210X297 mm)

A '43 67 1 〇, Α7 — Β7 V. Description of Invention Howling)

dl5 dl4 dl3 dl2 dll dlO d9 d8 d7 d6 d5 d4 d3 d2 dl dO ADC left fourth data in Yuan Yuan puncher 8.7.9 Please refer to the note on the back of the flag slot register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r, wfl rf. Η Member of the Central Standards Bureau of the Ministry of Economy Η Consumer Cooperatives printed wfl control register to write flags. If set, the CODEC is prepared to receive the control register data. rf 1 Controls the register capture flag. If set, the CODEC is ready to send the control register data. Chapter 9 Video CODEC 9.1 Overview This video CODEC series is from the interface to the KS 0 1 1 9 and KS 0 1 2 2 chips on the evaluation board, and the interface is to the D M A module in the MSP chip. . The KS () 119 CODEC can also provide screen update operations. For this operation, a direct data path to the MCU module is implemented as shown in the fifty-fourth plaque -167 paper size, using Chinese National Standard (CNS) A4 (210X 297 mm) Λ 4 3 671 0, Λ7 B7 V. Description of the invention (A- / 9.2 Top (t η d)) As shown in Figure 55, the top module includes three sub-modules: • KS0119 screen update module Sister • KSG 122 video data capture module, and three-line serial host interface module, which accesses KS 011 9 and KSQ 1 2 2 chip configuration register 9. 3 ί) Μ Α 道道 宝 DMA CHO KS 0119 CODEC DMA CHI Reserved DMA CH2 KS 0122 CODEC DMA CH3 Reserved DMA CH4 AD 1843 Audio CODEC DMA CH5 AD 1843 Audio CODEC DMA CH6 AD 1843 Audio CODEC DMA CH7 AD 1843 Audio CODEC DMA CH8 Reserved DMA CH9 Reserved — (Please read the back first Note * .Fill in this page) Order Λ. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Cooperatives, and Consumers Cooperatives, and detailed information on this module is introduced to KS 0 1 1 9 and KS (Π 2 2 wafers, all registers located inside these wafers are The serial interface is used for access. The serial interface module supports the functions of the communication protocols to the chips. Once it contains the registers for the KS0119 and KS (H22 interface series. The second reference is 9.5 ΕΡΚΠＭ 介-1 6 8-This paper size is in accordance with Chinese National Standard (CNS). ^ (210X297 mm) " 4 3 67 1 〇, Α7 Β7 5. Description of the invention (A-ton) KS0119 10 pin is also used As an external EPROM interface *, the EPR 0 Μ is used to load program data immediately after the system is reset * and is part of the MSP-1EX startup initialization. Please refer to the pin assignment Μ for more details. EPROM is a memory mapping from the address range of COOOOH to DFFFFH. 9.6 KS 01 〖9 Register Description KS0119 has a basic address C0DEC_REQ0, which is equivalent to Q4BQ0000 and extends to Q4BFFFFF. 9.6.1 KS011Q register imitation hi · Shoot KS0119 Register Address Map Employee Central Coordination Bureau of the Ministry of Economic Affairs Consumer Cooperatives Printing Offset (hex) Register Name 0 Gong Segment Size Register 1 ID 2 Control / Data Byte 3 Index / Data 0 4 Information 1 " 16 9- Pack ------ Order ------ Brigade (Please Please read the notes on the back before filling in this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) 4367 1 0 Λ Printed by the Central Government Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 5 Materials 2 6 Materials 3 7 Status register 8 Capture data serial interface 9 Read PR0M data A A Control register B HS, VS Polarity C HS offset D VS offset 9.6.2 Segment size temporary temporary evil This temporary The controller controls the size of the data segment to be transmitted to the CODEC chip, as defined in Figure 50t. The minimum field length is 3 bytes. 9.6.3 Crystal M Τ Π 堑 Memory device-1 70- This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) III i I — —i. ... I IJ. I Order! Γ] (Please read the notes on the back before filling out this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4 3 67 1 〇 * Α7 ~ ---------------- Β7 ____ V. Description of Invention 0) This register should contain the CODEC chip ID value, and it should include G3H for KSG119 writer and 83H for KS0119 capture. 9.6 · 4 Controls / Controlling: Save This register informs the CODEC chip KS0119 that the bytes transmitted subsequently will be a register index or a data bit sister. For KS01 13 = 0 8 H, the index of the interested person is the following bit; and for K S 0 11 3 = 0 9 Η, it means that the data is the following byte. 9 · 6.5. Index / 索引 Μ0 堑 register This register will contain the index value or data 0 byte used for the CODEC chip configuration register, which depends on the value transmitted in the previous byte. Please refer to the communication protocol in the programming reference chapter.

9.6.6 substitute material 1 堑 # 5S This register contains the data to be written in the CODEC register, index +1. 9.6.7 Audio Material This register contains the data to be written in the CODEC register, index + 2. 9.6.8 Data Register This register contains the data to be written in the CODEC register, index + 3. 9.6.9 Filling the Birch Register The bit designation for the KSG119 control register is shown in Figure 58. 9.6.10 HSSB VS Orange This register defines the polarity of the horizontal sync and vertical sync signals. — A value of 0 is defined as a low action. • A value of 1 is defined as a high action. -17 1- This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210 X 297 mm) IΠ-1 . — II II-1 I — I n ^ I Ϊ nn H (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy The bit designation is as follows: Bit < 0 >: VS Polarity Bit < 1 >: HS Polarity 9 * 6-11 The HS service signal is generated after this offset value. It is defined as 00H. 9.6.12 VS deflection action signal is generated after this offset value. It is defined as 00H. 9.6.13 Status register This register is shown in the 59th figure. 9.6.14 Take the data string Agent and register This register will contain valid data from the serial port, after the capture flag has completed the transition from the in-use state to the ready state. 9.6.15 _f 取 ΡΙΠΠΜ Caution (Save) If the PROM flag is in the ready state | This register will contain valid FROM data. The video display hardware can be configured to operate in two different modes: • VGA overlay mode. • VGA emulation. This mode is operated by setting one of the logic control registers.涸 位 -172- --------- install — (Please read the precautions on the back before filling this page)

1T This paper applies the national standard (CNS) A4 specification (210x297) according to the standard 4367 1 IB; the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China is printed 5. The description of the invention (A,) yuan is controlled "MSSEL = 〇 * For VGA overlap mode * = 1, for VGA emulation mode. In VGA overlay mode, a VGA card on the PC system is required. • The monitor cable will be buried in the MSP card. The supported VGA resolution is up to 80 × 6i) G. The display adapter must have the same size as the VGA setting. To set up a video window | The software must fill a rectangular area of a color key in the VGA sales section. The video data in the MSP SDRAM should be written in the same size as the rectangular area in the VGA section. A rectangular area with positions. Please refer to Figure 16. The KS0119 chip will recognize the color key and switch from the VGA input port to the video input port. Software: Set the start address of DM A through 0 to the left of the top of the SDRM video output buffer | DMA record length should be set according to the pixel resolution used in the VGA card to set the resolution and video data (4 : 2; 2 = 16 bits per pixel). 9.6.16.2 The configuration register settings of the three KS0119 chips are described below. The protocol is as follows: • At least two information segments must be transmitted to the peripheral chip. • The first information segment is to set the configuration. Index of the register. • The second information segment is used to read or write data (register content). The software should set the size of the information segment register to an appropriate length and set -173- ----- ---- ^ ------ it ------ (Please read the precautions on the back before filling out this page) This paper size is applicable to the Chinese National Standard {CNS) A4 specification (210X297 mm) Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China _____B7 V. The description of the invention (AW) serial access bit is 1; then, the software should load the information for the information section before changing the size register For all bytes, the CODEC interface logic will wait until all the bytes have been loaded before starting to serialize the field. The first piece of information is used to set the index. The segment size is 3 bytes. Please refer to the 61st plaque. The second piece of information is used for the K register, and the size of the piece of information is 3 bytes. After each data byte, the chip will automatically increment the index by 1 * This allows setting up a flail register, which sends out multiple data bytes, and the CODEC interface logic can support up to Four data bytes. When performing a capture or write serial operation, the software should check the status register, which is used to read and write valid data flags during the capture operation, or prepare it before sending the next information segment Write flags. The following examples will show the setting of KS011 3 configuration register step by step. To set the value of byte 0 and byte 1 for chroma key * The index of this register is 6AΗ for byte 0 and 6BH for byte 1, please refer to KSIH19 data file. Since the two registers have a continuous Myanmar index, the two bytes can be loaded into a single piece of information. First, the index must be set as follows: * The value of Μ83Η (the size of the information segment is 3 and the serial access bit is set). Load the information segment size register (address is 〇4Βϋ_ϋΟΟ (] Η). • MG3H The value is loaded into the ID register (the address is 〇4BQ_G001H). -174- This paper size is applicable to China National Standards (CNS > Λ4 specification (210X297 male t > --------- reference- ----- 1T ------ ^ (Please read the notes on the back before filling out this page) d367 ^ 〇, ab; -------------- 5. Description of the invention (A-OS) • K loads the data / controlling bit sister (address is 04B0_0002H), which indicates that KSG119 should be the next byte index. • The value of M6AH is stored in the index register (address is Q4BQ_0003H). The serial interface will detect a situation that matches the content of the information segment size register, and will initially send out the information segment. At the same time, the write flag in the status register will be set to in use (busy ) Status, before loading the next piece of information • The software should check the flags in the status register. When these flags are in a ready state, the software can load the values for the next piece of information. 9. 7. KS (H? 2 temporary # device description KS0122 has a basic address C04DEC_REQ2 equivalent to 04C02000, and extends to 04C02FFF. (Please read the precautions on the back before filling this page) —Industrial and Consumer Cooperatives ’printing 9.7.1. KS01?.? Storage location address mapping Hire register name (hex) 0 Information segment size register 1 ID 2 Control / data byte -175- This paper Standard General Chinese National Standard (CNS) A4 specification (2IOX297mm t) Π Λ— 7 f

7 B A7 V. Description of Invention (PH%) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 3 Index / Information 0 4 Information 1 5 Information 2 6 Information 3 7 Reserved 8 Query the serial interface 9 Reserved A Edit Control register B reserved c reserved D reserved E status register -176- --------- button clothing — (please read the precautions on the back before filling this page) Standard (CNS) A4 (210X297 mm > 4 3 67 1 〇 Α7 Β7 Duty Packing and Consumer Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs Ⅴ. Description of Invention (Α-ιη) l_ I _________-------- 9.7.2 2菅 Segment f? Inch register This register controls the size of the information segment to be transmitted to the CODEC chip, as defined in Figure 62. The minimum information segment length is 3 bytes. 9.7.3 Wafer TDg register This register should contain the CODEC chip ID value * and should include D4H for KSD122 write and 84H for KS0122 read. 9. 7 .4. The register informs the CODEC chip KS0122 that the subsequent transmission byte will be like a register index or a data byte. For 1 ^ 0122 = 01) 11 ’means the following byte system index; Q 1Η means the following byte system data. 9.7. 5. Index / All 0 Register This register will contain the index or data 0 byte used for the CODEC crystal configuration register, which depends on the value transmitted by the previous byte. Please refer to the communication protocol in the programming reference chapter. 9.7. 6. 1 g of money to save money This register contains the data to be written in the CODEC register, cable bow | + 1 〇9.7.7 porcelain 2 register This register contains Write the data in the CODEC register, index + 2.

9.7.8 Audio material 3, 5S -1 77-This paper size is applicable to China National Standard (CNS) A4 (210X297). (Please read the precautions on the back before filling this page) -Frame-〇: Even bit 1: Exotic bit < 1 >: VS State Printed by the Consumer Cooperatives of the Central Directorate of the Ministry of Economic Affairs 0: VS from 1 to 0 1: VS from 0 to 1 9.7.11 Read Livestock The register This register will contain valid data from the serial port, and the flag has been changed from in use to ready state when the flag is obtained. 9.7.12 The configuration register of KS 牵 2 2 chip is set with KS 0 1 2 2 string, and this protocol is as follows: * At least two pieces of information must be transmitted to the surroundings Chip, • The first information section is used to set the index of the configuration register, • The second information section is used to retrieve or write data (register contents) -178- 4 3 6710 ^ A7 B7 V. Description of the invention (This register in the state of AI contains the data to be written in the CODEC register, index + 3. 9.7.9 ICS0122 edited g register for KSG 1 2 2 control register bit The designation is as follows: bit < 1: D > 0 0 4: 2: 2 format 0 1 4: 1: 1 format 10 CCIR656 format 10 state register bit < Q >: bit ( fie 1 d) Condition This paper size is applicable to Chinese National Standard (CMS) Α4 specification (210X 297 mm) --------- seed coat ------ 1T ------ ^ (Poem Please read the precautions on the back before filling this page) Α7 Β7 4367 1 0 V. Description of the invention (cutting 0 software should set the size register of the information segment to a proper length 'and set the serial access bit to 1. Then, changing Before the segment size register, the software should load all the bytes needed for the segment. Before starting to serialize the segment, the C 0 DEC interface logic will wait until all the bytes are loaded. The first information segment is indexed by M. The size of the information segment is 3 bytes. Please refer to Figure 62. The second information segment is used to set the register. The size of the information segment is 3 bytes. After each data bit sister, the chip will automatically increment the index. This allows M to send multiple data bytes and set a register for continuous performance. The CODEC interface series can support up to 4 data bytes. When performing a serialization or write operation, the software should check the status register, the capture and write flags * for valid data for the capture operation, or prepare it before sending the next piece of information Write the flag. The following example shows the step-by-step setting of the KS 0122 configuration register. To set the value for the chroma bit sister (1 and bit sister 1, the index of this register is for byte 0 System 6 ΑΗ, and byte 1 is S Β Η. Please refer to KS0122 data file. The two registers have a buried index. * The two bits can be carried in a single piece of information. First * the index must be set as follows ... • • The value is 83Η (the size of the information piece is 3 and Serial access bit setting) contained -179- This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) --------- ¾ ------ 1T-- ----- Brigade (Please read the notes on the back before filling out this page) Printed by the Central Government Bureau of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperative, w 0 Α7 Β7 (A-call into the real segment size register (address = (HBQ_Q 〇〇 () {{). . Load the ID register with the value of Q3H (the address is. • Load the data / control byte with the value of G 8 (the address is 04B0_00 [] 2Η), which indicates the lower byte of KS0122. Index. Load the index register with the value of 6AH (the address is (ΗΒ0 — 0003Η). The serial interface will detect a match with the content of the information segment size register, and send out the information segment. ; At the same time, the flags written in the status register will be set to be in use. Before loading the next piece of information | the software should check the flags in the status register. When these flags When the mark is in the ready state, the software can load the value for the next information segment. Chapter 10 Bitstream Processor 10.1 This chapter describes the design of the bitstream processor (BP) Functional requirements, the bit stream processor is one of the main MSP processing cores for video data compression and decompression applications. 10.2 gj Μ A / V audio and video BP bit stream processor (MSP block) CCU high speed Buffer Memory Control Unit (MSP Block) CIF Common Intermediate Format * It has 352X 288 at 29.97Hz Resolution: DCT, discrete cosine conversion, DMA, direct memory access, DSM digital storage media " 18 0- Paper size, using China National Standard (CNS) A4 specification (210X 297 mm) ------ --- Installation— (Please read the notes on the back before filling in this page) .1Τ W 4367 1 〇 ^ V. Description of the Invention (a-iSI) FBUS Fast Bus (MSP Internal Data Bus) GOB Block Group USTN—Generally switched telephone network (also known as PSTN) HDD hard disk drive software I / F interface I0BUS input wheel-out bus (MSP internal peripheral bus) ISDN integrated service digital network ITU-T-601 for color Standard for digital encoding of television signals. These signals have 7 2QX 48 0K at 29.97Hz and 720X576 at 25Hz (previously referred to as CCIR 601), but the display resolution can be 720X 480 or 704X480 LSB Least Significant Bit LUT Search List MPEG Animation Experts Group MSB Most Significant Bit MSP Samsung Corporation Multimedia Signal Processor Ministry of Economic Affairs Central Standards Bureau Shellfish Consumer Cooperation • Printed by Society (Please read the precautions on the back before filling out this page ) Q CIF quarter CIF, which has a brightness sampling resolution of 176X 144 at 29.97 Hz, RLC execution length and hierarchical code SDRAM synchronous dynamic random access memory SIF for MPGE-1 video standard source input format ' It has a brightness sampling resolution of 352X2 0 for NTS CK 2 9. 9 7 Hz -181- This paper size applies to China National Standard (CNS) A4 specification (2) 0X297 mm) Staff consumption of the Central Bureau of Standards, Ministry of Economic Affairs Cooperation. Du printed '43 671 Ο Λ β7 _ V. Description of the invention (Α.) · And brightness sampling resolution TBD for PAL M25ΗZ = 352X 288 For definition VLC variable length code VP vector processor ( MSP block) 10.3 Key Features * Supports the truncation (or 60B) layer for HPEG-1, MPEG-2, H.261, and H.263 encoding and solution applications and the following grammatical analysis and composition • Real-time Perform RLC processing • Instantly perform Huffman code processing for all Huffman lists listed in the MPEG-1, MPEG-2, H.261, and H.2 63 video standards • Supports two forward / reverse Tooth scan conversion rule is 731.4 million bits per second (32 bits @ 40 «1 ^) 10-bus interface with maximum transmission rate • Maximum operating clock frequency is 40 Μ Η 2 • Includes 9.2K ROM for Huffman CODEC search list • Includes 320 internal SRA Μ • Support Pre-fetch and shared text switching methods • The target used to control the path is 6K ** plus RAM and ROM 10.4. The bit stream processor (BP) is one of the four internal MSP peripherals. Its * 1 8 2---------- ^ ------ 1T ------ ^ (Please read the precautions on the back first to complete this page} The ft scale of this paper is applicable to Chinese national standards孳 (CNS) A4 specification (210X297 mm) Λ 3 b η Α7 Β7 Employees of the Central Standards Bureau of the Ministry of Economic Affairs f Cooperatives printed 5. The description of the invention is a dedicated hard gambling editor block * Support video compression and resolution with M Different bit streams of the compression standard. Because the VP and ARM7 located inside the MSP do not have an effective architecture for these bit processing • This BP unit is specially designed for bit-level processing. This BP pseudo sends and receives data through a 32-bit bus called IOUBUS, which has a maximum transmission rate of 731.4 million bits per second. This BP system performs like an independent process Qin Yuan and is under the software control of ARM 7 or VP. More specifically, BP encodes and decodes all information contained in a truncation or SOB layer and K, receives the data from the CCU, and sends the data to the CCU. This BP also performs forward and reverse tooth conversion, and encodes and decodes the differential DC coefficient. In addition, BP uses the differential motion vector M to decode a motion vector * when decoding, and performs the reverse operation when encoding, in addition to the following two special modes: dual best when MPEG-2 encoding (dualprime ) Mode, and advanced prediction mode in Η.263 encoding and decoding. This BP is assumed to be operating in simplex mode * meaning that once this BP starts processing-cutting or G 0 Β, the BP will not be interrupted until the truncation or G 0 8 processing system is completed. . This implies that full-duplex mode can be achieved by interleaving encoding and decoding cuts or GB0. However, if ARM7 wants the BPP to switch to another task immediately, this BPP will support the pre-emptive text switching mode. It can terminate the BPP processing before the current cut or GOB system is completed. The third figure shows a block diagram of BP. As can be seen from the third figure, the BP includes five blocks: an IOBUS interface unit, a VLC FIFO unit, a VLC LUT ROM, a control state control, and a BP core unit. Entering people and exporting capital -1 8 3---------- Installation ------ 1Τ ------ ^ (I have to read the precautions on the back before filling out this page) Standards are applicable to China National Standards (CNS) A4 specifications (210X297 mm) 4367t A7 B7 V. Description of the invention (λ-ι_ Materials are processed by I0BUS interface unit, which includes a 16X32 bit RAM. It supports all Data movement and interrupt request. VLC FIFO is used to prepare the next data block for data decoding and to perform output data encapsulation for data encoding. VLC finds that the table R0X has 768X12 bits. Size, which holds all the necessary information for all Huffman code processing. The control state mechanism controls all encoding and decoding actions in this design. The BP core unit is a small processor that includes an adder. , Comparator, column register, register register, and 128X 16-bit EAH. Because of this core *, this bit processing is available. 10.5 Signal Hongsai 8 P The required signal series for the external interface is shown in Listing 2 3. The signal at the end of the K letter "i" means a low position. Please note In the "Direction" list of the list, "B", " I »and" means two-way signal, input signal and output signal respectively. Installation ------ Order ------ ά (Please first Read the note on the back ^ and fill in this page) Printed list by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 2 3: BP signal definition Signal size direction description I0BUS [31: 0] 32 B 32-bit bidirectional multiplexed address And the data bus. If the operation is completed, the main controller should release the signal to tri-state. * 18 4- This paper size applies to the Chinese national standard (CNS M4 specification (210X 297 cm) 43 671 0 ^ V. Invention Explanation (Α-called A7 B7 IOB_rd_l The capture enable of the low-level action, which is used for all capture / write transactions, is the output of the master and the input of the slave. If the job image is completed, the master should Disarm the signal as tri-state. 阅读 Read the precautions for the background first, and then install the IOB_wr_l low-level write enable function, which is used for all capture / write transactions. I series master output and slave input. .If the operation is completed, the main controller should release the signal to three 1 ding I OB_ready_l Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs I 0 B _ c s. This paper size is applicable to China National Standards (CNS) Α4 specifications (210 × 297 mm) low-level action signals, which are from the slave device. Output and input of the master | Use M to indicate when the master is available for reading in slave mode. If the operation is completed, the slave should release the signal to tri-state. The low-level component selection signal is from the arbiter to Β > Μ 旅 185 6 3 4 ο

A

7 B V. Description of the invention Request by the Central Bureau of Standards of the Ministry of Economic Affairs of the Consumer Cooperative for Printing once the address is latched. IOB_ale_l 1 I Address strobe for low-level operation, which is the output of the arbiter and the input of B P * for master / slave operation. I〇B_req_bsp_l 1 0 Request for low-level action, from BP to the arbiter, M becomes a master controller for the bus to take or write transactions 0 IOB_tsize [l: 0] 2 B Data from the master to the slave , M indicates the transmission size, which is equivalent to one of 4 '8, 12, and 16 bytes. I OB_grant_bsp ^ 1 1 I The promise signal for the low-level action, from the arbiter to BP. Reset ″ 1 I System reset in low position. -18 6- The size of this paper is applicable to China National Standard (CNS) M specifications (210X29? Mm) (Please read the precautions on the back before filling this page)-binding. Order 4 3 67 1 〇a?-Β7 5 Description of the invention ⑷㈧ C 1Κ40Μ 1 I 40Mfiz clock ARH7_IRQ 1 0 Interrupt request signal • BP from AR Μ7, this signal should be cleared by ARM? In fact, this interrupt signal requested by BP is sent to the interrupt Controller, which is also an I 0 bus element. ------------ Installation-(Please read the precautions on the back before filling this page). Cooperative printed 10.6 Tian Yuxiang / Xie Xixi Materials. This section includes an example of a data stream for a typical video encoding and decoding application. It should be noted that * this document does not describe the audio data stream in detail 0 10.8. 1 媪 磘 Situation expensive-Step E 1: The entry of unprocessed A / V data is generally assumed that the incoming audio and video signals are sampled and digitized by an external codec, and then fed to the customer ASIC. But • In a multimedia PC environment • Some VGA controller cards are also Includes information segment (picture) grabbing device M and sound capture device. Therefore, it can be assumed that the unprocessed A / V data is fed by the customer ASIC or PCI bus interface. The customer ASI C and PCI bus interfaces include A small 32-bit buffer. The data in this buffer is borrowed from DMA logic M to be transmitted to the external SDRAf through a fast bus! Note | This data movement will start at the time of -187 -This paper size is in accordance with Chinese Standard (CNS) Α4 specification (210 × 297 mm) Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs 0._B7 I ------------ V. Description of the invention After resetting, it starts with AR Η 7. κ2: > λ VP makes advance wave. First, VP finds the unprocessed image data stored in SDR AM '. Take the padding area). Then * VP performs temporary ripple and spatial calibration on these pixels. Pre-filtering • Image resolution is generally converted from TTU-T601 size to CIF or QCIP size. VP is also responsible for Write the result of the previous wave to external SDRAM ° R3 By compressing the data of the VP, the VP again finds the pre-filtered data of SDRAH, and flushes the memory to the VP data at high speed. K executes the compression according to the rules proposed by the corresponding standard. Generally speaking, the VP execution section goes to the DCT and the front. Adaptive quantification, motion estimation, macro block type decision, etc. When completing these functions, the VP should rewrite the results including the appropriate start code information * into the VP data cache memory. In fact, this VP data high-speed title memory area can be used as a BP input buffer. To check the status of the buffer, a flag signal is used. Step _. Step E4: BP initialization by ARM7 Before BP actually starts its operation, ARM 7 should initialize the internal register of BP. Note that this initialization should not be performed during the period of 128 cycles after the power-on reset signal is asserted. Specifically, ARM7 must initialize the input and output balancer addresses and the BP command register, and specify the number of macro blocks to be encoded in this cut or GOB. Initializing these temporary -188-This paper is mounted on the same standard as the National Standard for China (CNS) A4 (210X297 mm) --------- Installation ------ Order ------诔 (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperation Department of the Central Bureau of Standards of the Ministry of Economic Affairs 4367 1 〇 Α7 ___ * _ Β7 ____ V. After the invention description (/ Vir?) Register, ARH 7 should be set BP enable flag, K starts BP processing. Also step E5: By the bit stream of BP, if any of the input libraries of Shuangyuan Punch are full, BP starts reading data through 10 buses. Only when the buffer is full, BP can fetch data. Then, the BP is converted to the 8X8 block data in the tooth format, and the result is directly RLC and Huffman code. The Huffman coded result can be transferred to ARM7 data high speed memory or SDRAM. Only when the scale is empty, BP must write a person to the output element * to avoid the overflow of the element. When the processing system ends (that is, the number of processed macro blocks is equal to the number of macro blocks specified by ARM7), BP must interrupt the ARM7 by the byte and bit position of the last data and terminate the current Cutting or G 0 Β treatment. Step E6: By the bit stream composition of ARM7 and A / V multiplexing By combining these Huffman-edited data and syntax parameters, ARH7 can form the final bit stream and repeat this process. ARM7 is also responsible for controlling the upper layers of the cut or G0B, and multiplexing the audio and video bit streams. This result was written by M ARM7 to SDRAM. Step R7: VP network interface (option for video conference) For video phone or video conference applications, the results up to step E6 can be processed by the VP to perform a network interface function, such as for 324.324 GSTfJ video phone V.34 modem (modem) or 1.400 serial interface for H.320 ISDM video conference terminal. Step 8E8: The last bit stream output-18 9------------------ ΐτ ------ ^ (Please read the precautions on the back before filling this page ) This paper size is in accordance with China National Standard (CNS) A4 (2 丨 οχ297 mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4367 1 Ο λ αβ] 5. Description of the invention (Α- 咖啡) Stored in SDRAM The final bit stream will be sent to the customer ASIC or PCI bus interface. Generally speaking, the customer A S IC block will be used for the network interface, and the PCI bus interface will be used to store data to a recording component (such as a hard disk drive HDD). This data movement uses DMA data transfer and must be initiated by ARM 7. 10.6. 2 Resolving steps J) 1: The bit stream is found in the multimedia PC environment. The bit stream that has been pressed to 0 will be fed by any one of the CD-ROM driver software, HDD, and network interface. Into. Therefore • It can be assumed that the source of this bit stream is the customer ASIC or PCI bus interface. The data stored in the 32-bit byte buffer of the customer AS 1C or PCI bus interface will be transferred to the SDRAM using DMA. Step D2: VP's network interface (option for video conference) In the video conference, it is assumed that the VP will deal with it first. K executes V. 34 or 1.400 0 serial network interface example . VP will write the result to SDRAM 0. Step D3: Demultiplexing and start code analysis of ARM7 by ARM7 will move the data in SDRAH to ARM7 physical cache memory and execute A / V Demultiplexing of Bit Streams. For the video bit stream, ARM7 is also responsible for finding all the start codes and parsing headers (starting codes, headers) with M until a cut or G 0 B is detected. The decoded bit stream syntax parameters can be stored in a specific area of the SDRAM through AβM7 ·. Audio and video bit stream transmission after demultiplexing -1 90- ^ ί I, ί. 1ΐ > — II I- J-. Ttf E ti m tn I ^^^^ 1 ^^^^ 1 -1-J ^^^^ 1 ^^^^ 1 ^^^^ 1 ^^^^ 1 ^^^ 1 * {Please read the precautions on the back before filling this page) This paper standard is in accordance with the Chinese National Standard ( CNS) A4 specification (210X 297 mm) 43671 〇 Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (Α-ι ^) 1 1 Each rate buffer 〇 Each application may have a rate For example, 1 for Q1 and Q for different sizes, and 1 for video rate. Sr size MPEC -1] 1 I proposes 37 0K bits t and MPEG -2 MP @ Μ L is 1. 8 3 5 M bits 〇Please kj 1 1 Step D4: JS is initialized by the BP of ARH7 to read back 1 | Except for the first register, which is used for the number of macro blocks to be encoded, it is not 1 [except for this step. The procedure is the same as step E4 in the previous section. Consent 1 1 Ground, this initialization should not be performed after the power-on reset signal is announced. Fill in the I 1 cycle and write it to 128. 0 Page 1 Step Of): Μ is processed by the bit stream of BP 1 1 in After initializing the BP used for a specific cut or G0B, the rest of the 1 1 data to be decompressed is transmitted to the input Shuangyuan puncher. The BP is responsible for the M data acquisition through 1 order I | 10 bus check all flags The state of the target ° BP must parse the grammatical parameters, whether to include the word group in turn. If BP recognizes that the next bit is 11 Huffman codes, it is more than four cycles for each Huffman code in a limb Perform 1 1 Huffman decoding. 0 If the Huffman is not used for DCT AC coefficients, the result of the Huff 1 traveler decoding is 8LC decoding to produce 64 circle components. The heavy 1 I circle after construction. Reverse dentate The conversion and the last fu sent to the output double-bit 1 1 I device K allows the VP to perform “vectorization” 0 ΒΡ 懕 continue processing until detection-~ L 1 1 non-cutting or non-G0B start code = if detected .BP must use K for the byte and bit position information of 1 i last data to interrupt ARMV 1 and terminate at 1 i 0 ARM7 懕 then look for the next cut or G0B start code * and repeat here 1 I Principle 0 1 1 I Step ηβ: VP information solution shrinking 1 1-19 1-! I This paper music standard is applicable to the national standard (CNS) A4 specification (2) ο × 297 public money) The consumption of shellfish by the Central Standards Bureau of the Ministry of Economic Affairs Cooperative cooperative print 43671 Q λ _ ^ __ V. Description of the invention (/ νι is the result of borrowing step D5. The VP should perform inverse quantization, inverse DCT, K, and image reconstruction using motion vectors. After decoding is completed, the VP will store the result in SDRAM. Step D7: Post-VP processing Before the video and audio data are finally transmitted to the digital-to-analog converter * these pixels will be processed by VP to obtain the desired output resolution and image quality. This result will be stored in SDRAM again. Step D8: Send unprocessed A / V data. Finally, the reconstructed audio and video data in SDRAM will be output using DMA. At the same time, this kind of data movement should be started by ARM7. Since the recent video overlay technology allows the PCI bus to send video source data, this last unprocessed data will be sent to the customer ASIC or PCI bus interface. 10.7 Box type 10.1. A certain RP companion address BP has the following 32-bit basic component address: < HSP_BASEXBP_BASEXAddress_Offset > where < in 3? _843 £ > is a 5-bit, which is composed of MSP The basic PCI component address designation: < BP_BASE > is 7 bits, which is equivalent to 7'blllll00; and < Address_OffsetM is 20 bits, which specifies the BP internal register. -192- --------- ^ ------? Τ ------. ^ (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) Α4 specification (210X297 mm) ο B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (A-yang) Therefore, in the entire MSP I / O component address mapping, The address range is from 27'h 7CO_fl00〇 to 27, h 7CF_FFPF 10.7.2. 2 Internal memory description The internal register settings are described in Table 24. All registers listed in Listing 24 can be accessed and written by ARM 7 or VP. (Please read the precautions on the back and fill in this page first) »List 2 4: BP internal register address_offset (Hex) ----- Register name size description 0_0000 BP_M0DE [31: 0] 32 BP processing mode register 0_0004 BP.C0NTH0L [31: 0) 32 BP control register 0_0008 IBUF0_START [3 1: 0] 32 Enter the start address of the element buffer G 0 0 0 0 0 CI BUFO — END [ 31: 0] 32 Enter the end address of the punch 0. 0_00! 0 IBUF1_START [31: 0] -1 9 3- 3 2 Enter the start address of the punch 1. The paper size is applicable to the Chinese national standard ( CNS) A4 specification (210X297 mm) 43671 Ο, .. — **** V. Description of the invention (A-ι) Called by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperation Du printed 0_00 14 I8UF1_END [31: 0] 32 Enter the end address of the punch 1 ------------ 0.0018 〇 BUFO_START [31: 0] 32 Start address of the output buffer 0 0.001C OBUF0_END [31; 0 ] 32 rounds end of punch 0 0,0020 0BUF1_START [31: 0] 32 start address of output punch 1 0_0024 OBUF1_END [31: 0] 3 2 output end of punch 1 0_0028 SAVE_ADR [31; D] 32 This text stores the start bit 0 _ 0 0 2 C VALID_BYTE_ADR [31: 0] 32 Byte address for the last data of the line input or output dual element punch -194- This paper standard is generally Chinese National Standard (CNS) Α4 specification (210 × 297 mm) --------------- IT ------. ^ (Please read the notes on the back before filling out this page) 4367 1 Ο ^ Μ-5 、 Explanation of the invention (Α- 咖啡) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 0,0014 I BUF1.END f 31: 0] 32 Enter the end address of the yuan punch 1 0 _0 0 1 8 〇 BUF0_START [31: 0] 32 Output start address of the output device G o_ooic 〇BUF0_END [31; 0] 32 Output end address of the output buffer 0 0_0020 0BUF1 „START [31: 0] 32 Output start address of the output device 1 0_0024 0BUF1_END [31: 0] 32 End address of output buffer 1 0_0028 SAVE_ADR [31: 0] 32 This file stores the start address 0_002C VALID „BYTE_ADR [31: 0] -194- 3 2 For line input or output The byte address of the last data of the double buffer The paper size conforms to the Chinese National Standard (CNS) A4 specification (210X 297 mm) --------- ^ ------ IT-- ---- ^ (Please read the note on the back first (Please fill in this page again for the matters needing attention) 43 67 1 〇 Α7 τη Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (Α 也) 0_0030 BP_STATUS [0] 1 The lowest significant bit of the BP status register 0.0031 B P_STAT US [1] 1 low significant bit 0.004E BP_STATUS [30] 1 high significant bit 0_004F BP_STATUS [3 1] 1 Most significant bit of BP status register 0.0050 BP_STATUS [3 1: 0] 32 BP status Register 0_ 0 0 5 4 BP_INT_MASK [15: 0] 32 BP interrupt mask temporarily stores I ZE [7: 0] register and M macro block H_MB_SIZE [7: 〇] The number of images vertical and horizontal size 0_0058 ARM7_IRQ [0] 1 ARM7 interrupt request pin 0_0059 Reserved for future use---Expansion 0,005F -195- ----------------------- ΐτ ------ ^ (Please read the precautions on the back before filling this page) This paper size applies to the national standards of the poor countries < CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ___ B7 Explain Oa-Roar)

0_ 0 0 6 0 0_〇19F BP_CACHE [Address] 8 BP high-speed rush to record the body area 0_0 1 AO Reserved for future use---Expand F_FFFF • BP_M0DE [31: 0] (Setting value) —This register is used to represent the standard video format and various image hierarchy information. Details can be found in section 10 · 8.1. • BP_C0NTR0L [31: G] (read / write, default value is "32'h0000 _0 00 0")-This register contains various control parameters for BP operation. ARM 7 or VP will set false flags in this register, and some flags are reset by B P. The bit description is found in section 10.8.2. IBUF0_START [31: 0] (read / write, no default value)-This register is initialized by ARM7, and M indicates the starting address of the input buffer G for the BP input double-element punch. Note * The initialization value used for IBUFQ_START should always be less than IBUFO_END, and IBUF0_START [3: 〇] should be equal to 4 ′ b 0 0 0 0. Usage is described in section 10.1 11. • IBUF0_END [31: 0] (for read only • no missing value)-This register is used to indicate the end address of input buffer 0 for the BP double buffer. Usage is described in section 10.11. -196- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) --------- 1 ------ ΪΤ ------ ^ (Please read Beinan first Note for re-filling ^ • this I) Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs 4367 1 0 ^ at __ Β7__ V. Description of the Invention (Α-⑺) • IBUF1_START [31: 0] (Read / Write , There is no missing value)-This register is initialized by ARM7, K indicates the starting address of input element 1 for BP input double element element. Note that the initialization value used for IBUF1_START should always be less than I Β ϋ F 1 _ E N D, and I B U F 1 _ S T A R T [3: 〇] should be equal to 4 ′ b Q Q Q 0. Usage is described in section 10.11. • IBUF1_END [31: 0] (only for capture, no missing value)-This register is M to indicate the end address of input element 1 for the BP input double element element. The usage is described in section 10.11. OBUFO_START [3 1: 0] (capture / write, no missing value)-This register is initialized by ARM 7. Use M to indicate the start of output element 0 for BP output double buffer. Address. Note that the initial value used for 〇BUFQ_START should always be less than 〇BUF0_END, and 〇BUFQ_START [3: 0] should be equal to 4 ′ b 0 0 0 0. Usage is described in section 10.1 11. • 0BUF0_END [31: 0] (only for capture, no missing value) —This register is used to indicate the end address of output buffer 0 for the BP output double buffer. Usage is described in section 10.11. • 0BUF1_START [31: 0] (get / write, no missing value)-This register is initialized by ARM7, and it is used to indicate the start position of output M punch 1 for the BP output dual element punch. site. Note * The initialization value used for 0BUF1_START is always less than 〇ΒϋΡ1_ΕΟ, and 〇BUFl_START [3: 0] should be equal to 4 ′ b 0 0 0 0. The usage is described in 1 (ϊ. 1 1 sub-section. • 0BUF1_END [3 1: 0] (read only, no missing value)-this register is used as M to indicate the output element title for the BP output double buffer. The end of the device 1 -1 97- This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297). --------- Installation ----- 1T ------ d (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 43 67 1 Ο ^ Α7 __________ Β7 V. Description of the Invention (Α-⑽ Address. Usage is described in 1 0 Section 11. • SAVE_ADR [31: 0] (for praise only, no missing value)-This register is M to indicate that SDRAM wants to store the starting address of the internal BP text. When the request is a prefetch text switch In the formula mode, some related instructions can be found in section 1 0. 1 2. 1. • VALID_BYTE_ADR [31: 0I (capture / write, no missing value)-this register is indicated by K in the case of deblocking. Rotate the last valid data byte position of the double-yuan punch * or the last valid selling byte position of the output double buffer in the coded shape. This register is used for Working signal exchange between ARM 7 and BP. In general, there is a need for additional information on the effective bit position of the valid byte data, which is included in the BP_CONTROL [31: Q] register. Details Can be seen in section 10.13 ° • BP_STATUS [3 1: 0] (capture / write, the default value is w32'hQ000 -0000 ”)-this register uses M to represent various internal states of BP. In the lower two Each bit position of a byte (ie BP_STATUS [15: 0]) is an interrupt condition * which can set ARM7_IRQ to κ 1 ”. This register can be accessed in two ways. ARM 7 or VP Can read or write the entire 32-bit register using address 27'h7C0_005f. However, in general, ARM7 and VP would rather write (or reset) this BP_STATUS register bit by bit The contents of the register. By specifying the range of each bit of BP_STAT [JS from 27'h 7CO_0 0 3 0 to 27'ii 7C0_O04F. The detailed bit description can be found in section 10.8.3. -198- This paper size is applicable to China National Standards (CNS) A4 grid (2! 〇Χ297 公 嫠) --------- ^ ------ 1T ------ - (Please read the back of the precautions to fill out this page) Ministry of Economic Affairs Bureau of Standards employees consumer cooperatives printed ___ -_ B7__ V. description of the invention (A-w)

• BP-I NT_HASK [15: 0] (for performance only, the default value is “16hFFFF”) — each bit in this register corresponds to one of the given by BP_STATUS [15: G] 涸Interruption condition, and the condition before the person being carried in BP_STATUS [15: 0] is "AND". If a mask bit is set to "0", the corresponding interrupt condition is set unconditionally to rtQ "(that is, disabled). Details of this interrupt can be found in section 10.9. • V_MB —SIZE [7 : 0] (read only, no default value)-This register is used to indicate the vertical size of the image to be encoded or decoded. Please note that 'this value must be described by the number of macroblocks. For example, if the vertical size is 288 pels, 7_pay 8_312 £ [7: 0] = 288/16 = 13. ARM7 is responsible for setting the fc value before each start of the BP encoding or decoding job. • H_MB_SIZEn : 〇l (only for capture, no missing value)-This register is used to indicate the horizontal size of the image to be encoded or decoded. It should be noted that this value must be described by the number of M macro blocks. For example * if the horizontal size is 352? 613 * then 11 _ ^^ _ 312 £ [7: 0] = 352/16 = 22. 609 is responsible for setting this before each start of the BP encoding or decoding job. Value. _ ARM7_IRQ [0] (only for writer, the default value is "")-this register is a 1-bit flag to request interrupt to ARM7, and is directly connected to output port A RM7_IKQ. If any bit of BP_STATUS [15: 0j is set to "1", this flag will be set. ARM 7 is responsible for resetting this flag with M. 10.8 RP T / Π tremolo block format -199- This paper size applies to the Chinese national standard (CNS Μ4 specification '(2ΙΟ × 297 mm) --------- ^ ----- ^-, π ------ ^ (Please read the notes on the back before filling out this page) A7 B7 5 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ 43671〇 Invention Description (Α ^.) This section contains M for BP input and output command data and macro block data block format. 10 · 8.. 32-bit BP_M0DE register at 27'h7CQ_Q0QQ temporarily stored in IBP M0nF register. Listed in list 25. Note: BP_M0DE [31]: PARAM_SET2 [7] 'and BP_MODE [〇]: SF [0]. List 25 BP_M0DE register format bytes / bits 7 6 5 4 3 2 1 0 bytes 0 PS PT-SF Byte 1 PARAM_SE T 0 Byte 2 PARAM_SET1 Byte 3 PARAM.SET2 _standard_friat (SF · naked standard format)-The video standard to be used * It is defined in list 26. SF It should always be specified by ARM 7 before the BP system is enabled for all video encoding and decoding operations. Listing 26 Definition of SF This paper size applies the Chinese National Standard (CNS) A4 specification (2 0X297 mm) --------- install ------ tx ------- 1-.41 < Please read the precautions on the back before filling this page) 4367 1 Ο ^ λ7 Β7 V. Description of the invention M-bl) Consumption cooperation between employees of the Central Bureau of Standards of the Ministry of Economic Affairs and printing of bytes [2: 0] Standard format 3 1000 MPEG-1 video encoding 3 'b00 1 MPEG-1 video decoding 3, b0 1 0 MPEG-2 video encoding 3 * b0 11 MPEG-2 video decoding 3, blOO H. 261 encoding 3, b 1 0 1 H. 261 decoding 3, b 1 1 0 2 6 3 encoding 3, bl 1 1 Η 2 6 3 decoding • picture_type (PT, picture type)-a picture coding type * which is defined in the list 2 7. Note * The value Q 0 for P T means a specific situation for Ji P E G -1, M PEG-2, and Η.263 applications. In particular, D image is designated as an image type for HPEG-2, although D image-2 0 1-This paper size applies to the Chinese national standard (CNS} A4 specification (210X297 mm) --- ------ ¾ .------ tT ---------- line (please read the notes on the back before filling this page) 43 67 1 Ο 4 α7 Β7 (Β0 丨) Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs [2: G] Standard format 3 1000 Μ PEG-1 video encoding 3 'b00 1 MPEG-1 video decoding 3, b0 10 MPEG-2 video Encoding 3, bO 11 MPEG-2 video decoding 3, b 1 0 0 Η. 261 encoding 3 'b 1 0 1 Η. 2 6 1 decoding 3, b 11 0 Η. 2 6 3 encoding 3 5 b 11 1 Η. 2 6 3 Decoding --------- Approval ----- 1T --------- Line (please read the precautions on the back of Jing before filling this page) _ Pictur > e_type (PT, picture type)-Picture coding type, which is guaranteed to be defined in list 27. Note • The value of 00 for PT means specific situations for MPEG-1, M PEG-2, and Η · 263 applications .Specifically, D-picture is designated as an image type for MPEG-2, although D-picture 2 0 1 μ Paper size applies Chinese National Standards (CNS) M specifications (210X297 mm) 5 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and printed by Aigong Consumer Cooperative A7 B7 Invention Description w2e2) The image will not be used in MPEG-2. This is because MPEG- 1-bit stream is MPEG-2-bit stream-a collection of pictures. List 27 Defined Bytes of PT [5: 4] MPEG-1 MPEG-2 H.261 H.263 2 * b00 D picture D picture Like Illegal PB data segment 2, b01 intra (intra) illegal intra (intra) 2 'blO predictive predictive always mutual (inter) 2, bll two-way two-way illegal illegal • picture_structur e (PS, image structure) -Image structure information * which is defined in the list 2 8. Similarly, the value 0Q of ρ τ is illegal and causes an error. List 2 8 Definition bytes of PS [7: 6] MPEG-1 MPEG-2 H.261 H'263-2 0 2-The standard of this paper is applicable to China National Standard (CNS) A4 (2iOX29? Mm) --------- t .--- --- 、 Order ------ 2 < Please read the note on the back before filling in this page) 6 3 ο

V. Description of the Invention uM 2'b00 Illegal Illegal Illegal Illegal 2, b01 Illegal Top Illegal Illegal Illegal 2, blO Illegal Bottom Illegal Illegal Illegal 2 'bll Information Section Information Section Information Section Responsible Section -------- -^-(Please read the notes on the back before filling this page). Parameter _ set (Parameter setting) 0, 1, and 2 (PARA Μ _ SET 0, PARAM_SET1, PARAM_SET2)-these three sisters M is used to represent various parameters required for MPEG-1, MP £ G-2, and Η. 2 6 3 applications. The definitions used for each parameter setting are described in Listings 29 and 30. Listing 2 9 Definition of PARAM_SETO, ^ 1 Bytes / bits printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 7 6 5 4 3 2 1 0 Bytes 1 VSF AS IVF CMV FPFD TFF IDP CPM AP-2 0 3-.. The paper size of the paper is applicable to China National Standards (CNS) Α4 (210 X 297 mm) Central Printing Bureau of the Ministry of Economic Affairs, Shellfish Consumption Cooperation Du printed by u 4367 1 0, D / V. Description of the invention intra_dc_precision (IDP) — dc accuracy parameter in 2 bits, pseudo-defined in M PEG-2 'if set to 00 in MPEG-1 applications. .top_f ield_first (TFF)-A flag for MP E G-2 used for motion vector encoding and decoding. .frame — pred-fr'affle-dct (FPFD) — A flag used for MPEG-2. Use M to indicate that frame DCT and information segment prediction are used. • cοncea 1ment_motion_vect〇rs (CMV) (hidden motion vector) or advanced_prediction_mode (AP) (advanced prediction mode)-This flag is used in the MPEG-2 system to indicate that the motion vector is used in the macro block. This flag is set to 1 when H_263 is used to perform advanced prediction mode, otherwise it should be set to 0. For other standards, this flag should be set to zero. • intra_vlc_forEat (IVF)-a flag for MPEG-2. Use M to determine the type of VLC list for the intra-macro block. • alternate_scan (AS) —A flag for M PEG-2. Use K to determine the order of the coefficients to be encoded and decoded. • ν ertica 1 _ siz e_ f 1 ag (VSF) (vertical size flag) or continuous_presence_multipoint (CPM)-in MPEG-1 and MPEG-2, when the vertical size of the image exceeds 2800 lines , This flag is set to 1, otherwise it should be set to 0. Yu Η. 2 6 3 · When the multi-drop mode is used, this flag is set to 1, otherwise it should be set to 0 〇List 3 0 Definition of PARAM „SET1 and PARAM_SET2 -204- This paper size applies Order Country National Standard (CNS) A4 Specification (210X29? Mm) --------- t .------ IT ------ Travel (Please read the notes on the back before filling (This page) 43671 Ο ^ V. Description of the invention Α7 Β7 MPEG-1 bit / bit 7 6 5 4 3 2 1 0 Byte 2 Reserved full_pel, forward_vector forward_f_code Byte 3 Reserved full_pel_backward_vector backward_f_code HPEG-2 bit Group / Bit 7 6 5 4 3 1 2 1 0 Byte 2 forward „vertical_f_code forward_horizontal_f_code Byte 3 backward_vertical 丄 code 1 backward_horizontal_f_code 10-8-2 RP [flNTROI.Register 暂 ------ --- Equipment-- (Please read the notes on the back before filling in this education) 丨 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Online Economics 7CO_0004) The bit description is shown in list 31. List 3 1 BP_C0MTR0L register format-2 0 5-This paper size applies to the national solid standard (CNS M4 specification (210X297 mm) OH e 3 '<Γ w

7 7 AB Printed bit / location flag name read / write description by male labor consumer cooperative of Central Standard Bureau of Ministry of Economic Affairs 0 BP_EN R / W BP processing enable I SOFT_RESET R BP software reset 2 PAUSE R BP processing freeze 3 DETECT, START_CODE R Detect the next start code 4 STEP R BP step horizontal processing 5 CTX_SWITCH R Request to switch the text 6 CTX_M0DE R Switch to the text mode 7 CTX_RELOAD R Request to reload the text 8 ERR_HAiNDLE_MODE R Error processing mode 9- Reserve -20 6- --------- install-(Please read the precautions on the back before filling in this purchase)

, 1T This paper size applies to Chinese national standards (CNS &gt; Λ4 size (2 丨 0X297 mm) 4367 1 05. Description of the invention Α7 Β7 UM) The Central Standards Bureau of the Ministry of Economic Affairs is responsible for work and consumer cooperation. Du Yin 10I 15 16I 3 1-Reserved S〇_MBS (0) No. of MB_ (S) macro blocks to be encoded in the current cut or-R GOB • BP-enable (ΒΡ_ΕΝ)-when this flag is set by When ARM7 or VP is set to "1", BP starts processing. Therefore, all other register configurations should be made before this flag is set. If BP finishes processing, this flag is cleared by BP. • software_reset (SOFT_RESET)-When this flag is set to "1» by ARM7 or VP, BP stops the current processing and returns all internal registers to the default state * and enters the state of hearing. By setting BP_EN flag * ARM7 can restart BP processing. The BP hardware reset signal is a low-level action. • pause (PAUSE)-When this flag is set to "1" by ARM7 or VP, BP freezes the current Process execution. By setting the BP_EN flag, the user can resume a suspended operation. , Detect _ start _ c 〇de (DETECT _ START _ C (3 DE)-when this flag-2 0 7-This paper size applies to China National Standard (CNS) A4 specifications (210x297 mm) Binding Travel (please Please read the notes on the back before filling this page) Printed by the Central Consumers' Bureau of the Ministry of Economic Affairs, Printed by Consumers Cooperatives 4367 1 〇 Α7 * Β7__ 5. Description of the invention ΑZO〇ϊ) When set to "1" by ARM 7 or VP , BP looks for the next start code between the data in I BUFO. Therefore, the user should set the appropriate addresses for IBUFO_SrAET and IB (JF0_EHD. It must be that this command will only work properly when BP is in an idle state. Therefore, if BP is not inter- Before sending this command, ARM 7 should send a software reset command to BP. .Step (STEP)-When this flag is set to "" by ARM? Or VP, BP will advance to the current state of processing execution ~ . This is a very useful feature for debugging. ARM7 should first send a pause command K to enable this step. .Context_switching_r * equest (CTX_SWITCH)-When this flag is set by ARM7 " 1 ”, BP performs prefetch or cooperative text switching based on the content of CTX_M0DE. Details can be found in section 1 2 · 0 • context_switching_mode (CTX_M0DE) —When this flag is set by ARM7 or VPM, CTX_StfITCH is set to" 1 " Set to "1" * BP executes pre-fetch text switching mode® if it sets CrX_StfITCH to "1" and sets it to "0" · BP executes collaborative text switching mode. Note that if CTX_SWITCH is not set to "1" ' The CTX The _M0DE setting will not affect the BP processing. Details of the switch in this article can be found in section 10.12. • context_reload_request (CTX_REL〇AD) —When this flag is set to "1" by ARM7 or VP, BP reloads people The text previously stored in SDRAM. BP is responsible for obtaining the text stored by the address SAVE_ADR [31: 0]. The details of the switching of this text can be found in section 10.12. -2 0 8 * This paper size is applicable to the country of China 榇Standard (CNS) A4 (210X297) ---- --------- ^ ------, ιτ ------- ^ (Please read the notice on the back before filling in this I ) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ 4367 1 〇A7 &gt; B7 V. Description of the invention • err〇i * _handle_mode (ERR_HANDLE_MODE)-This flag is used to promote when an error occurs when transmitting the compressed bit stream BP's error recovery procedure. When the incoming bit stream has invalid data, BP must interrupt ARM 7 and check the content of this flag. When this flag is set to "1", BP automatically looks for the next start Start code. If the start code is used for a cut or GOB, BP resumes processing. When this bit is set to "0 When, B P must fall into the idle state without looking for the next start code. The details of the job hand-shaking between BP and ARM7 are described in section 1 0. 13 ° nufflber_of_niacroblocks_to_be_encoded (NO_MBS [15: 0])-this register includes 16-bit unsigned An integer indicating the number of macroblocks to be truncated or encoded by GOB. With this bit resolution, up to 6 5 5 3 5 macroblocks can be encoded in one cut or GOB. Here, the value "0" is not allowed as a number of macro blocks. 10.8.3 RP Chess B P _ S T A T U S [3 1: 0 I register (address 2 7 ′ h 7 C 0-0 ί) 5 0) The bit description is shown in list 32. List 3 2 BP_STATUS register format bit / position flag name read / write description -209- This paper size is applicable to China National Standards (CNS) Λ4 specification (210X2S7 Publication &gt; ------- --- (Please read the notes on the back before filling this page)

11T 6 3 4 ο 5. The description of the invention is called printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. IBUF0_D0NE V IBUFO empty 1 IBUF1_D0SE w IBUF1 empty 2 OBUFO_FULL w OBUFO full 3 0BUF1_FULL w 0BUF1 full 4 BP—DONE w BP processing completed 5 CTX_SW_DONE V Ready to switch to this document 6 CTX_REL0AD_D0NE w This document is reloaded and completed 7 —-Reserved 8 BP JRR w BP error condition 9 i Reserved 15 16 IBUF0_FULL R / W BP input buffer 0 full paper size applicable to China Standard (CNS) A4 specification (210'X 297 mm) -210- (Please read the precautions on the back before filling out this page), -fl Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy B 43 6 ^ 1 0 ^ at ____1 Β7-— V. Description of the invention (shirt ... 17-), IBUF1_FULL R / W BP round-in punch I full 18 OBUFl_DONE R / W BP output buffer Q empty 19 OBUFl_DONE R / W BP output balancer 1 empty 2 0 VALID_BIT_P0S [2; 0] R / W Bit 2 2 position between the data stored in VALID_BYTE 1 _ADR, which will start the next processing 2 3 —-Reserved 2 4 1 BP_ERR_CODE [7: 0] W BP error code 3 1 • in put_buffer_0_done (IBUFO_DONE) _ — Flags The material used to notify the input device Μ with M is used up by BP. This flag is set by BP and cleared by ARM 7 or VP. Note 'This flag The standard is an interruption condition. -2 11- This paper size applies to the Chinese National Standard (CNS) Α4 specifications &lt; 2〗 〇 × ^ 7 公 楚) --------- ache ------------ τ ------- ^ (Please read the note on the back ^ before filling this page)

The Central Standards Bureau of the Ministry of Economic Affairs—Industrial and Consumer Cooperatives Printed Together 5. Invention Description (Mli)

• input.buffer_l_done (IBUFl.DONE)-a flag that uses M to inform the input buffer 1 that all data is used up by BP. This flag is set by BP and cleared by ARM7 or VP. Note that this flag is an interrupt condition. • 〇utput_buffer_0_ful1 (OBUFO-FULL) —a flag to notify the output element that 0 is filled by BP. This flag is set by BP and cleared by ARM 7 or VP. Note that this flag is an interrupt condition. output.buf er_l_full (OBUFl ^ FULL)-This flag is used to notify that the output buffer 1 is filled by BP. This flag is set by BP * and cleared by ARM 7 or VP. Note that this flag is an interrupt condition. • B P_p r 〇 es si ng_ done (BP_D0NE)-a flag to notify BP that K has completed encoding a cut or GOB, or that a non-cut or non-GOB start has been detected in the decoding situation code. This flag is set by BP and cleared by ARM7 or VP. Note that this flag is a neutral condition. • context_switching_done (CTX_SW_DONE)-a flag that informs the BP system that it is ready to switch to another task in this article's switching mode. This flag is set by BP. It is cleared by ARM7 or VP. Note that this flag is an interrupt condition. .context_reload_done (CTX_RELOAD — DONE) — ~ flags, K is used to notify BP that the reload operation for the text stored by address SAVE_AM [31: 0] has been completed. This flag is set by BP and cleared by ARM 7 or VP. Note that this flag is an interrupt condition. • BP_error_f lag (BP_ERR)-a flag to notify the processing-2 12- This paper size applies to China National Standard (CNS) A4 (210 &gt; 097 mm) Read the notes on the reverse side and fill in this page) Order a Printed by the Ministry of Economic Affairs and the Central Standards Bureau, Printed by the Consumers Cooperatives 4 3 6 7 1 〇α7 ___ * __ Β7_ V. Description of the invention 丨 &gt;) An error occurred in the BP data . This flag is set when BP_EliR_C0DE [7: in (= BP_STATUS [31:24]) is not equal to zero. Details can be found in section 10 · 9.2. • input.buffer_0_ful 1 (IBUFO.FULL) —a flag that indicates that the data in the input buffer 0 is filled by ARM 7 or VP. This flag is set by ARM7 or VP and cleared by BP. • input.buffer_l_ful 1 (IBUF1_FULL)-A flag indicating that the data in the turn-in punch 1 is filled by ARM 7 or VP. This flag is set by AKM7 or VP and cleared by BP. • output_buffer_0_done (0BUF0_D0NE) — — flags • Used to indicate that the data in the output element buffer 0 is used up by ARM 7 or VP. This flag is set by AKM7 or VP and cleared by BP. • output_buffer * _l_done (0BUF1_D0NE) — a flag ‘M 'indicates that the tribute materials in round-out buffer 1 are all used up by ARM 7 or VP. This flag is set by ARM7 or VP * and cleared by BP. • valid_bit_position (VALID_BIT_P0S [2: 0]) — — 3-bit information. Use M to indicate the valid bit position between the data bytes stored in VALIDjYTE_ADR [31: 0]. • For the next processing. This value must be set during video coding ’Bp, and ARM7 懕 starts the next processing from this bit position. During video decoding * ARM7 must set this value to 1 and BP should start processing at this bit address. • BP_error_code (BP_ERR_CODE [7: 0]) — 8-bit information. Use M to notify what kind of error occurred in it. A zero value means that no error occurred. -213- This paper size is applicable to China National Standards (CNS) A4 (2l0XW7mm) ^ '1τ ------- line (Please read the notes on the back before filling this page) Central Ministry of Economic Affairs Standards Bureau Consumers' Cooperatives ¥ «. 4367 1 Ο Α7 ^ __ 5. Details of the invention description can be found in section 1.0 * 2 *. 10-8.4 The rounding data format used for decoding Ling is used for code format and output data format In this case, the data actually contains the compressed bit stream. The data may include the start code, header parameters, and the collapsed data according to the corresponding criteria. This bit stream is packed in bytes one by one. However, in some applications, it is not necessary to perform byte positioning. Note • This bit stream can include data for several cuts or GOBs. 10-8 * 5 Used by coders to be careful and to be able to check the data in the solution. In this case, * data actually contains macro block header information, mobile data, and pixels. Coefficient Yinke. The format of the various data is defined in the following 10.8.5.1. The macro exhibition exhibits a slot and a header. The macro block header should always contain six bytes and have the following data format given in Listing 33. List 33 Macro block block format byte / bit 7 6 5 "2 1 4" This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm). I ^ II ---- -. ^. (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 6710, at B7 V. Description of the invention _ |! Γ) Byte 0 r 1 1 i 1 1 1 VM A GRNO Byte 1 ΗΜΑ MBPS Byte 2 MT DT MB MF QPI LF M4 Byte 3 Reserved Q_ SCALE Byte 4 CBP_1 CBP_0 Byte 5 Reserved CBP _ 1 Byte 6 Reserved FID LCI Bytes 7 Reserved Bytes 8 HBA_ INC -2 15- Binding. Thread (please read the precautions on the back before filling in this f) This paper size is in accordance with China National Standard {CNS) A4 specification (210X297 mm ） Ί 3 ΓΪ / 1 〇 f Α7 ___ ^ _B7 V. Description of the invention (sentence byte 9 (for output only) byte 1 0 PRE_DC ^ Y byte 11 (for output only) bit sister 12 PRE_DC_Cb Byte 1 3 (for output only) Byte 1 4 PRE.DC ^ Cr Byte 15 (only Output) (Please read the notes on the back before filling out this page) -The binding of the Central Standards Bureau of the Ministry of Economic Affairs and the Shellfish Consumer Cooperatives printed here. The parameters listed in the above list are defined after: • vertical_macroblock_address (vertical macro Block Address (VMA) or group_number (group number, GRNO)-This byte means the vertical macro block position, which can have a value from 1 to 255. Note * The first vertical position is labeled as 1 instead of 0. An exception in H.261 encoding * This broadcast I bit represents group number information, which informs the location of the block group. * Horizontal_aacroblock_address (horizontal macro area address, HMA) or Bacroblock_position (mega Set block position) _This niche means the position of the horizontal macro block * which can have a value from 1 to 255. Note | -2 16- This paper size applies to China National Standard (CNS) A4 specifications (2! OX297 (Mm) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives 43 6 ^ 1 0 a? __ [__ Β7 ___ V. Description of the Invention The first horizontal position is labeled 1 instead of 0. An exceptional shape of Η_261, this niche represents one of the 33 possible positions of the macro block between GOBs. • Bacroblock_intra (I) —If the current macro block is encoded in (t_a), set it to j :. Otherwise, it is set to zero. • nacroblock_pattern (P)-Set to 1 if the current macro block includes an encoded block. Otherwise, it is set to zero. • Bacroblock_quant (Q) —If the current macro block has a new quantization scale parameter, set it to 1. Otherwise, it is set to zero. .raacrobl〇ck_motion_forward (M F) —If the current macroblock is forward prediction, set to 1. Otherwise, it is set to 0. • maci * obl_ck_inotion_backward (MB) —If the current macroblock is backward prediction, or is included in the B block of H.263, set to 1. Otherwise, it is set to 0. • dct-type (DT), loop_filter (LF), or advanced „prediction (M4) -bit 2 [5] has different meanings in each application. Not used in MPEG-1 * This bit. In MPEG-2, it indicates dcltype. If the macro block is a bit DCT code, this flag is set to 1. If it is the information section DCT code * is set to 0. At 261 * if the loop filter The loop filter is used for the current macro block. This flag is set; otherwise, it is set to 0. In H.263, if the current macro block uses advanced prediction mode, Is set to 1; otherwise, it is set to 0. • raotion_type (MT)-This 2-bit weight indicates the -217- --------- meal for MPEG-2. 1T ------ ^ (Please read the notes on the back before filling in this page) The paper size is applicable to China National Standard (CNS) A4 (2! 0X2mm) 4367 1 〇 V. Description of invention Οκβ ) frame_motion_type (field movement type) or field_motion_type (position moving type), which has the following meanings as in Listings 34 and 35. Note that 00 values are reserved. Columns 3 4 frame_motion_type meaning code prediction type intion ^ vector ^ count inv_f or mat dmv 00 Reserved 01 Field-based 2 Unit 0 0 Fraioe-based 1 Field 0 11 Dual-prime 1 Unit 1 List 3 5 Meaning of fieid_motion_type ----------- Install-(Please read the precautions on the back before filling this page)

、 1T. 丨 The Code Prediction Type printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs niotion_vector_count mv_f orinat daiv -2 18-This paper size applies to China National Standard (CNS) Α4 specifications (210 × 297 mm) V. Description of the invention 〇4 -2if)

7 7 AB 00 Reserved 01 Field-based 1 Bit 0 10 16X8 MC 2 Bit 0 11 Dual-Prime 1 Block 1 The quantizer-scale (Q_SCALE, quantified scale) printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs An unsigned integer in the range of 1 to 31 is a scale used to determine the reconstruction level of the DCT coefficient level. Although this value is the same as the previous macroblock (gp aacroblock_quant is zero), each macroblock header should include one of the appropriate values for this parameter. The user is responsible for writing the appropriate value to this bit when encoding. At the time of decoding, the BP writes the Donghua scale value of Huffman decoding so far. If the current macro block does not include the Huffman code for this niche, BP writes the scale value of the previous macro block. • coded_bl〇ck_pattern_0 (CBP_0)-a 6-bit pattern code * is used to represent the coded block in the current macro block, where CBI &gt; _〇 [5] == &gt; brightness (Y ) 〇 Block CBP _ 〇 [4] == &gt; Brightness (Y) 1 Block CBP _ 〇 [3] == &gt; Brightness (Y) 2 Block — 219- 1 [ί &quot;; I. T &quot; '^ (Please read the notes on the back before filling this page) This paper size is applicable to China National Standards (CNS &gt; A4 size (210x297 mm) A7 Printed by the Consumers' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs 436 ^ 1 〇, V. Description of the invention (ten called CBP-0 [2] == &gt; Brightness (Y) 3 Block CBP_0 [1] == &gt; Chroma Blue (cb) Block CBP_G [0] = = &gt; Chroma Red (Cr) block • coded_bloc_pattern_l (CBP_1)-additional coded_block_pattern (coded block form) for the BP information segment B block in H.263 applications, where CBP_1 [51 == &gt; Brightness (Y) 0 area CBP_1 [4] == &gt; Brightness (Y) 1 block CBP_1 [3] == &gt; Brightness (Y) 2 Block CBP_1 [2 I == &gt; Brightness (Y ) 3 blocks CBP-1 [1] == &gt; Chroma Blue (cb) CBP_1 [0] == &gt; Chroma Red (Cr) block • 1 〇gica 1 _ cha η ne 1 _ indicat 〇r (LCI, logical channel indicator)-2 bits for GOB logical channel number Information is only used for continuous multipoint mode of Η.263. • frame_id (FID)-涸 2-bit information. For GOB information segment 10, it is used for H. 2 6 3. • macr 〇b 1 〇ck _ address — increment (Μ BA _ INC, macro block address increment)-a 2-byte information of the incremental value of the macro block address of the current macro block. This information is always provided by BP Provided as additional information 'so the user does not need to set the input format. Any value * specified in the input macro block header block will be ignored by BP. • Previ〇us_dc_1uminance (PRE_βC_Y, previous dc brightness) '-2 2 0-ti clothing ~ I * I ^ I f' i '(Please read the precautions on the back before filling out this page) This paper uses the Chinese national standard {CNS) A4 size (210X 297) } Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 436 ^ 1 0 ^ α7 __ 4 Β7-~ 丨 丨-_ _-_ 5. Description of the invention (/ 1-22 丨) 2 bytes of information, (^ value for the chroma block of the previous macro block). If there is a skipped macro block, a reset value will be issued. This responsibility is always provided by BP as additional information, so the user does not need to set the input format. Any value specified in the Rose Header Group of the input macro area will be ignored by BP. 'previ 〇us _ dc _ chr 〇minance _ b 1 ue (PRE _ DC _ C b, previous dc chroma blue)-a 2-byte information for the blueness block of the previous macro block dc value. If there is a skipped macro block, a reset value occurs. This information is always provided by BP as additional information | so users do not need to set it in the input format. Any value specified in the input macro block header block will be ignored by BP. * previ〇us_dc_chr〇fflinance_red (PRE_DC_Cr, previous dc chromaticity red)-a 2-byte information, for the dc value of the redness block of the previous macro block. If there is a macro block that jumps, a reset value is issued. This newsletter is always provided by BP as additional information, so users do not need to set it in the input format. Any value specified in the input macro block header block will be ignored by B P. 1 0 · 8 · 5 · 2 way Portuguese 1 W material word 驵 If the macro block includes a motion vector, the header of each macro block should have an additional 字 word group. First, consider the case of MP PEG-1 and MP PEG-2. When one of the following situations occurs, these standards will have the additional header block format shown in Listing 36 for the motion vector: -22 1- This paper standard applies to China National Standards (CNS) A4 Specifications (2 丨 0X29? Mm) --------- ¾ ------ ir ------ ^ (Please read the precautions on the back before filling this page) 43671 Ο a Five Description of the invention U-Kunqian 1) When MF = 1 or (1 = 1 and CMV = 1) Case 2) When MB = 1 Printed list of the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3 6 For MPEG- 1 General motion vector data format with MPEG-2 Bytes / Bits 7 6 5 4 3 2 1 0 Bytes 0 First forward movement to the horizontal component FSO Byte 1 Byte 2 First Front Directional motion vector vertical component byte 3 bit sister 4 First backward motion vector horizontal component FS1 byte 5 byte 6 First backward motion vector vertical component byte 7 Pack ------ -Order ------- i (Please read the notes on the back before filling this page) This paper size applies to Chinese national standard (CNS 丨 A4 specification U10X297 mm) 4 3 6/1 Ο 4 Α7 _________ Β7 Invention description Q Bytes 8 Second forward motion vector horizontal component FS2 Byte 9 Byte 10 Second forward motion vector vertical component Byte 11 Byte 12 Second backward motion vector horizontal component FS3 Byte 13 bytes 14 Second component of the backward motion vector vertical component bytes 15 --------- ^ ------ 1Τ ------ ^ (Please read the precautions on the back before (Fill in this page) The Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs is printed in the list 36. All the component values are half-pel accuracy. F S 0, F S 1, F S 2, and F S 3 are all 1-bit flags, and K is used to inform the selection of the unit position for each motion vector. If no bit selection is present, the flag should be set to zero. Since MPEG-1 does not use bits to retrieve information, such information should be set to zero. -2 2 3-This paper uses Chinese National Standards (CNS) Λ4 specifications (210 乂 297 mm), Central Standards Bureau, Ministry of Economic Affairs, Industrial Cooperatives, Cooperative Indy 4 3 6/10,-A7 B7 V. Description of the invention U-2W) An exceptional case occurs when HPEG-2 encoding a dua prime motion vector. In this case, the forward motion vector contains 16 bit-sisters (8-bit bytes are used by the buttercup), and the format should be as shown in Listing 3?. Normally, when video coding is applied, B P converts the motion vector value to a differential value. However, the motion vector components in Listing 37 should be differential values, which are the actual inputs of the Huffman encoder. In MPG-2 decoding applications, these dual primary motion vectors are controlled by BP. Listing 3 7 Motion vector data format for dual primary mode for MPEG-2 encoding

Bit sister \ bit 7 6 5 4 3 2 1 0 Byte 0 Horizontal component of forward motion vector 1 Byte 2 Vertical component of forward motion vector 3 Byte 4 Unused DM- 2 2 4-This paper size is applicable to China National Standard (CNS) A4 specification (210X297). --------- Shen Yi --------, 玎 ------ line (please first Read the notes on the back and fill in this page) 43671〇 * 'A7 _____________ B7 V. Description of the invention (4-1 $ Byte 5 &quot; ----- Byte 6 Unused D Μ V _ v —' '' --- Bytes 7 Bytes 8-1 5 Reserved Η · 261 and H.263 will have slightly different motion vector data cells. Most importantly, a single byte will be sufficient for any The value of the motion component. Depending on the contents of the M1? And ^ 14 flags, the corresponding motion compensation set block will have at least 2 and at most 10 motion vector components. The data format for the J vector is shown in Listing 38. Listing 38-Motion vector data format for H, 261 and H.263. Quantitative set moves to the macro "· '^-(Please read the precautions on the back before filling this page) Order by the Ministry of Economic Affairs Round Employee consumer cooperative printing byte order MF = 1 and M4 = 0 MF = 1 and M4 = l Byte 0 Forward move to 虿 Horizontal component The first block moves vector Horizontal component Byte 1 Forward move Vector horizontal component The first block moves the vector vertical component bytes 2 B- The block moves the vector horizontally and the second block moves towards the horizontal component-2 2 5-This paper scale is applicable to the Chinese National Standard (CNS) A4 Specifications (2 丨 0x297 mm) A 'ο

7 7 AB V. Description of the invention U-ei) Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (existing if MB = 1) Bytes 3 B-block moving vector horizontal component (existing if MB = 1 ) The second block motion vector vertical component byte 4 The third carp block motion vector horizontal component byte 5 The third block mobile consultation vertical component byte 6 The fourth block motion vector is reserved Horizontal component byte 7 Reserved fourth block motion vector Vertical component byte 8 Reserved B-block motion vector horizontal component (exists if MB = 1) Byte 9 Reserved B-block motion vector vertical component (Exists if MB = 1) Bytes 10-15 Reserved Reserved-2 2 6-(Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297) Chu) Decoration 43671〇Α7 B7 V. Description of the invention (^ call) 10.8.5.3 The four elementary video compression standards of the H element fe feed material have different maximum pixel bit lengths for different quantization levels. Comparison Made in list 3-9. Listing 39 Input and output pixel bit resolutions. Orange quantization level. Each I0BUS read / write each I0BUS 謓 / write. Number of bytes in the maximum bit length cycle. Number of pixels in the cycle. MPEG-1 9-bit 2 2 MPEG-2 12-bit 2 2 Η.261 8-bit 1 4 8.263 8-bit 1 4 ^ ------ ΐτ ------- Brigade (Please read the back first (Notes are re-filled on this page.) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative. Therefore, as we can see from Listing 40, the format of the pixel data used for MPEG is different from that used for video conference standards. Listing 4Q-Pixel Pseudo-Number Data Format-2 2 7-This paper size applies to Chinese National Standard (CNS) Α4 specification (210X 297 mm) 6 3 4 ο 5. Description of Invention UW) Staff Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Byte order of printing MPEG-1 and MPEG-2 Η '2 6 1 and Η. 2 63 bit sister 0 coefficient 0 coefficient G byte 1 coefficient 1 byte 2 coefficient 1 coefficient 2 byte 3 Coefficient 3 bytes 4 coefficient 2 coefficient 4 bytes 5 coefficient 5 bytes 6 coefficient 3 coefficient 6 bytes 7 coefficient 1 bytes 8 coefficient 4 coefficient 8 bytes 9 coefficient 9-2 2 8-equipment -(Please read the notes on the back before filling in this page),-° This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 5. Explanation of the invention A7 B7 Byte 1 〇 Coefficient 5 Coefficient 10 bytes π coefficient 11 bytes 1 2 coefficient 6 coefficient 12 bits 13 coefficient 13 bits 14 coefficient 7 coefficient 14 bytes 1 5 coefficient 15 10.9 break condition _ install-(Please read the back first (Notes for filling in this page)

， 1T Μ printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives ¾ BP interrupts ARM7 by asserting the ARM7_IRQ flag, if the flag meets the interrupt conditions described in this chapter, the BP has two sets of interrupt conditions , Default conditions and error conditions' These conditions are stored in RP_STATUS [15: 0]. If any bit is set by BP, then BP will start the ARM HR Q signal, all of which can be set by setting BP_INT_MASK [15: G] The relative bits of the register to mask. 10.3.1 New conditions in meat acres • Default conditions 0 (BP_STATUS [0] &gt; — When the processing of input punch 0 is completed, BP should assert that the ARM7_IRQ also sets the ibuF0_D0NE flag.-2 2 9-This paper size Applicable to China National Standard (CNS) A4 specification (210X297mm) Economy. Deng Central Standards Bureau Printing Co., Ltd. Shellfish Consumer Cooperative Press 4367 1 0 ^ A7 ____ B7 V. Description of the invention • Default conditions 1 (BP_STATUS [1]) — When When completing the input buffer 1, the BP should assert that the ARM7_IRQ also sets the IBUF1_D0NE flag. • Default condition 2 (BP_STATUS [2]) — When the processing of the input buffer 0 is completed, the BP should assert that the ARM7_IRQ is also set at the same time. OBUFO_DONE flag. • Default condition 3 (BP_STATUS [3]) — When processing of input buffer 1 is completed, BP should assert that ARM7_IRQ also sets the 0BUF1_D0NE flag. • Default condition 4 (BP_STATUS [4])-if the video code When the cut or GOB specified by ARM7 is completed, or if the video is decoded • When the start code of non-cut or non-GOB is reached, BP should assert that ARM7_IRQ also sets the BP_D0N'E flag at the same time. Default condition 5 (BP_STATUS [5])-When the text storage operation is completed in the prefetch text switching mode or when the current truncation or GOB is completed in the collaborative context switching mode, BP should assert that the ARM7_IRQ also sets the CTX_SW_DONE flag at the same time • The default condition 6 (BP_STATUS [6〗)]) Once the reload operation is completed, BP should assert that AEM7_IRQ also sets the CTX_REL0AD_D0NE flag. • Default condition 7 (BP_STATUS [7]) _ Currently BP_STATUS [7 丨 is reserved, so this bit must be set to "0 &quot;. Usually these default interrupt conditions are not recommended for use-2 3 0-this paper size Applicable to China National Standard (CNS) Λ4 specification (210X297 mm) Packing— (Please read the precautions on the back before filling this page) Order the I-Consumer Cooperative Cooperative Printing of the Order Bureau of the Ministry of Economic Affairs t 4367 1 Ο Λ ^ __ 5. Description of the Invention (Gechuan) BP_INT_MASK [7: 0] to mask, but, in some applications, the user may want to mask the default condition 1. 10.9.2 Error Cause If an error occurs in BP, then BP Set the BPjRR flag that will cause the ARM7 interrupt request. At the same time, the BP is set to the appropriate data of a non-zero value in the BP_ERR_CODE bit of the BP_STATUS register. This 8-bit BP_ERR_CODE has the following meanings: • BP _ ERR _ C 0 DE = 8 'b 0 0 0 0 _ 0 0 0 0: No error occurred. • BP_ERR_C0DE = 8'b0000_0 () 01: Illegal setting of the BLMODE register. _ BP_ERR_CODE = 8'b (30GO_0010: Illegal The position of the horizontal macro block is set == • BP_ERR_C0DE = 8'l] 0000_0011: Illegal vertical macro block location is set. BP_ERR_C0D8 = 8'b00Q0_0100: Illegal VLC for macro block address increment. • BPJRR__CODE = Vbf) GGG_Gl ( n: Illegal VLC for the macro style of the macro area. _ BP_ERIi_C0DE = 8'bQQ () CI_0110: Illegal VLC for the macro block movement mode.. BP_ERR_CODE = 8'bOOOOJlil: Illegal hidden motion vector 搮Identification bit. .BP_ERR_CODE = 8'b0000_100O: -231 for coding block mode-This paper size is applicable to Chinese national standards (CNS &gt; A4 specification (210X297 mm) --------- ^ ------ iT ------ ^ (Please read the notes on the back before filling this page) 43 67 1 Ο 4 α7 ______ B7 ___ V. Description of the invention G-iP) Illegal VLC. .BP_ERR_CODE = 8'b [) (3 [10_l (301: Illegal VLC for block DCT dc size. .BP_ERR_CODE = 8’bO0OG_101O: Illegal DCT dc value • BP_ERR_CODE = 8’bOOOO_1011: Illegal V L C for block DCT etc coefficient. • BP_ERR_CODE = 8’bOOOO_1100: The number of blocks in a macro area exceeds 64. • BP_EM_CODE = 8’bOOOO_1101: Illegal f_code value (that is, the value is 0). • BP__ERR_C0DE = 8’bGQ00_1110: Illegal V L C used for block DCT ac coefficient. .8P__ERH_CODE = 8’bOOOO_llll: Illegal iBUF and 0BUF address settings. • BP_ERR_CODE = 8’b 0 0 0 1 _DDOO: The lowest 4 bits of the starting address used for BP input or output buffer is not equal to 0. • Other BP_EO_CODE values are retained. Du Yin, Employees' Cooperative Standards Department of the Central Bureau of Standards, Ministry of Education 31 (Please read the notes on the back before filling this page) 10.10 The function of Note M requires 10.10.1 All data movement systems between PB and CCU Through IOBUS, IOBUS is a 32-bit bus with multiple addresses and data synchronized at 40 megabytes (MH2). Because 16-byte data transfer via IOBUS requires at least 7 cycles, however, I 〇B The maximum transfer rate for us will be g 1 · 4 megabytes per second 2 3 2-(CNS) A4 * m (210X297 ^) 'Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4367 1 Ο Λ Α7 Β7__ 5. DESCRIPTION OF THE INVENTION U-Suppress (&gt; ^ 5 ^ 6/3 (: (:) (= 731.4 megabits / second (pay 1) 1 ^ 3/56 (:)). For all IOBUS and write transactions In other words, βP can be a master BP or a slave BP. When the BP operation becomes a master BP, the BP must send a request signal to the IOBUS arbiter. If the IOBUS is space, the arbiter will send a permission and a device selection BP. The content of IOBUS resources may be any of the following three types: 32-bit containing two or four pixel elements Pixel information, 32-bit compressed bit string characters, M, and syntax / control parameters used for encoding and decoding operations. For further information on timing diagrams such as those on the IOBUS interface, it is recommended that you let Review the HSP_IOBUS manual. 10.10.2 The area is as wide as possible 10.10.2.1 Analysis of 檷 檷 刖 刖 刖 BP supports two types of zigzag scanning aiming matrix proposed in the MPEG video standard, transferred between The 8X8 zone data must contain all 64 components.

10.10.2.2 Rl.P.iiS For RLC decoding * BP generates zero material and level data based on the results of Huffman decoded DCT ac coefficients. If it is 64 for an 8 X 8 block The end_of_block signal was detected before each pixel data. Then the RLC decoder is negative and generates the remaining zero data. For RLC encoding, BP calculates the number of zero data of the continuous mine and combines the next @nonzero data to Generate run length and level code. If the remaining data is equal to zero, BP should generate the end_of_block signal instead of the remaining data.-2 3 3-This paper size applies the Chinese National Standard {CNS) A4 specification (2i0X297 mm) ---------- ^ ------ ίτ ------ Λ (Please read the notes on the back before shuffling f) ο

7 7 A B Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (Introduction Af) Generate RLC. The processing cycle for RLC bricks and the number of zeros to be generated are the same. 10.10.2.3 Huffman codes BP Huffman codes support all the Huffman codes (MPEG-1, MPEG-2, M.261, K, and M · 26 3) video standards Huffman tables • Assume that most of the tables have been modified to look up table ROMs, where each ROM character is 12 bits wide, but some have been developed into simple or rather complex Huffman tables The use of hard-wired editing to modify the decoder list that should use the search list ROM to modify the modification is summarized in Listing 41. List 41 Description of ROM size required for Huffman decoder search list Explanation of standard table ROM size (bits) 1 MPEG-1 &amp; 2, dct_coeff_next, TCOEFF 144X 12 8.261 2 Η.263 TCOEFF 102x 12 3 MPEG-1 &amp; 2, motion_vector_code »17X12 Η.261, Η.263 niacroblock_address_increinent -234- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297). ------, order ------ ^ (Please read the notes on the back before filling out this page) 6 3 4 ο 5. Description of the invention (/ Η #) 4 MPEG-1 &amp; 2, Η .261 coded_block_pattern 32X12 δ MPEG-1 &amp; 2, Η.261, Η.263 macroblocfc_type and MCBPC 18X 12 6 HPEG-1 &amp; 2 dct_dc_size 12X12 7 Y.263 for Y and CbCr Inter-segment CRPY 8X12 缌 and 333 X 12 encoder tables requiring a ROM size larger than the ROM size of the decoder table are listed in list 42. (Please read the precautions on the back before filling out this page) List printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives 42 Description of the RQM size number standard table for Huffman decoder search list Yuan) -23d- The standard of this paper is applicable to the Chinese National Standard {CNS) A4 specification (210X297 mm) 43671 Ο ^ 5. Description of the invention is called A7 Printed by the Consumers Cooperative of the Central Government Bureau of the Ministry of Economic Affairs. , Η.261 dct_coeff_next, TCOEFF 1δ6Χ 12 2 Η.263 TCOEFF 98X 12 3 MPEG-1 &amp; 2, Η.261, Η.263 iotion „vector_code, raacroblock_address_increment 35X 12 4 HPEG-1 &amp; 2, Η.261 coded_block_pattern 64X 12 5 MPEG-1 &amp; 2, Η.261 macroblock_type 22X 12 6 Η.263 MCBPC 28x 12 7 MPEG-1 &amp; 2 dct_dc_si2e 16x 12 8 Η.263 for Y and CbCr Inter-level CRPY 16X12 and 435 X 12-2 3 6---------- ^ ------ ΪΤ ------ Λ (Please read the notes on the back before filling in this Page) This paper size is in accordance with China National Standard (CNS) Α4 size (210X 297mm) Printed by the Shell Standard Consumer Cooperative of the Ministry of Standards of the People's Republic of China 43 67 1 Ο, V. Description of the Invention (4-e) 1 MPEG-1 &amp; 2, H.261 dct_coeff_next, TCOEFF 156X 12 2 H.263 TCOEFF 98X 12 3 MPEG- 1 &amp; 2, H.261, H.263 motion_vector_code, macroblock_address_incre0ient 35X 12 4 MPEG-1 &amp; 2, H.261 coded_block_pattern 64X 12 5 MPEG-1 &amp; 2, H.261 raacroblock_type 22X12 6 H.263 MCBPC 28X 12 7 HPEG-1 &amp; 2 dct_dc_size 16X for Y and CbCr 12 8 H.263 CKPY 16x 12 for information segment and information segment 435 x 12-2 3 6-------- --- Installation ------ ΐτ ------ Λ {Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specification (2! 0X297 mm) Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, ι π Α7 '_ _87__ V. Description of the Invention (, Sichuan) From the list, we can see that the total number of Huffmanmancoders # decoders is used. The required ROM size f / 68x 12 bits, the above table does not include the sign bits of the processed fill code, escape brick, DCT coefficient , And end_〇f_block code. r ~ 'The processing cycle for each Huffnan code is listed in Table 43. Listing 43 Processing cycle for Huffman codes

Huffman code type for MPEG-1 S 2 processing cycle for Η. 261 &amp; Η. 263 processing cycle Processing clock dct differential 4-δ 5-6 40 megajo dc coefficient (MHz) 1 with complement 2 dct ac coefficient escape code plus 2 3 fixed length code end_of_block 1 2 -237- This paper size applies to China National Standard (CNS) Α4 specification (210/297 mm) --------- t. ------ IT ------ Λ (Please read the notes on the back before filling this page)

i3 6710 ^ S code Other Huffman codes 1 1 Finally, note that if we use this method, we cannot improve JPEG, but please note that the dc_coeff_next_0 table can be applied to JPEG encoding applications. 10.10.2.4 The radical ri η borrows if the block in the block * BP is also the first component of the 8X8 block resource to calculate its differential dc coefficient, and re-establishes the dc with the dc coefficient of the transmitted differential value. 10.10.2.5 Unencrypted area: BP does not support unencoded blocks. VP and ARM 7 are responsible for processing the unencoded blocks. In order for VP and ARM 7 to process such blocks * BP indicates that Uncoded block in coded_block_pattern in the set block header. Printed by Shellfish Consumer Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs --------- 1 —— (Please read the precautions on the back before filling this page) Order 10.10.2.6 Xi Huaifu's 11 @ 席謓 Note that the order of the blocks used to encode and decode a macro block transmitted by both is equal to the following: Luma (Y) zone 0, 1, 2 and 3, Chroma blue (Cb) zone Blocks and chroma red (Cr) blocks. 10.10.3 Collective Blocks ΜM-2 38-The paper baht scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs is printed by 1 3 G 7 ^ C B7. — -.- * — — 1-丨 _ 1 ~-·-V. Description of the invention CW "10.10.3.1 Differential movement to the most BP From the motion estimation result, calculate the differential movement vector and re-establish the differential movement with the transmission Except for the following cases where the vector moves towards the child. • The first case is the case of MPEG-2 video coding in double prime mode. In this case, the motion vector transmitted to BP should be [0] [〇 ] [1: 〇] type, rather than the vector [γ1Π] [1: 〇] type. (Please see? ^ Day 6-2 Video Article 7.6.3.6). • The second case is a prior prediction Κ · 263 of the formula, in this case we may have a quadratic motion vector and these values should be passed from / to the BP as differential values. 10.10.3.2 Troublesome macro area Assume that BP does not support skipping Macro blocks * Both VP and ARM7 are responsible for processing these skipped macro blocks. The skipped macro blocks are processed. BP writes the horizontal and vertical macro block addresses into the macro block header characters. 10.10.3.3 P set block filling code In MPEG-1 decoding, BP discards A macro block fill code in a cycle, if it exists'. However, in the instigating code, BP does not seek users to enclose the macro block fill code within the title of the macro block layer. Generally, In other words, this padding code is used to control the output video rate buffer, so it is recommended to add a zero padding code between the start code and not the macro block padding code.-2 3 9-This paper size Applicable to China National Standard (CNS) A4 specification (210X297 public address) --- II ---- install -------- order ------ East. (Please read the precautions on the back before filling this page ) 4 3 67 1 0, at Β7 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives V. Description of the Invention (4-Called 10.10.4 Truncate or G n R Calendar 捭 10.10.4.1 Byte alignment for MPEG For -1 and MPEG-2 applications * the bit string output up to the truncation layer should be aligned by the byte 'for H.263 applications' although the bit string output up to the image layer should The bytes are aligned, but the output of the bit string up to the G0B layer may be aligned by the bytes. However, the output of the H.261 encoder will not be aligned by the bytes. Therefore, it is formed in ARM7. Conventional bit strings should be carefully programmed, because of these differences, it is assumed that when encoding, if the data used for the final data transmission through I 〇 Β S is less than 16 bytes, Then the PB automatically performs padding to zero at the end of the cut. 10.10.4.2 Clipping blinds outside the library are being decoded • Any additional clipping information that may be included in the clipped header of an MPEG-1 or MPEG-2 bit string is discarded by the BP * In the encoding Does not include any additional truncation information that may be requested by the user | If the user still needs to include the information in an MPEG-1 or MPEG-2 bit string, he / she can add that information In the bit string that has been coded by PB. 10-10,4 * 3 Intra Slice In the MPEG-2 truncation layer bit string, a parameter called Intra + Slice is used to notify that the current truncation only includes macro blocks within the macro block | this The information is not used in the decoding process and is intended to help DSM applications to perform fast forward or fast reverse functions, so * BP discards this information in decoding applications and in encoding applications, BP adds lntra_Slice as β Cut &quot; 2 4 0 ~ (Please read the notes on the back before filling in this page) -Pack -5 The size of the original paper is applicable to the Chinese National Standard (CNS) Α4 size (210X29 * 7mm) Staff of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives * _B7 _____ V. Description of the invention 0 like 0 in the title of the slice. 10.10.4.4 Paved or G Π R class: In MPEG-1, MPEG-2, and H.261, each image must have at least one cut or GGB start code * However, a picture 263 image may not have The G0B start code and title information, in particular, the first G0B in any Η · 2 3 3 image will not include the start code and title information. Therefore, if the incoming bit string is H.263, The BP state machine must directly process the macro block layer. In addition, if the GOB start code is issued while the bit string is decoded, BP must decode the start code and continue its processing without It will interrupt ARM7 ° 10.11 input / output zero and want to introduce the puncher and 10.11.1-the ship's sharp input and output group puncher must be improved with a double buffer, so in fact, we have four called Storage punches for IBUFQ, IBUF1, OBUFQ, M, and 0BUF1, as shown in Figures 64 and 65. As we can see from Figure 64 and circle 65, each elementary punch has a start address and an end address M and a full flag and a completion flag. In order to determine the size of each buffer | the user should The appropriate values are written into the start address buffer and the end address buffer for each buffer. Once the source processor for the yuan punch completes the write operation to the yuan punch, it should set the full flag and start writing to other banks. If the receiving processor for the bank finds that it is about to be stored, Taking the row group is full, the receiving processor captures the data. If the row group becomes empty, then the receiving -24 1- I ..... seed coat t III! I order-[t — _ .m (Please read the notes on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs' / 13 67 1 〇 Α7 A Β7 ___ V. Description of the Invention The Saki processor should set the completion flag and check the full flags of other platoon sisters. As explained in Section 10.7.2, the four start addresses are updated by BP, and each time BP accesses the input or output buffer, 'two registers are different from the start address. Will contain the most recent byte address accessed by the BP, so if any of the four flags IBUFO_DONE, IBUFl_DOiiE, OBUFO_DONEM, and OBUFl_DOHE are found to be set, then the BP should set its associated address again The starting address of the. It is also noted that the last four bits used for the start address should always be set to zero through ARM7. This is because an internal data alignment structure between FBUS, CCU and I0BUS also needs to be set for each Once the end address is made, the number of bytes used for any element size can be a multiple of 16. In addition, the minimum size of the element size recommended for MPEG-1 and MPEG_2 should be 64 bytes, and the smallest element size for Η. 2 1 1 and Η. 2 6 3 should be 128 bytes. This is to prevent ARM 7 interruptions due to BP. The resulting performance deteriorates. 10.11.2 7 ~ 7P regular guardian state if the two output buffers are full, then regardless of the input double buffer state, BP must stop its processing and fall into the state of the set, if OBUFO_DOME or OBUF1_DONE flag is set, then BP should automatically wake up from this idle state. If both input buffers are empty, BP does not need to stop immediately and can continue its processing until BP finishes processing the remaining internal data. However, if both temporary storage buffers are empty, BP will immediately Interrupt-2 4 2-

(Please read the notes on the back before filling in this page. J This paper size is applicable to China National Standards (CNS) A4 size (210X297 mm)) Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperation Du 3 4 67 彳 Ο μ ___ &quot; _Β7 V. Description of the Invention ⑷⑻) After the processing of the remaining data of ARM 7 is completed, and if the _injector is still found to be empty, BP must fall into the review state, and again, if IBUFO_FULL or IBUF1_FUU is Set, then BP should automatically wake up. The idle state described in this chapter is different from other idle states described in this manual, because wakeup from other idle states generally requires ARM7 control commands. 10.11.3 T / II slow sore device "Spore electricity: Example: determine the position and size of the BP input buffer and output buffer is mainly the responsibility of the user * users can change the buffer to VP data In the cache memory area of cache memory, ARM 7 data cache memory II, or SDR AN, although the improvement of the BP input and output dual buffers seems to be somewhat limited, there may be effective methods to change Bodhi above the buffer. Now, let ’s consider a special example of the application of rated element punch in video decoding. In this case, the user may want to improve a ring element for this input punch. Here * assuming we Use SDRAM, and the full buffer will be divided into four blocks, as shown in Figure 66. Initially, the user can set Rate_Buffer_Block_tm Rate_Buffer_Block_l to become IBUF0 and IBUF1 respectively. This can be accomplished by the following settings: I BU F0_START = Rate_Buffer_Address_0; IBIIF0_END = RateJuffer_Address-1;-2 4 3---------- ^ .------ IT ------ ^ (Please read the precautions on the back before filling This page) The paper standard i4 uses the Chinese national standard &lt; CNS) A4 specification (2) 0X297 mm

Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. The description of the invention is called IBUF1.START = Rate_Buffer_Address_2; IBUF1_END = Rate_Buffer_Address_3; The data in IBUFO (that is, the data in Rate_Buffer_Bl0ck-10) are all consumed by BP. After that, the BP will interrupt ARM7. Then, ARM7 can set Rate_Buffer_Bl0ck_2 to be IBUF0 by setting under K: IBUFO.START = Rate_Buffer_Address_4; IBUF0_END = Rate_Buffer_Address_5; After all the data in Rate_Buffer_Block_l is consumed by BP BP will interrupt ARM7 * again and ARM 7 can set Rate_Buffer_Block_3 to become IBUF1 by setting under K: IBUFl.START = Rate „Buffer_Address_6; IBUF1_ESD = Rate_Buffer_Address_7; after all the data in this Rate_Buffer_Block_2 is consumed by BP * ARM 7 can again set the Rate_Buffer_Block_Q to become IBUF0 by setting the same address as in the first step. Therefore, only by repeating this complete procedure can the ring-pumping device be improved. This example shows that BP double The use of the punch can be used depending on the K The intention is quite flexible. 10.12 In this section, if more than one application will run on the MSP, the ARH7 operating system will order the suspension of the current job and switch to another job. This procedure is generally considered as "this article" "Switching", BP supports two switching modes in this article, -2 4 4-This paper size is applicable to China National Standard (CNS) A4 specifications &lt; 210X297 Male 1) --------- Installation ----- -Order ------ Quan C, please read the notes on the back before writing 4: · Write this page) A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Below. 10.12.1 Switch to preemptive mode first. This switch means that BP will implement processing of the current 8X 8 circle prime blocks and then suspend the normal processing. * ARM 7 can be set in BP_CONTROL [6: 5] The CTX_SWITCH and CTX_M0DE flags in the register become "11" to command the prefetch text switch mode. When the processing of the current block is completed, BP will send the internal text to the external SDRAM for future processing. BP ends this article when saved | BP will set the bit BP_STATU The CTX_SW_DONE flag at the address of S [5] comes to 8iARM7 * and then * ARK7 will store all the contents of the input and output elements of the BP and start the BP for another job. This mode is for BP to respond to ARM7's switching request as quickly as possible. In the worst case, BP will need about 150 cycles (= 3.75 microseconds (w sec)) to complete the processing of the current block. However, under normal circumstances, it is reasonable to assume that a few cycles are required to complete the processing of this block. 10.12.2 Coordination is too much. "Switching Cooperative text switching is to save the BP from the stored procedures. This can be achieved due to the fact that each cut or G0B layer processing needs to start all BP internal states. Here In the mode, BP remotely cuts its current processing or (JOB * 's normal processing and then suspends buried there. ARM7 can command the cooperative type by setting the CTX_SWITCH and CTX_ffODE flags in BP_C0NTR0L [6: 5] to "lfl". This article switches the mode, when-2 4 5-^ — (Please read the precautions on the back before filling this page) Ding-5 thread paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm)

Printed by the Ministry of Economic Affairs of the Central Bureau of Bakery and Consumer Cooperative Production 5. Description of the Invention Ovwl) When the current cutting or GQB processing is completed, BP will interrupt by setting the CTX_Stf_D0NE flag at the address of BP_STATUS15] ARM7, then ARM 7 must store the entire contents of the BP's input and output buffers and start the BP for another job. 10.12.3 In order to switch to the previous work, BP should reload the article stored in SDRAM from the address SAVE_ADR [31: 〇]. In order to request this article to reload, it needs BP is in an idle state. The possible conditions for this request will be when BP_DGNE is set, when CTX_DONE is set, or when ARM7M software resets BP. Therefore, if ARM7 is set in BP_CONTROL [7] CTX_RELOAD flag, then BP will wake up from the indirect state and start grabbing the stored text. After BP ends the reloading operation in this article, BPM sets the CTXjELOAD_DONE flag to stop ARM7. Then, ARM7 must start the internal register of BP and enable BP for the previous work processing. 10.13 Ding Zuofei This section covers the detailed procedures for work contact exchange when BP completes processing. Here, "the update of the instructions for the final data" means that BP writes the appropriate values to VALID_BYTE_ADR [31: 0] and VALID_BIT_POS [2: 0]. 10.13.1 The market situation is not normal, the input data used for encoding will be fed from the VP * If one of the input double buffers is filled by the VP * then BP starts to read via iBUS-2 4 6 · (Please read the precautions on the reverse side before filling out this page). Binding-涞. This paper size applies to the Chinese national standard (CNS &gt; A4 size (2: 0X297 mm). System 4 3 67 1 〇Α7 __ ^ __ Β7__ V. Description of the invention 〇4-Z is called to take data, when the end of processing (that is, the number of macro blocks processed is equal to the macro specified by ARM7) The number of blocks) I BP must set the BP_DONE flag to interrupt ARM7 and fall into the idle state. The indicator used for valid data should indicate the "end of the compressed bit string" used for truncation or G 〇 B. In addition, VALID_BYTE_ADR [31: Q] should indicate the position of one of the output dual element punches . ARM 7 combines this compressed bit string with the upper-level header and repeats the process to form the final bit string. If ARM 7 wants to restart BP before BP completely consumes the data in the output dual buffer, ARM 7 can This is achieved by consuming at least one output double buffer and storing an index for the last data, as this index will be updated by BP when it is restarted. 10.13.2 Decoding situation First, ARM7 looks for a truncation or G0B start code (if it exists). If it finds this start code, then ARM7 starts and enables BP. Huffman decoding is performed in BP. "RLC Decoding" and inverse zigzag scan transform. The data is transferred to the output buffer for VP processing. BP then guesses this processing work until a non-cut or non-G 0 B start code is detected. If they are detected, then BP sets the indicator used to indicate the "end of the non-cutting or non-G0B start code" for the last data, and then breaks ARM 7, ARK7 and then The start code is decoded and a header analysis is performed until the next cut or G0B start code is found. 10.13.3 锫 颉 issued in the brain ^ bit string-2 4 7-This paper size is applicable to the Chinese National Standard (CNS) 'A4 parlance (2 〖0 &gt; &lt; 297 mm) --- ------ β ------ 1Τ ------ It (Please read the precautions on the back before filling this page) 436 ”〇 5. V. Invention Description (/ 4 lectures) Economy. 经济Printed by the Central Bureau of Standards Consumer Cooperatives in video conferencing applications where actual data will be transmitted via telephone lines and public switched networks, it is highly likely that the incoming bit string will contain-empty valid data, in this case Under '8? It is necessary to interrupt arm 7 and check the contents of the ERLUANDLEJODE flag * If the user decides the error handling mode before BP is enabled for a special application, it will be safer. When the ERii_HAHDLE-MODE flag is set to "" 1 ”* BP will automatically find the next start code. If the start code is used for truncation or G 0 B ', then BP continues its normal processing, because BP can find the start code earlier than ARM 7. And when the next start code is found, ARM 7 can perform other processing tasks, so this mode is quite efficient. However, a start code different from the slice or GOB layer is found * then the BP should set the BP_D0NE flag to ARM7 again and fall into the idle state. In this case, it is used for the final data. The indicator must indicate the end of the next start code. If £ 11! ^ _ 1 ^} ^! ^ _ ^ (] 13 £ flag is set to "0", then 8? Must fall into the idle bark state and No more searching for the next start code * In this case, the index used for the last data must indicate the location where the error was found. If the user wants to use the ΑΙΪίΠ instruction to remove the contaminated bit string * then this The mode will be valid.-2 48 &quot; This paper size applies to China National Standards (CNS) Α4 specifications (2 丨 0 X 297 mm). Packing-(Please read the precautions on the back before filling this page) Line. 43 67 1 〇, _ ^ __ V. Description of the invention (tH)

Attached R MP PC Bit Stream Processor Bit Stream Processor (BP, BitstreaB Processor) is one of the main MSP processing cores for video data encoding and decoding applications. BP covers slice layer encoding and decoding, and Η.261 / Η.263 group block (GOB) layer encoding and decoding. When decoding applications, BP provides the full Gongxun included in each macro block to the vector processor or ARM7 core. The bit stream processor hardware system is divided into four functional blocks: • 10-bus interface, including 10 control and decoding unit BP control state mechanism. Codec core, including BP register multiplexer and register, arithmetic logic Units and Multiplexers, and FIFO Control Units • VLC FIF0 Unit

• VLC Codec, including search ROM VLC LUT ROM 340 (third picture) with Codec address generator is described directly below. 1.0 Methodology f HethoHology 员工 Industry Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs (Read the precautions on the back before filling this page) The Look-up Table unit is the core of Huffman codes and decoding. This unit provides a list of all UCs included in the MPEG-1, MPEG-2, H.261 and H.263 specifications, and is provided by SAMSUNG MSP. Most of these lists are implemented in ROM, which is 12 bits wide. However • If the search process is too simplified or fails to fit the size of the ROM list, a specific encoding / decoding will be applied. All four paper scales in this layer use the Chinese National Standard (CNS) A4 specification (210X 297 gt), printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 43 67 1 Q, _b77 _ V. Description of the invention (π1) Specifications include many variable length codes up to 17 bits. In addition to the coded or decoded values • The code size and valid code indicator are intended to be used for coding and decoding, and M processes the process correctly. If the transmission method is used to encode or decode such VLC lists, both the ROM list and the address generator will be very large. 1.1 fTmpIftmftntation strategy) The implementation strategy can be described as follows: If it does not make the address generator difficult to process, add as many shared ROM lists as possible • Rearrange the VLC list based on encoding or decoding * Zero or one count , Which is based on Huffman code, decodes first by reducing the list size by using a bit flag such as a symbol or even / odd number • If possible, divide a ROM position into high and low levels LSBsM generates ROM list addresses. This method of simplifying the address generator by M is very efficient. The final ROM list size is 7 6 X 12 bits, which is much smaller than what this question implies.

This search is performed by a ROM list address generator and a ROM list search process. The address generator decodes such input signals as list type, mode, and VLC / value * and generates the address of the ROM list. The encoded or decoded data can then be read from ROM list values and other information. The decoding lists have two formats. The first format is used for DCT. The paper size applies to the Chinese National Standard {CNS) A4 (210X297 mm) --------- its ------, 玎 ------ ^ (Please read the notes on the back before filling out this page) Printed by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs ^ Λ3 '0 ^ at B7 V. Inventive coefficient, each VLC code has a ROM location The other format is applied to other lists. Each ROM location is divided into high-order 6-bit and low-order 6-bit; therefore, each position contains two VLC codes. The coded list has two formats: one format is used for TC0EF of H.263; the other format is used for other lists. Each ROM location contains a Huffman code used to encode the application. The ROM list has a size of 768 X 12 bits. The list can be described as follows: List 1: V L C decoding R 0 Μ list mapping

Specification list Description Range Bit MPEG 14, 15 DCT coefficient 0x000-0x08? 144X 12 Η. 261 5 TC0EF 0x000-0x06E Η.263 12 TC0EF 〇X〇9A-〇X〇FF 102X12 Η.263 9 CBPY 0x090-0x097 8x 12 MPEG 2,3,4 macro block type OxOOO-OxlOF 19_5 × 12 Η.261 2 ΜΤΥΡΕ OxlOO-OxlOF -3- This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) ---- --- f ------ IT ------, (Please read the notes on the back before filling this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 4367 1 Ο 4 α7 Β7 V. Description of the invention (rK) H.263 3,4 HCBPC 0x098-0x099, OxlOO-OxlOF, Ox06F-OxlBO (LOW) MPEG 1,10 MB INC, mobile code OxllO-OxllF, OxOE2 17X 12 Η. 261 1,3 MB ADR, mobile code OxllO-OxllF, 0x0E2 H.263 10 HVD OxllO-OxllF, 0x0E2 MPEG 9 MB form Oxl20-0xl3F 32X12 Η.261 4 CBP 0xl20-0xl3F MPEG 12, 13 DCT DC size Ox 140Oxl4B 12X12 Total 332 -4- --------- ^ ------ ΪΤ ------ ((Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standards (CNS) Λ4 specifications (2ίOX 29 7 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4367 1 0, V. Description of the Invention

Listing 2: VLC coded ROM list mapping specification list description range bit MPEG 14, 15 DCT coefficient 0xlED-0x288 156 X 12 Η.261 5 TC0EF 0xlED-0x25E Η.263 12 TC0EF 0x289-0x2E9, OxlEC 98X 12 Η. 263 9 CBPY 0xl9B-0xlAA 16x 12 MPEG 2, 3, 4 macro block type 0x2EA-0x2FF 22X 12 Η.261 2 ΗΤΥΡΕ 0x2EA-0x2FF Η.263 3,4 MCBPC 0X14C-0X167 28X 12 MPEG 1,10 MB INC, mobile Code 0χ17δ-0χ19Α 35X 12 Η.261 1,3 MB ADR, mobile code 0xl78-0xl9A (Please read the precautions on the back before filling out this page) '% The size of the paper used in this edition applies to the Chinese national standard (CNS) Λ4 specification (210X 297 mm) 5. Description of the invention) Η.263 10 MVD 0xl78-0xl9A MPEG 9 MB form 0x1AB-0xlEA 64X 12 Η.261 4 CBP OxlAB-OxlEA MPEG 12,13 DCT DC size 0x168-0x177 16X 12 Total 423X 12 Comments U-list 12 / H.263 has special encoding for 4 VLC codes. 2) Retain the position of three 俪 礁 · 解 ⑽ (DF⑽R) --------- &amp; ------ ΐτ ------ ^ (Please read the precautions on the back before filling in 舄(This page) All lists printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs for debrickers are rearranged based on zero or one count. If the MSB of a U C code is '0', zero count is applied. S then 1 uses one count. For example, if there is a * Q 〇 Q1X X X, the code ′ has 4 zeros. If there is' 1110XXX ·, there are 3 賫 counts. The bricking program will first decode the zero / one count and output the zero / one count of the VLC code to the ROM list address generator. The address generator then decodes the remaining codes K to generate an address. The address includes two parts: one part is an offset address—6 — This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210 × 297 mm). Printed by the Consumer Cooperative of the Central Elevator Bureau of the Ministry of Economic Affairs 4 3 671 〇 α7 ___: _ Β7 ____ 5. Description of the Invention (rl): Another part can be derived from the VLC list, which is called a masked address. The address is the logical OR of the two parts. Other information provided by this address generator can be described as follows: • VLC code size • Special flag: 2-bit flag 搮 * Indicated in the decoding state mechanism Η.261 of the 'ESCAPE (jump)', ' END OF BLOCK (end of block) ',' STUFFING (fill in blank Γ or * START CODE (starting code) • high data extraction enable: valid data is 6 bits higher • symbol / even number enable: this flag indicates the decoding The LSB of the VLC must be derived based on the list as a symbol or unit of digits. • Effective VLC • Mask bit and mask: These two signals are applied to generate masked addresses. Except for MPEG-2 List 14 In addition to, 15, and list 12 / H.263, for the ROM list, each position stores data in the high and low bit formats. The size of the ROM list used for decoding is 332 X 12 bits. 1.2. 1? Ll ^ 1 4 / UP FG-2 This list is the same as list 2-B · 5 C / Μ PE (3-1 and list 5 /. 2 6 1. ROM list format: bits 10 to 6: RUN Bits 5 to 0: LEVEL. 1.2.2 m ^ IR / MPPΠ-P The big branch of this list is shared with List 14 / MPEG-2 because they all have the same RUM, LEVEL, and VLC codes. ^ (^ List format: bits 10 to 6 41 ^; bits 5 to 0: 1 ^ \ ^ 1. --------- buttercup .---- --1T ------ (Please read the notes on the back of 1ί before filling this page) This paper size is applicable to China National Standards (CNS) Α4 standard (210X297 mm) 43 671 〇Α7 Central Ministry of Economic Affairs Printed by BJB Consumer Cooperatives B7_____ V. Description of the invention (1.2.3 Profit 1 2 / H · The cabinet is more than the list 14, 15 / MPEG-2. This list has one more output value, LAST '. ROM List format: Bit 11: LAST; Bits 10 to 4: RUN; Bits 3 to 0: LEVEL. 1.2.4 Swing 磘 / 戸 隹 Block 捎 S This section covers List 1 / MPEG-2, List 1Q / MPEG-2, list 2-B.1 / MPEG-1, list 2-B.4 / MPEG-1, list 1 / H.261, list 3 / H.261, and list 10 / H.263. Please note For motion codes, except for VLC = 1, LSB is a sign bit. For macro block increments, except for VLC = 1, LSB is an even-valued flag. Therefore, only half of the list can be decoded. .If the tile symbol / even bit is ignored, except for the upper part of the list 1Q / H.263 * the list of the two types is The VLC same with the decoded value. The decoded value is up to 6 bits, which means that two data values are put into one position. Although the decoded value of the lower part of the list 10 / H.263 is different from the others *, because of the use of fixed points, that is, 16 positions are used and half of the positions are used to cover all of these lists, tile The bit values are the same. Only one FSM system uses M to generate ROM addresses. At the time of application, if the mobile code is decoded, the ROM list provides an absolute value. On the other hand, if the address generator enables the sign bit, the decoder will derive the LSB as a sign, where '1' represents a negative number and a positive number. This algorithm can be described as follows: -8- --------- Κ ------ '1Τ ------- ^ (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS} A4 (2! 0X297). Central China Bureau of Standards, Ministry of Economic Affairs, Consumer Consumption Printing 4367 1 Ο Λ Α7 ______ Β7 V. Description of the invention) if (sign_enable == l) increment_va 1ue = sign * ROH_table_value; else increaent_value = EOM_table_value; If the macro block address increment list is decoded, the result can be derived from the ROM list value and the even flag. For example • Get a '5' value from the ROM list. If the even flag is high, the result of '1 G' is obtained. If the even flag is low, 低 1 ′ is obtained. The description of this algorithm is as follows ... if (even_enab 1 e = = 1) increfflent_va 1 ue = (R0H_tab1e_va 1ue &lt; &lt; 1) | (-even_bit); else increment_value = ROM_tab1e_va 1ue: ROM list format: bit 11 To 6: high data; bits 5 to 0: low data. 1.2.5 Shame-shaped rims in the huge area This section covers List 9 / MPEG-2, List 2-B.3 / MPEG-1, List 4 / H. 261 (CBP). The decoded value is up to 6 bits, which means that two data lines are put into one position. That is, all 32 lists are covered by M. ROM list format: bits 11 to 6: high-order data; bits 5 to 0: low-order data. 1.2.6 P 隼 area shame type -9- This paper size applies to Chinese National Standard (CNS) A4 specification (210X 297g t) --------- U ------ 1T ---- -. ^ (Please read the notes on the back before filling in this card) Printed by the Consumers ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the Invention (Me) This section covers lists 2, 3, 4 / MPEG-2 , List 2-B.2 / MPEG-1, List 2 / Η · 261 (MTTPPE), and List 3, 4 / H.263 (MCBPC). The decoded value is up to 5 bits. The concept of high / low data is still used. Only a fake FSM uses M to generate ROM addresses. βOM list format: bits 11 to 6: high-order data; bits 5 to 0: low-order data. Although some bits have different meanings for different specifications, the format of the macro block type is commonly defined for each specification, which is based on MPEG. It should be noted that Η · 263 has secondary decoding based on its information box, which can be described as follows: Decoding MCBPC · It obtains a 3-bit macro block type; Macro block type search, based on macro blocks Format, PB flag, and image format: The format of the macro format in the macro area of the VLC list can be described later: Listing 3: Macro block format format for MPEG Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 bit 0 Reserved Q FMV BMV P 1 List 4: H.263 HCBPC format bit 4-2 bit 1 bit 0 -10- This paper size applies to China National Standard (CNS) A4 specification (210X 297 male Li) (谙 Please read the notes on the back before filling in this page)

A V. Description of the invention ()

MB type CR CB

List 5: H.261 macro block format format Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FI LQ MVD Reserve CBP INTRA From List 4, you can get not only the 3-bit macro Block type, and a 2-bit chroma form can also be obtained. Here, the macro block type is a 3-bit value * which has a range from Q to 4. As mentioned earlier, detailed macroblock type data is decoded at the second level. The decoding search list can be described as follows: List 6: Macro block decoding list for 263 --------- t ------ IT ------ thousands. &Lt; ( Please read the notes on the back before filling this page) Ministry of Economy _ Central Standards Bureau Bureau Zhenggong Consumer Cooperative Co., Ltd. Printed PT MB Type PB M4 θ MF HODB P (Y) INTRA INTEK 3 0 0 0 0 0 1 1 INTER 4 0 0 1 0 0 1 1 INTER 0 0 0 0 1 0 1 0 -11- This paper uses China National Standards (CNS) A4 specifications (2 丨 Ox297 mm) 6 3 4 ο

7 A Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy INTER 1 0 0 1 1 0 1 0 INTER 2 0 1 0 1 0 1 0 INTER 3 0 0 0 0 0 1 1 INTER 4 0 0 1 0 0 1 1 INTER 0 1 0 0 1 1 1 0 INTER 1 1 0 1 1 1 1 0 INTER 2 1 1 0 1 1 1 0 INTER 3 1 0 0 1 1 1 1 INTER 4 1 0 1 1 1 1 1 1.2.7 ΠΓΤ Π [size This section covers the list 1 2, 1 3 / Μ PEG-2 and the list 2-Β. 5 / Μ ί »EG-1. It should be noted that due to the structure of VL C, one count M is used instead of zero count. -12- This paper size applies to Chinese National Standard (CNS) A4 (210X 297 mm) (Please read the notes on the back before filling out this page) Loading 43 67 1 〇α7 ___ ^ ΒΊ __ _-— ____ __ 5. Description of the invention ROM list format: Bmtl to 6: high data: chroma; bits 4 to 0: low data: luma. Bit U and Bit 5 are reserved and unused.

1-2.8 CBPY This section covers Listing 9 / H.263. It should be noted that this list contains the second sister data *-one group is used for mutual (i nt e r-) images and another group is used for int a-images. A sister value is a transformation of another group, which enables a group of data to be stored in ROH. Here, the Department of Internal Capital is placed in ROM. A 4-bit value is used to describe the CBPY value. βOM list format "bits 9 to 6: high-order data; bits 3 to 0; low-order data. Bits 11 to 1D and bits 5 to 4 are reserved and unused.

1.2.9 DUAL PR THFIS HODR This section covers lists 11 / ΜPEG-2 and list 7 / Η .2 6 3 〇 These two lists are very simple and small, so they can be decoded directly. 1.3 煸 琚 fRNnnnfn is similar to the decoding * encoding program using the concept of zero / one count. The EOM list includes zero / one count information, code sizes following the first T after zero or one count, and UC codes following the first / last '1'. According to this format * the size of the ROM list can be limited to 12 bits per position, with four exceptions to the list 12 / H.263 *, which is solved by the M-specific encoding. This format can be described later: Listing 7: —Generally encoded format Bit 1 Bit 8 Bit 7-Bit 5 Bit 4-Bit 0 -13- ^ Paper scale Gu Zhongguanjia standard (Norway ) 8 4 specifications (2 offering 297 mm) y ------ ΐτ ------ line (Please read the precautions on the back before filling out this page) '3 B7 1 〇 ^ Α7 ^ Β7 V. Description of the invention）) Zero / 賫 count VLC code size VLC code list 8: List 12 / H.2 6 3 encoding format bit 11-bit 9 bit 8 -Bit 6 Bit 5-Bit 0 Zero / One Count VLC code size VLC tile is in the above list, VLC code size is the size of the VLC code following the first / last '1'. The VLC code is the VLC code following the first / last '1'. In the shape of zero count, the first VLC code of '1' is derived. Otherwise, the VLC code should be derived from the bit following the last '1'. It should be noted that the counting application at the time of encoding is different from the decoding case. One count is applied if and only if the one count is enabled by the address generator. Therefore, if the MSB of a VLC is 1 but the one-count flag is low, the zero / one-count part of the ROM list will be 0, which means that the zero count is applied. The following examples cover all possible cases of coding. Example 1 ί VLC = 0000011 [) D1, one count enabled = 0—general result: 0 1 0 1 1 0 0 0 1 0 0 1 List 12 / H.263 result: 101 1QQ 0Q1001 Example 2: VLC = 1 1 0 0 1, one count enable = 0-the result of the general situation: 0000 100 01001 -1 4-This paper size applies to China National Standard (CNS) A4 specification (2I0X297 mm) ------ --- U ------ Order ------ {Please read the notes on the back before filling in the form page) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 4367 1 Ο ^ Α7 &gt; A 7 ___ Β7 _ 5. The results of the invention description (ρ-κ) list 12 / Η.263: 〇〇〇〇〇001001001 Example 3: VL C = 11 〇1, the responsibility count enable = 1-the result of the general situation: 0Q1Q 〇11 00001 The result of list 12 / Η.263:-The general address is generated by adding an offset to the input value. 1 * 3 1 Toe watch 1 &quot; MPFn-? This list is the same as list 2-B.5C / HPEG-1 and list 5 / H.261. Encoding processing RUN, FIRST, DC, ESCAPE and END OF BLOCK input 0 Encoding result: The offset address is generated by adding M with LEVEL or RUN. 1-3 * 2 T5 / HPRG-2 Most of this list is shared with list 14 / MPEG-2, because they have the same RUN, LEVEL and VLC codes. For some specific cases, a 萱 count is used. The encoding processes the input of RUN, LEVEL, FIRST DC, ESCAPE and END OF BLOCK. Encoding result: offset address, and one count indicator. 1.3.3? Ll ^ 1 2 / Η. As mentioned earlier, this list is very special. Different formats are handled by K. Unfortunately, there are some exceptions where the 12-bit M cannot be used to describe the vLC code. These exceptions are described in list g. These exceptions can be specially coded without going to the ROM list. Listing 9: Exceptions to the coding in Listing 1 2 / H. 2 6 3 -15- The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2Ί0 × 297 mm) --------- 1-- ---- IT ------ ii! (Please read the notes on the back before filling out this page) 4 3 6 * Μ 〇, Α7 Β7 V. Invention Description LAST (Final) RUN (Execute) LEVEL (bit Quasi) 0 0 10 0 0 11 1 0 3 1 1 2 (Please read the precautions on the back before filling in this page) Order code processing RUN and ESCAPE input. Coding result: The offset address is used to add LEVEL or RUN to generate the address. 1.3.4 Children's Blocks / Reed Blocks This section covers List 1 / MPEG-2, List 10 / MPEG-2, List 2-B.1 / MPEG-1, List 2-B.4 / MPEG- 1. List 1 / Η.261, List 3 / Η.261 and List 1Q / H.263. As stated in the decoding section * all such lists can share a ROM list and a FSM. The VLC code derived from the ROM list should be combined with the symbol / unit digit to make a complete VLC code. Therefore, for mobile codes, the input values processed in this code FSM are absolute values, and their LSBs are the number of bits and the increment of the macro block address shifted to the right by one bit. -1 6- This paper standard is applicable to Zhongli National Standard (匚 Can) 8 4 (210 '; &lt; 297 mm) Flavor:. Central Standards Bureau of the Ministry of Economic Affairs Printed by the Central Standards Bureau of the Ministry of Economic Affairs Industrial and Consumer Cooperatives printed r A3 6 '0 * at _____ B7____ V. Invention Description Coding processing STUFFING, and ESCAPE's turn in. 1.3.5 Jue 1S Huai shaped rim This section covers the list 9 / H P E G- 2, the list 2-B. 3 / Μ P E G-1. This address is the sum of the offset and the morphological value. 1.3.6 Types in the PP area This section covers the list 2, 3, 4 / MPEG-2, list 2-B · 2 / MPEG-1 0 1.3.7 H 4 / m (M [: BPC) image Information on patterns, macroblock patterns, and fill-in-the-blank flags are provided to generate the EO M list address offset. This address is the sum of the offset address and the CBDC. 0 1.3.8 m m? / H. FMTYPK) This address generator is very complicated and has no added value for κ. 1.3.9 CRPY As discussed in the section on decoding, only intra image data is encoded. If the image type is an inter image, the data must be converted first. This address is the sum of the offset and the CBPY value. 1.3.10 ί) [Τ IK scale This section covers the list 1 2, 1 3 / Μ PEG-2, and the list. 2_B. 5 / MPEG-1 ° Because the SVLC code of brightness and chromaticity is the same, some The ROM list is available for sharing. The color code flag and some bit values are used to generate the offset bit. -17- --------- y ------ IT ------ (Please read the note on the back first Please fill in this page again for this matter) This paper size is applicable to Chinese National Standard (CNS) Λ4 is present (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ36 ^ 0 · Λ7 Β7__ V. Invention Description u #) address. The ROM address can be obtained by adding the offset value to the actual value '. 1.3.11 D I] A I. PRTM This section covers List 11 / MPEG-2 and List 7 / H.263. This list is very simple and small, so you can encode it directly. 2.0 Stele description The hard system of VLC encoding / decoding is included in the block of 'VLC'. This block contains three sub-blocks. These blocks are used to generate ROM list addresses or decode / encode the material itself. ‘ViC_DEC’ is used to deblock UC and generate ROM list address. VLC_EW 僳 is used to encode a block of VLC, which can generate ROM list addresses or specific codes for TC0EF list of H.263. 'LOOKUP' is to output VLC data based on ROM list value or specific code value. 2.1 The core of VLC solution addresser VLC_DEC is to decode FSM. This FSM decodes the input information and controls address generation. The input and definition of the FSM can be described later. • Zero / One Count (15 bits): Provides a zero / one count value. • Zero / Tone Count (4 digits): Provides zero / fee count. The purpose of using two different bit counting signals is to reduce the sparseness of input data to the user. In most cases, 15 bits are used. • One count enable (1 bit): One count indicator. * List type (6 digits): List type. Listing 10: VLC_DEC FSM list format format -18- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

1T line-

C

7 7 A B V. Description of the invention

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DCT size MB INC / MC MB form CBPY MB type DC C0EF horizontal (3 bits): operation mode List 11: VLC_DEC FSM mode format

Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H.263 Specification Image Type Chroma Final DC List 15 MB INC (Please read the notes on the back first (Fill in this page again) Specification definitions and image types are explained in the pin definitions. A special algorithm uses M to generate a decoded ROM list address', which simplifies the hardware and ensures ROM access time. The procedure is as follows: Step 1: Generate an offset address (OFFSET). Step 2: Generate a 4-bit shift (MASK_SHFT), and this shift will shift the 16-bit FIF0JATA to the right. Then the four least significant bits (F0L_DATA) are derived. Step 3: The four bits obtained in step 2 are inverted. Step 4: Generate a 4-bit mask signal to mask the data obtained in step 3 (MASK). -19- This paper size applies to the Chinese National Standard {CNS) A4 (210X297 mm) Silver — Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 43 67 1 0 λ Α7 j Β7 5. Description of the invention (1Η〇) Step 5 : Use the result of step 4 and the offset address as an OR or OR! . This result is the ROM list address. Combining these steps yields:

Address = OFFSET | (BI TREVERSE (Bit (3-0) (FIF0_DATA &gt; &gt; MASK ^ SHFT)) &amp; MASK) The output of this FSM is as follows: • MASK (4-bit): Mask material • OFFSET ( 3 bits): ROM list offset address • MASK_SHFT (4 bits): displacement amount • SIZE (5 bits): VLC size. SPECIAL_FLAG (3 bits): additional data for decoding: List 12: VLC_DEC The definition of special flags is f ο (Please read the precautions on the back before filling this page) The definition of the position value printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economy Bit 2 leads to the LSB bit of the VLC. 10 End of block / fill in blank 11 Η. 2 61 start code -20- Αφ This paper size applies Chinese National Standard (CNS) Λ4 specification (210x297 mm) 4 3 67 1 0 a? ___ ^ _ B7__ 5. Description of the invention U4) • VALID_VLC (1 bit): valid VLC code flag • HIGH_DATA_I0iCATOR (1 bit): the 6-bit input pin leading to ROM data: • F0L_DATA (4 bits): FIF0_DATA after shifting (Refer to step 2 above) • CNT (4, bits): Zero / one count_ 0NE_CNT_EN (1 bit ): One count indicator • MODE (14 bit): List type and other information. The definition is as follows 〇 (Please read the notes on the back before filling this page)

* 1T List 13: Mode format in VLC_DEC

Bit 13 Bit 12 Bit 11 Bit lfl Bit 9 Bit 8 Bit 1 DCT size MC MB INC MB shape CBPY MB type DCT C0EF This paper's standard is applicable to Chinese National Standard (CNS) Α4 (120X297 mm) ) Printed by the Consumer Cooperative of the Central Keji Bureau of the Ministry of Economic Affairs 6 digits 5 digits 4 digits 3 digits 2 digits 1 digit 0 ; 01 = MPEG-2; 10 = H.261; ll = h-263 -21- Printed by Xiaoxian Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 43 67 1 〇 λ α7 ______ Β7__ 5. Description of the invention 〇5-π) i Figure Image type: Q0 = RESERVED; 01 = INTRA; 1 〇 = PREDICED; 11 = BIDIRECTI 0 NAL;

• FIFO_DATA (16-bit): data, including VLC output pins: • ROM_ADR (1G-bit): RQM list address • MASK_SHFT (4-bit): used for the displacement of FIF0_DATA (refer to step 2 above) SIZE ( 5 bits): VLC size • SPECIAL_0 (3 bits): special flag (refer to FSH output) • VALID_VLC (1 bit): valid VLC flag • HIGH_DATA (1 bit): LSB of VLC is taken as an even flag Symbolic indicator • FULL _D ΑΤΑ (1 bit): Full 12-bit asset structure, which is high when decoding DCT coefficients. TABLE (6 bits): Defined at FSM input

• T_M0DS (9-bit): Defined by MODE at FSM input 2.2 VI. Γ RNC is the same as the section of M VLC encoding core, VLC_ENC encoding variable length code. The output of this section is a ROM list address or a special code for the VLC. As described in section 1.0, the 'coded data structure is conformed to the 12-bit data format except in some special cases of TC0EF for H.263. From the point of view of the code body K, although it is generated from the use of a bit adder -22-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 male f) (Please read the precautions on the back before filling in this Page) Order printed by the Central Bureau of Standards, Ministry of Economic Affairs, Consumers and Cooperatives, printed 4367 1 〇, _Β7 ____ V. Description of the ROM list address, which is much simpler than the VLC_D EC section. Like VLC_DEC, the core of this section is pseudo-named an FSM of VLC_ENC. The other FSM, ENC_SP, is used for special encoding. The round-in signal to FSM VLC „ENC is the same input pin as in this section: • LAST (1 bit): LAST value for TC0EF list of H.263. RUN / VALUE (6 bits): If The list of DCT coefficients is being encoded. This input means RUM. Otherwise, it is a general value, such as PATTERN. • LEVEL (6 bits): DCT coefficient LEVEL (level) • SPECIAL-FLAG ( 2 bits) · Special flag, which is defined in the VLC_DEC section TABLE (6 bits): same as VLC_DEC MODE (9 bits): same as VLC-DEC This RQM address generation system is very directly available. FSM Provide an offset address, which is added to VALUE (8UN) or LEVEL or DK to form the address. For special codes, because these VLCs have the same size and zero count, the round-off is the 2 least significant bits. The code of the round-out pin can be described as follows: • ONE_CiJT_FLG (1 bit): indicates the use of the VLC component, ': T count • SIGN_EN_BIT: indicates that the VLC component puts the sign / even bit as VLC LSB -2 3-A7 (Please read the precautions on the back before filling in 4 pages) V 'Staple paper Standards are applicable to China National Standard (CNS) A4 specifications (210X297 mm) 43671 〇, A7 -------- B7__ 5. Description of the invention (15-% • SPE [: IU_E: kC0DE (1 bit): Special Encoding flags • VLC (2 bits): Special encoding VLC codes LSBs • ADR_A (16 bits): Offset address. Note that the upper 6 bits are 0 ADRJ (16 bits): Another part of the address. Note that the high-order 10-bit system is always 0 2 · 3 L〇nn 丨 ρ (Strike) This section provides encoding / decoding VLC data. This block handles the following scenarios: • Regular 12-bit code / decode R0tl list Value output • Bit high bit / low bit decoded data output • Special coded data reconstruction as required, the output data is full and zero. Input pins: D_ADR (10 bits): Decode ROM address • E_ADR (10 bits) : Encoding R0H address. ENCODE (1 bit): 1: Encoding; G: Decoding. HIGH (1 bit): Leads to the 6-digit flag printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs {Please listen first Read the notes on the back of the page again &gt; · This page) • ENABLE (1 bit): All 12-bit data flag • UC (2 bit): Special edition The symbol • S P E C I A L _ E N C 0 D E (1 bit): _ a special code flag pin: 1001 (1] £ &gt; (16 bits): 711 (: code. -24- This paper size applies to China National Standard (CNS) A4 (210x297)

Claims (1)

The Central Bureau of the Ministry of Economic Affairs, the Ministry of Economic Affairs, Cooperative Cooperatives, India Cooperative Policy 4367 1 0, i D8 VI. Patent Application Scope 1 'A shovel for editing or decoding video data, the system includes: — a vector processor, a system Used to perform linear conversion of video data; a bitstream processor * uses K to compress one of the inward processors to output or decompress the video asset K to the vector processor; and a control circuit, which uses K synchronizes the operations of the vector processor and the bit stream processor, wherein the bit stream processor can be interrupted by the control circuit to stop processing a video data stream and start processing a different video data stream This enables the bit stream processor to process two fake video spring streams in approximately parallel, so that the system can encode or decode two video data streams in real time. 2 · The system of item 1 of Shenyang Patent Fanyuan, in which each video data stream represents a moving day. 3 — A system using K code or decoding video data, the system includes: a vector processor for performing linear conversion of video data; and — a bit stream processor for compressing the vector with K One of the processors outputs or decompresses the video data to the processor. The vector processor can be programmed by the program to execute a single arithmetic or Bollinger instruction1 and the bit stream is processed. The device cannot execute a single arithmetic or Bollinger's instruction programmatically. 4 * —A method for encoding or decoding video data with K. This method includes: This paper is again applicable to the Chinese National Standard (CNS) A4 scale (2 丨 0X297 mm) (please read the note ^ h on the back first) (Fill in this page again) &lt; ΤΓ + Α8 Β8 C8 D8 43671 〇, patent application scope K a vector processor to perform linear conversion of video data; a bit stream processor to compress the output of one of the vector processors, Or decompress the video data M and input it to the vector processor; and synchronize the operations of the processing S and the bit roll processor with a control circuit, wherein the bit stream processor can be used by the control circuit. Interrupted, κ stops processing a video data stream and starts processing a different video resource stream, so that the bit stream processor processes two video data streams in parallel, so that the system can encode or decode two video streams in real time Yellow stream. 5 · The method according to item 4 of the patent application, wherein each video data stream represents a moving day. 6 'A method for encoding or decoding the message data * This method includes: (Please read the precautions on the back before filling in this page) The central government bureau of the Ministry of Economic Affairs prints out the solution or layout of the consumer cooperatives, military Process and I I; rotation method for a non-revolving JK-based device calculator line management, the management of the device type. The amount of material flow and the flow of information are directed by the source. The amount of data is sufficient to see the contraction. The line can be used to press the system or the actuator to the device. Let Yiliangyuan refer to the one-way position of the funds. The forest will be distributed by the MV as it or the thread MV is calculated. The paper size is based on the Chinese National Standard (CNS) A4 specification (210X297 mm).