A7 B7 4 3: 93 5 r丨唪 4383twf. doc/〇〇5 五、發明説明（ί ) 本發明是有關於一種晶體振盪輸出入電路，且特別是 有關於一種可大幅減少特殊應用積體電路（APPlicatlon Specific Integrated Circuit;以下簡稱ASIC)元件庫的輸出入 (以下簡稱1〇)數量，並通過充電元件模式（Charge Device Mode ;以下簡稱 CDM)靜電放電（Electrostatic Discharge ; 以下簡稱ESD)測試之加強CDM ESD保護的通用晶體振盪 輸出入電路。 在積體電路（以下簡稱1C)的製程中，靜電放電（ESD)常 是導致積體電路損壞的主要原因。而於1C的製造及測試 中，由於操作者本身、或者是在傳送過程中摩擦生電，均 可能會產生靜電荷。而這些累積在操作者身上、1C本身、 ’或者是工作環境四週的靜電荷，一旦接觸到1C，或是經由 1C接觸到地，便可能會以人體放電路徑模式(Human Body Mode ; HBM)、充電元件模式（CDM)、或機器放電模式 (Machine Mode ; MM)等方式造成放電的現象，使得ic受 到相當程度的損壞。 而MOSFET因其高輸入阻抗及低崩潰電壓的特性，在 1C族中承受靜電放電的能力最差。所以在製造1C電路時， 便習慣性的在容易發生靜電放電的地方例如是電路的輸出 入（以下簡稱1〇)埠，另外增加一組保護電路，以做爲靜電 放電發生時，防止額外電流破壞元件的放電路徑。 晶體振盪器焊墊（Crystal Oscillator Pad)在一套特殊應 用積體電路（Application Specific Integrated Circuit ;以下簡 稱ASIC)元件庫（library)之中扮演著重要的角色，主要的原 本紙痕尺度適用中菌國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -I .二 、-&A7 B7 4 3: 93 5 r 丨 唪 4383twf. Doc / 〇〇5 V. Description of the invention (ί) The present invention relates to a crystal oscillation input / output circuit, and in particular to a integrated circuit which can greatly reduce the special application (APPlicatlon Specific Integrated Circuit; hereinafter referred to as ASIC) component library input and output (hereinafter referred to as 10), and passed the Charge Device Mode (hereinafter referred to as CDM) Electrostatic Discharge (hereinafter referred to as ESD) test to strengthen CDM ESD protected general crystal oscillator input and output circuits. In the manufacturing of integrated circuits (hereinafter referred to as 1C), electrostatic discharge (ESD) is often the main cause of damage to integrated circuits. In the manufacture and test of 1C, static electricity may be generated due to the operator itself or frictional electricity generation during the transmission process. And these static charges accumulated on the operator, 1C itself, or the surroundings of the working environment, once they touch 1C or touch the ground through 1C, they may use Human Body Mode (HBM), Discharging is caused by charging device mode (CDM) or machine discharge mode (Machine Mode; MM), which causes considerable damage to the IC. And because of its high input impedance and low breakdown voltage, MOSFETs have the worst ability to withstand electrostatic discharge in the 1C family. Therefore, when manufacturing a 1C circuit, it is customary to place the circuit where the electrostatic discharge is likely to occur, for example, the input / output (hereinafter referred to as 10) port of the circuit. In addition, a set of protection circuits are added to prevent extra current when electrostatic discharge occurs. Destroy the discharge path of the element. Crystal Oscillator Pad plays an important role in a set of Application Specific Integrated Circuit (ASIC) component libraries. The main original paper mark scale is suitable for medium bacteria. National Standard (CNS) A4 Specification (210X297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -I. 二 、-&
經濟部智慧財產局員工消費合作社卬製 4 J c 4383twf.doc/0〇5 A7 _____B7____ 五、發明説明（〆）Customs Cooperative System for Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 J c 4383twf.doc / 0〇5 A7 _____B7____ 5. Explanation of the Invention (〆)
因在於晶體本身提供了一個很高的品質因素（Q)値，使得我 們現在只要用很簡單的電路，便可以得到很穩定頻率的信 號。然而，隨著時代的進步，一套ASIC元件庫往往有著許 許多多的晶體振盪器焊墊，因而造成了 ASIC管理者與ASIC .設計者的困擾。 請參照弟1圖’其繪不的是習知一'般互補式金氧半電晶 體（以下簡稱CMOS)晶體振盪架構的電路圖。 如第1圖所示，其包括一 P型金氧半電晶體（以下簡稱 PMOS電晶體）12、一 N型金氧半電晶體(以下簡稱NMOS 電晶體）14、一回授電阻16及一晶體振盪器18。PMOS電 晶體Ϊ2與NMOS電晶體14兩者相當於一個CMOS電晶 體15，又如同一反相器，係做爲放大單元，其中CMOS電 晶體I5係建構在ASIC 10的內部。回授電阻16係用以決 定CMOS電晶體15的操作點，亦即用以提供電路所需之偏 壓。而晶體振盪器18則用來限制頻率。 傳統上，一套ASIC元件庫需要使用到多個振盪器10， 因此花費成本較高。此外，假若不能在一個振盪器1〇中’ 提供多個經由依攄不同供應電壓源所調到最佳化的元件驅 動大小的話，則無法提供不同客戶設計的需求，例如：有 些客戶會要求要降電壓，例如從3.3伏特（V)降至2.4V或降 至1.5V等情形。 而且，CDM ESD在現今超大型積體電路（VLSI)上，所 發現失敗的情況也越來越普遍。依照傳統之架構，在進行 CDM的ESD測試時，並無法有效地散去聚集在基底上的電 本紙張尺度適用中國國家標率（CNS ) A4规格（210X297公釐） -----^--.I 裝------訂------备 (請先閲讀背面之注意事項再填寫本頁) 4383twf.doc/〇05 A7 B7 五、發明説明（今） 荷，導致其保護振盪器IO的能力不佳，容易造成振盪器10 受損。 (請先閱讀背面之注意事項再填寫本頁) 有鑒於此，本發明提出一種加強CDM ESD保護的通用 晶體振盪輸出入電路，建構於特殊應用積體電路之內部， .其係由第一 PMOS電晶體、第二PM0S電晶體、第三PM0S 電晶體、第一NM0S電晶體、第二NMOS電晶體、第三NM0S 電晶體以及控制邏輯所組成。其連接關係爲，第一 PM0S 電晶體之源極耦接至電壓源。第二PM0S電晶體之源極耦接 電壓源，其閘極耦接第一 PMOS電晶體之汲極。第三PMOS 電晶體之源極耦接電壓源，其汲極耦接第二PM0S電晶體之 汲極。第一 NMOS電晶體之源極接地，其汲極耦接第一 PM0S電晶體之汲極。第二NMOS電晶體之源極接地，其閘 極耦接第一 NMOS電晶體之汲極，其汲極耦接第二PM0S電 晶體之汲極。第三NMOS電晶體之源極耦接其閘極與接地， 其汲極耦接第三;PM0S電晶體之汲極與第二NMOS電晶體 之汲極。控制邏輯耦接第一 PM0S電晶體、第三PM0S電晶 體、第一 NMOS電晶體之閘極，用以控制第一 PM0S電晶 體、第三PM0S電晶體、第一 NMOS電晶體之開關。 經濟部智慧財產局員工消費合作社即製 依照本發明之架構，可有效地減少晶體振盪器焊墊的數 量，藉以減低AS1C元件庫的10數量，以達到降低成本花 費的目的。本發明不僅能有效地改善振盪線路的執行效 能，使得產品更具有彈性，而且更具有快速開啓與低功率 耗損的優點。 此外，應用本發明的架構，當電路在測試CDM ESD時， 本紙張尺度適用中國國家標準（CNS ) A4規格U10X 297公釐） 4383lwf. tlo^/005 A7 B7_________ 五、發明説明（^) f請先閑讀背面之注意事項再填寫本頁} 流入之ESD將可經由第三PMOS電晶體或第三NMOS電晶 體放電，以避免受到ESD的損害。因此，本發明更可以有 效地幫助產品在測試C D M E S D的情況之下’幫助散去聚集 在基底上的電荷，使得此振盪器焊墊能通過CDM ESD測 試。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式’作詳細說 明如下： 圖式之簡單說明： 第1圖繪示的是習知一般CMOS晶體振盪架構的電路 圖； 第2圖繪示的是依照本發明一較佳實施例的一種通用 晶體振盪輸出入電路的基本架構圖； 第3圖繪示的是依照本發明一較佳實施例之控制邏輯 的示意圖； 第4圖繪示的是依照本發明一較佳實施例之以本發明 之架構取代兩個傳統晶體振盪器焊墊的示意圖； 經濟部智慧財產局員工消費合作社即製 第5圖繪示的是依照本發明另一較佳實施例之以本發 明之架構取代4個傳統晶體振盪器焊墊的示意圖；以及 第6圖繪示的是依照本發明再一較佳實施例之以本發 明之架構取代I6個傳統晶體振盪器焊墊的示意圖。 圖式之標號說明：The reason is that the crystal itself provides a very high quality factor (Q) 使得, so that we can get a very stable frequency signal with a simple circuit now. However, with the progress of the times, a set of ASIC component libraries often has many crystal oscillator pads, which has caused problems for ASIC managers and ASIC designers. Please refer to the figure 1 of the brother, which can not draw a circuit diagram of a conventional complementary metal-oxide-semiconductor crystal (hereinafter referred to as CMOS) crystal oscillation architecture. As shown in Figure 1, it includes a P-type metal-oxide semiconductor (hereinafter referred to as PMOS transistor) 12, an N-type metal-oxide semiconductor (hereinafter referred to as NMOS transistor) 14, a feedback resistor 16 and a Crystal oscillator 18. The PMOS transistor Ϊ2 and the NMOS transistor 14 are equivalent to a CMOS transistor 15 and are also the same inverter as an amplifying unit. The CMOS transistor I5 is built inside the ASIC 10. The feedback resistor 16 is used to determine the operating point of the CMOS transistor 15, that is, to provide the bias voltage required by the circuit. The crystal oscillator 18 is used to limit the frequency. Traditionally, a set of ASIC component libraries need to use multiple oscillators 10, so the cost is high. In addition, if it is not possible to provide multiple component drive sizes optimized by different supply voltage sources in one oscillator 10, it will not be able to provide different customer design requirements, for example: some customers will require Voltage drop, for example, from 3.3 volts (V) to 2.4V or 1.5V. In addition, CDM ESD is becoming more and more common in VLSI. According to the traditional architecture, when conducting CDM ESD test, the electrical paper size collected on the substrate cannot be effectively dissipated. The Chinese paper standard (CNS) A4 specification (210X297 mm) ----- ^- -.I Install ------ Order ------ Prepare (Please read the precautions on the back before filling this page) 4383twf.doc / 〇05 A7 B7 V. Description of the invention (present) The ability to protect the oscillator IO is not good, and the oscillator 10 is easily damaged. (Please read the precautions on the back before filling this page.) In view of this, the present invention proposes a universal crystal oscillation input / output circuit that strengthens CDM ESD protection. It is built inside a special application integrated circuit. It is made by the first PMOS A transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and control logic. The connection relationship is that the source of the first PM0S transistor is coupled to the voltage source. The source of the second PMOS transistor is coupled to a voltage source, and its gate is coupled to the drain of the first PMOS transistor. The source of the third PMOS transistor is coupled to the voltage source, and its drain is coupled to the drain of the second PMOS transistor. The source of the first NMOS transistor is grounded, and its drain is coupled to the drain of the first PMOS transistor. The source of the second NMOS transistor is grounded, its gate is coupled to the drain of the first NMOS transistor, and its drain is coupled to the drain of the second PMOS transistor. The source of the third NMOS transistor is coupled to its gate and ground, and its drain is coupled to the third; the drain of the PMOS transistor and the drain of the second NMOS transistor. The control logic is coupled to the gates of the first PM0S transistor, the third PM0S transistor, and the first NMOS transistor to control the switches of the first PM0S transistor, the third PM0S transistor, and the first NMOS transistor. According to the structure of the present invention, the number of crystal oscillator pads can be effectively reduced, thereby reducing the number of AS1C component libraries by 10 to achieve the purpose of reducing costs. The invention can not only effectively improve the execution performance of the oscillating circuit, make the product more flexible, but also have the advantages of fast opening and low power consumption. In addition, using the framework of the present invention, when the circuit is testing CDM ESD, the paper size is applicable to the Chinese National Standard (CNS) A4 specification U10X 297 mm) 4383lwf. Tlo ^ / 005 A7 B7_________ V. Description of the invention (^) f Please Please read the precautions on the back before filling this page} The incoming ESD will be discharged through the third PMOS transistor or the third NMOS transistor to avoid damage from ESD. Therefore, the present invention can more effectively help the product to help dissipate the charge accumulated on the substrate under the condition of testing CDM ESD, so that the oscillator pad can pass the CDM ESD test. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings' as follows: Brief description of the drawings: Figure 1 Shown is a circuit diagram of a conventional general CMOS crystal oscillation architecture; FIG. 2 shows a basic architecture diagram of a general-purpose crystal oscillation input / output circuit according to a preferred embodiment of the present invention; and FIG. 3 shows a circuit diagram according to the present invention. Schematic diagram of control logic of a preferred embodiment of the invention; Figure 4 shows a schematic diagram of replacing two traditional crystal oscillator pads with the structure of the invention according to a preferred embodiment of the invention; Intellectual Property Bureau of the Ministry of Economic Affairs Figure 5 shows a schematic diagram of replacing the 4 traditional crystal oscillator pads with the structure of the present invention according to another preferred embodiment of the present invention; and FIG. 6 shows a schematic diagram according to the present invention. Another preferred embodiment is a schematic diagram of replacing the six conventional crystal oscillator pads with the structure of the present invention. Description of the symbols of the drawings:
10、20 : ASIC 12、22 ' 24、26 : PMOS 電晶體 本紙張又度適用中國國家檩芈（CNS ) Μ规格（2i0 Χ^7公釐） 經濟部智慧財產局員工消費合作杜印製 五、發明説明（Γ) 14、28、30、32 : NMOS 電晶體 15 : CMOS電晶體 16、38 :回授電阻 18、40 :晶體振盪器 34、36 :傳輸閘 50 :控制邏輯 6〇、70 : 80 :本發明之架構 62、64、72、74、76、78、82、84、86、88 :傳統之架 構 . 實施煙_ 請同時參照第2圖及第3圖，第2圖繪示的是依照本發 明一較佳實施例的一種通用晶體振盪輸出入電路的基本架 構圖，以及第3圖繪示的是依照本發明一較佳實施例之控 制邏輯的示意圖。 如第2圖所示，其包括PM0S電晶體22、24與26、NMOS 電晶體28、3〇與32、傳輸閘34與36、回授電阻38以及 晶體振盪器40，其中PMOS電晶體22、24與26、NM0S 電晶體28、3〇與32’以及傳輸閘34與36係建構在ASIC 20 的內部，其中傳輸閘34與36可由PMOS電晶體所組成， 或由NMOS電晶體所組成，或由PMOS電晶體與NMOS電 晶體所組成。回授電阻38係用以提供電路所需之偏壓’而 晶體振盪器40則用來限制頻率。PMOS電晶體26與NM0S 電晶體32係用來做爲人體放電路徑模式(HBM)靜電放電保 護之用，而NM0S電晶體28與傳輸閘36係用來做爲充電 本紙張尺度適用中國國家樣準（CNS ) A4规格（210 X 297公釐〉 ---------- Γ.裝-- - V (請先閲讀背面之注意事項再填寫本頁) 訂 4 3 93 5 1 ' 4383twfrd〇c/005 B7 五、發明説明（l ) 元件模式靜電放電保護之用。 接著如第3圖所示，控制邏輯（Control Logic)50用以接 收邏輯輸入信號E與EB，並輸出對應邏輯輸入信號E與 EB之邏輯輸出信號01、02與03，其中邏輯輸入信號E、 .EB與邏輯輸出信號01、02與03之相對關係，如下列附 表一所示。舉例來說，當邏輯輸入信號E與EB之邏輯値分 別爲0、0時，則邏輯輸出信號01、02與03之邏輯値分 別爲0、0、：1，此時將使得第2圖之PM0S電晶體22與26 以及NM0S電晶體2S都爲”開”(on)，而傳輸閘34與36則 爲”關 ”(〇ff)。 --------------裝— (請先閱讀背面之注意事項再填寫本頁) E EB 01 02 03 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 附表 -訂 Μ 經濟部智蒽財產局員工消費合作社印製 請再參照第2圖、第3圖及附表一，本發明之操作原理 將如下所述。 當邏輯輸入信號E與EB之邏輯値分別爲0、〇時，貝ij 邏輯輸出信號01、02與03之邏輯値分別爲0、〇、1，使 得PM0S電晶體；22與26以及NM0S電晶體28都爲”開”， 而傳輸閘34與36則爲，，關”，此時電路相當於一反及閘 (NAND Gate)之功倉g。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公漦） A7 B7 4 3 93 5 1 4383lwf.doc/005 五、發明説明（q〉 當邏輯輸入信號E與EB之邏輯値分別爲0、1時，則 邏輯輸出信號〇1、02與03之邏輯値分別爲1、〇、1 ’使 得PMOS電晶體26爲，，關”’PMOS電晶體22爲”開”，NM0S 電晶體28爲”開”，而傳輸閘34與36則爲”關”’此時電路 處於三態模式（tri-state mode)下，可應用在時序信號由外部 輸入至晶片內部，例如測試狀態時° 當邏輯輸入信號E與EB之邏輯値分別爲1、0時，則 邏輯輸出信號〇〗、02與03之邏輯値分別爲1、1、0，使 得PMOS電晶體22與26以及NMOS電晶體28都爲”關”， 而傳輸閘34與36則爲”開”’此時電路相當於一反相器（NOT Gate)之功能。 當邏輯輸入信號E與EB之邏輯値分別爲1、1時，則 邏輯輸出信號Ο1、02與03之邏輯値分別爲1、0、]，使 得PMOS電晶體26爲”關”，PMOS電晶體22爲，，開”，NMOS 電晶體28爲開”，而傳輸閘34與36則爲”關”，同樣地電 路係處於三態模式下’可應用在時序信號由外部輸入至晶 片內部，例如測試狀態時。 因此，依照本發明之架構，可以有效地減少ASIC元件 庫的晶體振盪器焊墊的數量，例如：以一個本發明之架構， 將可以取代掉兩個傳統晶體振盪器焊墊，如第4圖所繪示， 其中標號60爲本發明之架構，而標號62與64爲傳統之架 構。 若本發明再加上內部回授電阻的話，亦即將第2圖之回 授電阻建構在ASIC 20的內部，則—個本發明之架構將 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） I--------!:裳------訂------線 - (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 經濟部智葸財產局員工消費合作社印製 4 3 93 - 1 43S3twf.doc/00 5 B7 ---------------------- "~' 五、發明説明U ) 可取代掉四個傳統晶體振盪器焊墊’如第5圖所繪示’其 中標號70爲本發明之架構，而標號72、74、76與78爲傳 統之架構。另外，振盪器之邏輯輸入信號FEB係用來控制 ASIC 20內部之回授電阻38的開關。 另一方面，若本發明再加上不同推力（事實上’根據不 同的外在條件與頻率需求，其增益係由不同的推力來決定 的），其中上述外在條件包括爲因應不同客戶設計的需求， 例如從3.3伏特（V)降至2.4V或降至1.SV等降電壓情形。 假設我們在10MHz、20MHz、30MHz、40MHz各調整一個 增益的尺寸的話，則一個本發明之架構將可取代掉4X4 = 16 個傳統晶體振盪器焊墊，如第6圖所示，其中標號84、 86與88各包含有第5圖所示之標號72、74·、76與78，而 標號 82、84、86 與 88 分別係做爲 10MHz、20MHz、30MHz、 4〇MHz之用，其中推力範圍的選擇將由標號80中之兩控制 信號源SO、S1完成。 控制邏輯單元（如第6圖所示之振盪器）的選擇腳位 S0、S1將不僅限於S0、S1兩隻腳，亦即若只有S0、S1， 則可以獲得22M種推力範圍。若有SO、SI、S2，則有23 = 8 種推力範圍選擇。並且，SO、SI、S2組合而成的選擇項將 不限定於不同推力，亦可包括不同邏輯，例如可以用來過 濾雜訊的史密特觸發邏輯（Schmitt Trigger Logic)。例如說， so、SI、S2有8種不同選項組合而成，其中4種是不同推 力反閘，而另外4種是不同推力的史密特觸發閘。 因此，本發明將可有效地把晶體振盪器焊墊的數量，大 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X297公釐） ---------裝------訂------氣 (請先閲讀背面之注意事項再填窝本頁) A7 B7 43S3twf. doc/005 五、發明説明（f ) (請先閲讀背面之注意事項再填寫本頁) 幅減少至一或二個，藉以減低ASIC元件庫的1〇數量，使 得ASIC使用者和ASIC管理者都將獲得實際上的便利。此 外，依照本發明的架構，不僅能有效地改善振盪線路的執 行效能，讓ASIC設計者獲得更多在設計上的便利性，使得 .產品的彈性更加突顯，而且更具有怏速開啓與低功率耗損 的優點。 另外，應用本發明的架構，當電路在測試CDMESD時， 流入之ESD將可經由第2圖所示之傳輸閘36之NMOS電 晶體或NMOS電晶體28放電，以避免受到ESD的損害。 故，本發明將有效地幫助產品在測試CDM ESD的情況之 下’幫助散去聚集在基底上的電荷，使得此振盪器焊墊能 通過CDM ESD測試。並且，本發明亦可達到習知 PIOS(Programmable IO on Silicon)的優點。 而且，根據模擬的結果，本發明之架構與傳統架構相比 較之下，在同權的驅動能力下，所造成的頻率推力與負電 阻値幾乎完全相同。因此，本發明之架構將可有效地取代 傳統架構，而不須像傳統架構一樣，需要使用到多個振盪 器ίο =故可以大大地降低成本花費。 經濟部智慧財產局員工消費合作社印" 綜上所述，本發明具有以下的優點：10, 20: ASIC 12, 22 '24, 26: PMOS transistor This paper is again suitable for China's National Standard (CNS) M specification (2i0 x 7 mm). Description of the invention (Γ) 14, 28, 30, 32: NMOS transistor 15: CMOS transistor 16, 38: feedback resistor 18, 40: crystal oscillator 34, 36: transmission gate 50: control logic 60, 70 : 80: Architecture 62, 64, 72, 74, 76, 78, 82, 84, 86, 88 of the present invention: Traditional architecture. Implementation of smoke _ Please refer to Figure 2 and Figure 3 at the same time, Figure 2 shows What is shown is a basic architecture diagram of a general-purpose crystal oscillation input / output circuit according to a preferred embodiment of the present invention, and FIG. 3 shows a schematic diagram of control logic according to a preferred embodiment of the present invention. As shown in FIG. 2, it includes PMOS transistors 22, 24 and 26, NMOS transistors 28, 30 and 32, transmission gates 34 and 36, feedback resistor 38 and crystal oscillator 40, among which PMOS transistor 22, 24 and 26, NMOS transistors 28, 30 and 32 ', and transmission gates 34 and 36 are built in the ASIC 20, wherein the transmission gates 34 and 36 may be composed of a PMOS transistor or an NMOS transistor, or It is composed of PMOS transistor and NMOS transistor. The feedback resistor 38 is used to provide the required bias voltage 'of the circuit and the crystal oscillator 40 is used to limit the frequency. PMOS transistor 26 and NMOS transistor 32 are used for human body discharge path mode (HBM) electrostatic discharge protection, while NMOS transistor 28 and transmission gate 36 are used for charging. This paper is applicable to Chinese national standards. (CNS) A4 specification (210 X 297 mm) ---------- Γ.Packing--V (Please read the precautions on the back before filling this page) Order 4 3 93 5 1 '4383twfrd 〇c / 005 B7 V. Description of the Invention (l) For electrostatic discharge protection in component mode. Then, as shown in Figure 3, Control Logic 50 is used to receive logic input signals E and EB and output corresponding logic inputs. The logical output signals 01, 02, and 03 of the signals E and EB, among which the relative relationship between the logical input signals E, .EB and the logical output signals 01, 02, and 03 are shown in the following Table 1. For example, when the logic input When the logic 値 of the signals E and EB are 0 and 0 respectively, the logic 値 of the logic output signals 01, 02, and 03 are 0, 0, and 1: respectively. At this time, the PM0S transistors 22 and 26 in FIG. 2 and The NM0S transistor 2S is “on”, and the transmission gates 34 and 36 are “off” (〇ff). -------------- (Please read the notes on the back before filling this page) E EB 01 02 03 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 For printing by consumer cooperatives, please refer to Figures 2 and 3 and Schedule 1. The operation principle of the present invention will be described as follows. When the logical input signals E and EB of logic 値 are 0 and 0, respectively, ij logic output The logic 値 of signals 01, 02, and 03 are 0, 0, and 1, respectively, so that the PM0S transistor; 22 and 26 and NMOS transistor 28 are both "on", and transmission gates 34 and 36 are, "off", this The time circuit is equivalent to the power warehouse g of the NAND Gate. This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 cm) A7 B7 4 3 93 5 1 4383lwf.doc / 005 V. Description of the invention (Q) When the logic 値 of the logic input signals E and EB are 0 and 1, respectively, the logic 値 of the logic output signals 〇1, 02, and 03 are 1, 0, and 1 'respectively, so that the PMOS transistor 26 is "'PMOS transistor 22 is" ON ", NMOS transistor 28 is" ON ", and transmission gates 34 and 36 are" OFF ". At this time, the circuit is in a three-state mode. (Tri-state mode), it can be applied to the timing signal from the external input to the chip, for example, in the test state ° When the logic input signal E and EB logic 値 are 1, 0, the logic output signal 〇〗, 02 The logic 値 of 03 is 1, 1, 0, so that PMOS transistors 22 and 26 and NMOS transistor 28 are both "off" and transmission gates 34 and 36 are "on". Phaser (NOT Gate) function. When the logic 値 of the logic input signals E and EB are 1, 1, the logic 値 of the logic output signals 〇1, 02, and 03 are 1, 0, respectively], so that the PMOS transistor 26 is "off", and the PMOS transistor 22 is, “on”, NMOS transistor 28 is “on”, and transmission gates 34 and 36 are “off”. Similarly, the circuit is in the tri-state mode. 'It can be applied to the timing signal from the external input to the chip, such as When testing status. Therefore, according to the structure of the present invention, the number of crystal oscillator pads of the ASIC component library can be effectively reduced. For example, with one structure of the present invention, two conventional crystal oscillator pads can be replaced, as shown in FIG. 4 As shown, reference numeral 60 is a framework of the present invention, and reference numerals 62 and 64 are traditional frameworks. If the present invention is coupled with an internal feedback resistor, that is, the feedback resistor of FIG. 2 is built in the ASIC 20, then the framework of the present invention applies this paper size to the Chinese National Standard (CNS) A4 specification (210X297). Mm) I -------- !: Shang ------ Order ------ line- (Please read the precautions on the back before filling out this page} Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Cooperatives printed by the Ministry of Economics and Intellectual Property Bureau Employees Cooperatives 4 3 93-1 43S3twf.doc / 00 5 B7 ---------------------- " ~ 'V. Description of the invention U) Can replace four traditional crystal oscillator pads' as shown in Figure 5' where the number 70 is the structure of the invention, and the numbers 72, 74, 76 and 78 are the traditional structure . In addition, the logic input signal FEB of the oscillator is used to control the switch of the feedback resistor 38 inside the ASIC 20. On the other hand, if the present invention is coupled with different thrusts (in fact, 'the gain is determined by different thrusts according to different external conditions and frequency requirements), where the external conditions include those designed for different customers Demand, such as dropping from 3.3 volts (V) to 2.4V or 1.SV. Assuming that we adjust the size of a gain at 10MHz, 20MHz, 30MHz, and 40MHz, an architecture of the present invention can replace 4X4 = 16 traditional crystal oscillator pads, as shown in Figure 6, where the numbers 84, 86 and 88 each include the numbers 72, 74, 76, and 78 shown in Figure 5, and the numbers 82, 84, 86, and 88 are used for 10MHz, 20MHz, 30MHz, and 40MHz, respectively. The thrust range The selection of the signal will be completed by two control signal sources SO, S1 in reference numeral 80. The selection pins S0 and S1 of the control logic unit (such as the oscillator shown in Figure 6) will not only be limited to the two pins of S0 and S1, that is, if there are only S0 and S1, 22M thrust ranges can be obtained. With SO, SI, S2, there are 23 = 8 thrust range options. In addition, the combination of SO, SI, and S2 will not be limited to different thrusts, and may include different logic, such as Schmitt Trigger Logic, which can be used to filter noise. For example, there are 8 different options for so, SI, and S2, 4 of which are reverse thrust brakes of different thrust, and the other 4 are Schmitt trigger brakes of different thrust. Therefore, the present invention can effectively convert the number of crystal oscillator pads. The large paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X297 mm) --------- installation ---- --Order ------ Qi (please read the notes on the back before filling in this page) A7 B7 43S3twf.doc / 005 V. Description of the invention (f) (Please read the notes on the back before filling in this page ) To reduce to one or two, thereby reducing the number of ASIC component libraries by 10, so that ASIC users and ASIC managers will get practical convenience. In addition, the architecture according to the present invention can not only effectively improve the execution performance of the oscillating circuit, but also allow ASIC designers to gain more convenience in design, so that the flexibility of the product is more prominent, and it has a fast turn-on and low power. Attrition advantages. In addition, with the architecture of the present invention, when the circuit is testing CDMESD, the incoming ESD can be discharged through the NMOS transistor or NMOS transistor 28 of the transmission gate 36 shown in FIG. 2 to avoid damage from ESD. Therefore, the present invention will effectively help the product in the case of testing the CDM ESD to help dissipate the charge accumulated on the substrate, so that the oscillator pad can pass the CDM ESD test. In addition, the present invention can also achieve the advantages of the conventional PIOS (Programmable IO on Silicon). Moreover, according to the simulation results, compared with the traditional architecture, the frequency thrust and the negative resistance 在 caused by the driving power of the same weight are almost the same. Therefore, the architecture of the present invention can effectively replace the traditional architecture without the need to use multiple oscillators like the traditional architecture, so the cost can be greatly reduced. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs " In summary, the present invention has the following advantages:
(1) 可有效地大幅減少晶體振盪器焊墊的使用數量，藉 以減低ASIC元件庫的IO數量，使得ASIC使用者和ASIC 管理者都將獲得實際上的便利，同時能大大地降低成本花 費。 (2) 能有效地改善振盪線路的執行效能，讓ASIC設計 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） β ^ Ί 1 ' 43 S3twr.doc/005 A7 Β7 五、發明説明（/〇 者獲得更多在設計上的便利性，使得產品更具有彈性。 (3) 可有效地幫助產品在測試CDM ESD的情況之下， 幫助散去聚集在基底上的電荷，使得振盪器焊墊能通過 CDM ESD 測試。 (4) 可達到習知PIOS的優點，而且更具有快速開啓與 低功率耗損的優點。 雖然本發明已以較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍內，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者爲準。 (請先閎讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS > A4規格（210 X 2.97公釐）(1) Can effectively reduce the number of crystal oscillator pads used, thereby reducing the IO number of ASIC component libraries, so that ASIC users and ASIC managers will get practical convenience, while greatly reducing costs. (2) Can effectively improve the execution performance of the oscillating circuit, so that the ASIC design paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) β ^ Ί 1 '43 S3twr.doc / 005 A7 Β7 V. Invention Note (/ 〇 will get more convenience in design, making the product more flexible. (3) can effectively help the product under the test of CDM ESD, help to dissipate the charge accumulated on the substrate, so that oscillation The soldering pad of the device can pass the CDM ESD test. (4) The advantages of the conventional PIOS can be achieved, and it also has the advantages of fast turn-on and low power consumption. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit The present invention, anyone skilled in the art, can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. Please read the notes on the back before filling out this page) The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to Chinese national standards (CNS > A4 size (210 X 2.97 mm)