^ 4443 53 3244twf.doc/006 八7 B7 經濟部中央樣準局貝工消費合作社印装 五、發明説明（t) . 本發明是有關於一種節點接觸窗（node contact)的製 ‘造方法，且特別是有關於一種動態隨機存取記憶體（DRAM) 中節點接觸窗的製造方法。 在半導體製程逐漸邁入0.25μιη尺寸時，在動態隨機存 取記憶體的製程中，不論是字元線（word line) '位元線 (bit line)與接點接觸窗的寬度，以及接點接觸窗至字元 線、位元線的距離，都得隨著設計規則（design rule)縮 小。第1圖所示，爲一種動態隨機存取記憶體記憶胞俯視 圖，其中主動區100由場氧化層102定義出，字元線104 和位元線106係垂直相交排列在半導體基底上，而字元線 104和位元線106重疊區108以介電層（未繪出）上下隔 離，另外，在字元線104側邊的半導體基底摻有雜質，作 爲源極ll〇a與汲極區110b，而電容（未繪出）則以一導電 層由源極區110a中之節點接觸窗112接出。 第2a圖爲第1圖線I-Ι之側視剖面圖，第2b圖爲第1 圖II-II之側視剖面圖。一個DRAM記憶胞的製作過程包括 利用一標準的CMOS製程，在基底200先形成場氧化層202 及閛極氧化層204 然後沉積一層大約厚2500A的複晶矽 層，再以磷離子對此複晶矽層進行摻雜，以形成字元線° 接著，在複晶矽層之上，沉積一層大約厚3000A如矽酸四 乙酯（TOES)氧化物的絕緣物質，再以一般的微影蝕刻程 序，以電漿法將複晶矽層及絕緣層蝕刻成堆疊狀，作爲_ 極206。接著，對矽基底200進行一LDD之離子植入’形 成源/汲極區208,然後再在複晶矽閘極206上沉積一層厚 3 (請先閲琦背面之注意事項再填寫本頁j .裝^ 4443 53 3244twf.doc / 006 8 7 B7 Printed by the Central Samples Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives. 5. Description of the Invention (t). The present invention relates to a method for manufacturing a node contact window. In particular, it relates to a method for manufacturing a contact window of a node in a dynamic random access memory (DRAM). As the semiconductor process gradually moves into the 0.25 μm size, in the process of dynamic random access memory, regardless of the width of the word line 'bit line' and the contact window of the contact, and the contact The distance from the contact window to the word line and the bit line must be reduced according to the design rule. Figure 1 is a top view of a dynamic random access memory memory cell. The active area 100 is defined by the field oxide layer 102. The word lines 104 and bit lines 106 are arranged on a semiconductor substrate perpendicularly to each other. The overlapping region 108 of the element line 104 and the bit line 106 is separated from each other by a dielectric layer (not shown). In addition, the semiconductor substrate on the side of the word line 104 is doped with impurities as the source 110a and the drain region 110b. The capacitor (not shown) is connected by a conductive layer through the node contact window 112 in the source region 110a. Fig. 2a is a side sectional view of Fig. 1 line I-I, and Fig. 2b is a side sectional view of Fig. II-II. The manufacturing process of a DRAM memory cell includes the use of a standard CMOS process. A field oxide layer 202 and a ytterbium oxide layer 204 are formed on the substrate 200, and then a polycrystalline silicon layer having a thickness of about 2500 A is deposited. The silicon layer is doped to form word lines. Next, on top of the polycrystalline silicon layer, a layer of approximately 3000 A thick insulating material such as tetraethyl silicate (TOES) oxide is deposited, followed by a general lithography process. , The polycrystalline silicon layer and the insulating layer are etched into a stack by a plasma method as the _ pole 206. Next, perform a LDD ion implantation on the silicon substrate 200 to form the source / drain region 208, and then deposit a layer of thickness 3 on the polycrystalline silicon gate 206 (please read the precautions on the back of the Qi before filling this page j Install
J 線- 本紙張尺度通用中國困家榇準（CNS ) 格（2丨0X297公釐） 發邊i§ §含 3 244twf.doc/006 八] B7 經濟部中央標準局負工消費合作杜印製 五、發明説明ο ) .約2000A的TOES氧化物，並以電漿對此TOES氧化餍進行 •蝕刻，以在多晶矽閘極上形成氧化物間隙壁210，並將閘 極206以一厚的氧化物介電層212覆蓋。之後，在介電層 212上形成一複晶矽層，定義成複晶矽線214，作爲位元 線。續在複晶矽線214上形成蓋氮化矽層216與氮化矽間 隙壁218，再對複晶矽線214覆蓋一介電層220與一氮化 矽層222，接著定義氮化矽層222與介零層220，利用氮 化矽間隙壁218與作爲介電層220之氧化物蝕刻選擇率的 差異，進行自動對準接觸窗（self-aligned contact，SAC) 技術，完成節點接觸窗224之蝕刻製程，而暴露出源/汲 極區20δ » 在此節點接觸窗224之蝕刻製程，若控制氮化矽/氧化 物的蝕刻選擇率較高時，則蝕刻步驟較易停止在氮化矽間 隙壁218，因此氮化矽間隙壁218具有保護位元線214的 功用，但因接觸窗224高寬比越大，使得蝕刻選擇率高時 難以將介電層212完全蝕刻，導致源/汲極區208未能暴 露出’而使後續製程無法進行β若選擇氮化矽/氧化物蝕 刻選擇率較低時，雖可進行蝕刻步驟暴露出源/汲極區 208 ’但氮化矽間隙壁218則無法發揮作爲蝕刻終點，保 護位充線214的功用，因此亦導致接觸窗224製程失敗。 有鑑於此，本發明的主要目的，就是在提供一種方法’ 係在位元線側邊的氮化矽間隙壁上提供一複晶矽間隙 壁’利用複晶矽材料/氧化物較氮化矽/氧化物爲高的蝕刻 選擇率’將複晶矽間隙壁當作蝕刻終點，藉此更保護位元 4 tii^(-CNS) Al«iT-21〇x297^ ---^-----y —裝------訂-----^線 C請先閣讀背面之注意事項再填寫本頁) 444353 經濟部中央標準局負工消費合作社印製 3244twf.doc/006 Λ7 B7 ............ — — _ -----------__ 五、發明説明（3 ) 〜"—'~一 .線。另外，藉由複晶矽間隙壁降低接觸窗軸刻高度，@胃 .蝕刻製程較易進行’因此可避免習知技藝無法完=飽刻S 電層之缺點。 爲達上述之目的’本發明提供一種自動對準節點接觸 窗的製造方法，首先在一經過前處理的半導體晶圓沉積_ 第一介電層，並在第一介電層上形成導電層線，且導電層 線側邊具有氮化矽間隙壁。接著，在導電層線上依序形g 一第二介電層與一硬材料層，並定義硬材料層與第二介電 層，再以氮化矽間隙壁爲終點，在第二介電層形成—開 口 ’而暴露出第二介電層側壁、氮化矽間隙壁與部分第一 介電層β之後，在該第二介電層開口側壁形成一複晶砂間 隙壁，並自動對準複晶矽間隙壁，而定義第一介電層，以 形成一節點接觸窗，並暴露出晶圓。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係顯示一種動態隨機存取記憶體記憶胞之俯視 圖； 第2a圖及第2b圖爲顯示根據第I圖I-Ι與ΙΙ-ΙΙ線之 側視剖面圖；以及 第3a、3b圖至第6a、6b圖係顯示根據本發明較佳實 施例節點接觸窗之製造流程剖面圖。 其中，各圖標號之簡單說明如下： 5 本紙張尺度通用中國困家標準（CNS ) A4规格（2丨0X297公釐） (請先閲讀背面之注$項再填寫本頁) 裝· 訂- ί 11 -! 4443 53 3244twf.doc/006 Λ 7 Β7 經濟部中央標準局員工消費合作杜印製 五、發明説明（夺） . 100 :主動區 102、202、302 :場氧化層 104、206、304 :字元線 106、214、310 :位元線 110a、110b、208、306 :源/汲極區 112 :節點接觸窗 200、300 :基底 204 :閘極氧化層 210、314 :氧化間隙壁 212、220、308、308a ' 316、316a、316b :介電層 216、312 :蓋氮化矽層 218 :氮化矽間矽壁 222 :氮化矽層 318、318a :硬材料層 322 :複晶矽間隙壁 實施例 第3a、3b圖至第6a、6b圖所示，爲根據本發明一較 佳實施例節點接觸窗之製造流程剖面圖，而以本實施例形 成之節點接觸窗，其俯視圖與習知相似，因此以第1圖示 之，钕圖示中，第3a圖至第6a圖與第3b圖至第6b圖係 顯示分別顯示第1圖I-Ι與II-II線之側視剖面圖。 首先，請參照第3a、3b圖，如習知技藝，提供一已經 過前處理之晶圓，包括CMOS製程，首先在基底300上形 成場氧北層30.2，並以場氧化層302定義主動區，且形成 6 C請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家揉IMCNS)A4規格（210X297公犮） 4443 53 3 244twf .doc/006 Λ7 B7 經濟部中央樣準局負工消費合作社印策 五、發明説明（ς) .有字元線304與源/汲極區306。之後’例如以化學氣相沉 ‘積法（CVD)對基底300形成一介電層308 ’且在介電層308 上形成一導電層，在定義導電層後，形成導電層線310 ’ 作爲位元線。其中介電層308例如爲硼磷矽化物，而導電 層310例如爲摻有雜質的複晶矽層》續在複晶矽線310上 形成蓋氮化矽層312與氮化矽間隙壁314 ’再對複晶矽線 310覆蓋一介電層316與一硬材料層318，硬材料層318 包括氮化矽層。 如第4a、4b圖所示，接著，定義硬材料層318a與介 電層316a，以位元線310的氮化矽間隙壁314爲蝕刻終 點，在介電層318a中形成一開口 320,暴露出介電層308、 介電層316a側壁316b與氮化矽間隙壁314。之後，在硬 材料層318a與開口 320中形成一複晶矽層’以硬材料層 318a爲蝕刻終點，回蝕刻複晶矽層’在介電層316a側壁 形成複晶矽間隙壁322,覆蓋氮化矽間隙壁314’如第5a、 5b圖所示。 續以硬材料層318a與複晶矽間隙壁322爲罩幕’蝕刻 介電層308a，暴露出字元線304之源/汲極區306 ’完成 自動對準節點接觸窗324之製程’如第6a、6b圖所示。 由於'複晶矽與作爲介電層之氧化物蝕刻選擇率較大’因此 在進行蝕刻介電層316a時’複晶矽間隙壁322可保護位 元線310，且可自動對準介電層308a而繼續進行蝕刻。而 複晶矽間隙壁322之形成’降低了接觸窗324的蝕刻高 度，使得介電層308a之蝕刻較爲容易，因此可避免習知 7 ^紙張尺度適用中國國家標率（CT&) A4规格（2丨0X297公ίΠ (請先閱讀背面之注意事項再填寫本頁) 裝-Line J-This paper is in accordance with the standards of the Chinese Standards for Households (CNS) (2 丨 0X297 mm) Hairline i§ § Including 3 244twf.doc / 006 8] B7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs V. Description of the invention ο) .TOES oxide of about 2000A, and the TOES oxide is etched with a plasma to form an oxide spacer 210 on the polycrystalline silicon gate, and the gate 206 with a thick oxide The dielectric layer 212 is covered. Thereafter, a polycrystalline silicon layer is formed on the dielectric layer 212, and is defined as a polycrystalline silicon line 214 as a bit line. Continue to form a silicon nitride layer 216 and a silicon nitride spacer 218 on the polycrystalline silicon line 214, and then cover the polycrystalline silicon line 214 with a dielectric layer 220 and a silicon nitride layer 222, and then define a silicon nitride layer 222 and dielectric zero layer 220, using the difference between the silicon nitride spacer 218 and the oxide etch selectivity of the dielectric layer 220, perform self-aligned contact (SAC) technology to complete the node contact window 224 Etch process and expose the source / drain region 20δ »In this node contact window 224 etch process, if the silicon nitride / oxide control selectivity is high, the etching step is more likely to stop at silicon nitride The spacer 218, so the silicon nitride spacer 218 has the function of protecting the bit line 214, but the larger the aspect ratio of the contact window 224 makes it difficult to completely etch the dielectric layer 212 when the etching selectivity is high, resulting in source / drain The electrode region 208 fails to be exposed 'and subsequent processes cannot be performed. If the silicon nitride / oxide etching selectivity is low, the source / drain region 208 can be exposed by an etching step, but the silicon nitride spacer is exposed. 218 cannot be used as the end point of the etch, the protection bit charge line 2 The function of 14 also causes the process of contact window 224 to fail. In view of this, the main object of the present invention is to provide a method 'providing a polycrystalline silicon spacer on the silicon nitride spacer on the side of the bit line' using a polycrystalline silicon material / oxide over silicon nitride / The oxide has a high etch selectivity rate ', taking the polycrystalline silicon spacer as the end point of the etch, thereby protecting the bit 4 tii ^ (-CNS) Al «iT-21〇x297 ^ --- ^ ---- -y —install ------ order ----- ^ line C, please read the notes on the back before filling out this page) 444353 Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 3244twf.doc / 006 Λ7 B7 ............ — — _ -----------__ 5. Description of the invention (3) ~ " — '~ 1. Line. In addition, by reducing the engraving height of the contact window axis with the polycrystalline silicon spacer, the @ stomach. Etching process is easier to perform ', so that the disadvantages of the inability to complete the conventional technique can be avoided. In order to achieve the above-mentioned object, the present invention provides a method for manufacturing an automatic alignment node contact window. First, a pre-processed semiconductor wafer is deposited with a first dielectric layer, and a conductive layer line is formed on the first dielectric layer. , And the side of the conductive layer line has a silicon nitride spacer. Then, a second dielectric layer and a hard material layer are sequentially formed on the conductive layer line, and the hard material layer and the second dielectric layer are defined, and then a silicon nitride spacer is used as an end point on the second dielectric layer. Formation-opening 'to expose the second dielectric layer side wall, the silicon nitride spacer wall and a portion of the first dielectric layer β, a polycrystalline sand spacer wall is formed on the opening side wall of the second dielectric layer and automatically aligned The polycrystalline silicon spacers define the first dielectric layer to form a node contact window and expose the wafer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 Top view of a memory cell of a dynamic random access memory; Figures 2a and 2b are side cross-sectional views showing lines I-1 and III-III in Figure I; and Figures 3a, 3b through 6a Figures 6b are cross-sectional views showing the manufacturing process of a node contact window according to a preferred embodiment of the present invention. A brief description of each icon number is as follows: 5 This paper size is in accordance with the Chinese Standard for Household Standards (CNS) A4 (2 丨 0X297mm) (please read the note on the back before filling this page). Binding-ί 11-! 4443 53 3244twf.doc / 006 Λ 7 Β7 Consumer cooperation between the Central Bureau of Standards of the Ministry of Economic Affairs and the Department of Printing 5. Invention Description (Win). 100: Active zone 102, 202, 302: Field oxide layer 104, 206, 304 : Word line 106, 214, 310: Bit line 110a, 110b, 208, 306: Source / drain region 112: Node contact window 200, 300: Substrate 204: Gate oxide layer 210, 314: Oxidation barrier 212 , 220, 308, 308a '316, 316a, 316b: Dielectric layers 216, 312: Cover silicon nitride layer 218: Silicon nitride intersilicon wall 222: Silicon nitride layer 318, 318a: Hard material layer 322: Compound Figures 3a, 3b to 6a, 6b of the embodiment of the silicon barrier wall are sectional views of the manufacturing process of a node contact window according to a preferred embodiment of the present invention, and a top view of a node contact window formed in this embodiment It is similar to the conventional one, so in the first diagram, in the neodymium diagram, Figs. 3a to 6a and 3b to 6b are shown. Do not show side cross-sectional view of FIG. 1 I-Ι with the line II-II. First, please refer to Figures 3a and 3b. According to conventional techniques, provide a wafer that has been pre-processed, including the CMOS process. First, a field oxygen north layer 30.2 is formed on the substrate 300, and the field oxide layer 302 is used to define the active area. , And 6 C, please read the notes on the back before filling in this page) This paper size is applicable to the Chinese national standard ICNS) A4 size (210X297) 犮 4443 53 3 244twf .doc / 006 Λ7 B7 Industrial and Consumer Cooperatives Co., Ltd. V. Invention Description (ς). There are word lines 304 and source / drain regions 306. Thereafter, for example, a dielectric layer 308 is formed on the substrate 300 by a chemical vapor deposition (CVD) deposition method and a conductive layer is formed on the dielectric layer 308. After the conductive layer is defined, a conductive layer line 310 'is formed as a bit Yuan line. The dielectric layer 308 is, for example, a boron-phosphorus silicide, and the conductive layer 310 is, for example, a polycrystalline silicon layer doped with impurities. Continued on the polycrystalline silicon wire 310 is a capping silicon nitride layer 312 and a silicon nitride spacer 314 ′. The polycrystalline silicon line 310 is further covered with a dielectric layer 316 and a hard material layer 318. The hard material layer 318 includes a silicon nitride layer. As shown in Figures 4a and 4b, next, the hard material layer 318a and the dielectric layer 316a are defined, and the silicon nitride spacer 314 of the bit line 310 is used as the end point of the etching. An opening 320 is formed in the dielectric layer 318a and exposed. A dielectric layer 308, a sidewall 316b of the dielectric layer 316a, and a silicon nitride spacer 314 are formed. Afterwards, a polycrystalline silicon layer is formed in the hard material layer 318a and the opening 320. With the hard material layer 318a as the etching end point, the polycrystalline silicon layer is etched back to form a polycrystalline silicon spacer 322 on the sidewall of the dielectric layer 316a, covering the nitrogen. The siliconized spacer 314 'is shown in Figs. 5a and 5b. Continue to use the hard material layer 318a and the polycrystalline silicon spacer 322 as a mask to etch the dielectric layer 308a, exposing the source / drain region 306 of the word line 304 'Completing the process of automatically aligning the node contact window 324' as described in the section 6a, 6b. Due to the 'large selectivity of polycrystalline silicon and oxide as a dielectric layer', the polycrystalline silicon spacer 322 can protect the bit line 310 and automatically align the dielectric layer when the dielectric layer 316a is etched 308a, and the etching is continued. The formation of the polycrystalline silicon spacer 322 'reduces the etching height of the contact window 324, making the etching of the dielectric layer 308a easier, so that the conventional 7 ^ paper scale can be applied to the China National Standard (CT &) A4 specification. (2 丨 0X297 公 ίΠ (Please read the precautions on the back before filling this page)
T SM§§§ 3244twf. doc/006 A7 _____B7__________ 五、發明説明（έ ) ,無法完全蝕刻介電層308a的困難。 本發明的主要特徵在於，在原來位元線既有的氮化矽 間隙壁上再提供複晶矽間隙壁，利用複晶矽/氧化物較氮 化矽/氧化物爲高之蝕刻選擇比，以複晶矽間隙壁作爲蝕 刻終點，先進行上部介電層之定義，之後，再利用複晶矽 間隙壁爲罩幕，自動對準下部介電層而蝕刻。因此，可同 時達到縮小接觸窗尺寸與完全蝕刻介電層之目的。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ---；--+-----裝------1T-----^v線 (·請先閱请背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印装 $ 本紙張尺度適用中國Η家《举（CNS ) A4現格（210><邛7公釐）T SM§§§ 3244twf. Doc / 006 A7 _____B7__________ 5. Description of the Invention (（) It is difficult to completely etch the dielectric layer 308a. The main feature of the invention is that a polycrystalline silicon spacer is provided on the existing silicon nitride spacer of the original bit line, and the polycrystalline silicon / oxide has a higher etching selection ratio than the silicon nitride / oxide. Using the polycrystalline silicon spacer as the end point of the etching, the upper dielectric layer is defined first, and then, the polycrystalline silicon spacer is used as a mask to automatically align the lower dielectric layer and etch. Therefore, the purpose of reducing the contact window size and completely etching the dielectric layer can be achieved at the same time. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ---;-+ ----- installation ------ 1T ----- ^ v line (· Please read the notes on the back before filling this page) Printed by consumer cooperatives $ This paper size is applicable to the Chinese family "CNS" A4 now (210 > < 邛 7mm)