TW448563B - Metal oxide semiconductor transistor - Google Patents

Abstract

A MOS transistor is formed on a semiconductor chip. The semiconductor chip includes a silicon substrate, an insulation layer formed on the silicon substrate, and an active region formed on a predefined region of the insulation layer. The MOS transistor includes a crystalline silicon layer formed on the insulation layer of the active region, and a trench formed on the surface of the insulation layer of the active region and passed through the bottom of the crystalline silicon layer to divide the active region into a source region and a drain region. A source conductive layer and a drain conductive layer are formed in the source region and the drain region for respectively connecting to the crystalline silicon layer. The source conductive layer and the drain conductive layer is surrounded by a spacer on the periphery respectively. A gate dielectric layer covers the surfaces of the four sides of the crystalline silicon layer above the trench. In addition, a gate dielectric layer is filled in the trench under the crystalline silicon layer, and covers the surface of the gate dielectric layer. When an initial voltage is applied on the gate conductive layer, a channel is formed on the surface layer of each of the four sides of the crystalline silicon layer to conduct the source conductive layer and the drain conductive layer.

Description

V. Description of the invention (1) Field of the invention The present invention provides a metal oxide semiconductor (MOS) transistor, especially a metal oxide semiconductor transistor which can provide four channels. i I Background Note: Metal oxide semiconducting heteroelectric crystals are the most important electronic components in today's semiconductor products. They are mainly used as switches in circuits: (switch), but with the integration degree of circuits (integrati 〇)), the current operating speed of MOS transistors has gradually fallen short of the needs of body circuit designers. Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a conventional MOS transistor 10. The MOS transistor 10 is located on the surface of a silicon substrate i 1 2 ′. The periphery of the MOS transistor Zhao 1 0 is surrounded by a field oxide layer 14 and isolated. MOS transistor 1 〇 is mainly composed of a gate

I i (gate) 16, a drain 18 and a source 20, and a gate oxide 22 between the gate 16 and the silicon substrate 12 2 » A spacer 24 'is provided around the gate 16 to isolate the gate 16, and two lightly doped drains (LDD) 26 are provided below the side wall 24 to prevent heat. Electronic effects (h ote 1 ectr ο neffects).

Page 5 448563 V. Description of the invention (2) Since the MOS transistor uses its metal-oxide-semiconductor stack Φ structure to form a M0S capacitor, when applied to M0S When the voltage on the metal layer of the capacitor is higher than a threshold voltage, the 'MOS capacitor will have a strong inversion phenomenon on the surface of the semiconductor layer. That is to say, using the relationship between the starting voltage and the strong inversion, the M0S transistor 10 can control the switching state of the M0S transistor 10 (ON / OFF) by the voltage applied by the gate 16 states) »As shown in Figure 1, M0S capacitor refers to the structure formed by gate 16-gate oxide 2 2-silicon substrate 12. i When the voltage applied to the gate 16 is less than the starting voltage, the non-electrode 18 and the source 20 are isolated, so that the switching mode of the M0S transistor 10 is " off 11. When the voltage applied to the gate 16 is greater than the starting voltage, the silicon substrate 12 under the strong i inversion mode 'will form a channel near the gate oxide layer 22 | 2 8' so that the drain 18 and the Isolation between source 20 is eliminated. Therefore, under a proper bias condition, for example, the source 20 is grounded and the drain 18 is applied with a positive voltage, the current can flow from the non-pole 18 to the source 20 through the channel 28, so that the M0S current that was originally disconnected ^ The crystal 10 becomes " on ". However, the Ϊ Γί Ϊlike plane formed under the known strong inversion mode of the M0S transistor 10 not only occupies an equivalent surface, but also has a low efficiency of current transmission. At the same time, the operation of the M0S transistor is also restricted. . Therefore, in the future, high-speed and high-accumulation component processes are required ^,

4-4856 3 V. Description of the invention (3) Knowing the bottleneck of MOS transistor, we must operate speed. SUMMARY OF THE INVENTION The present invention relates to oxidized semiconductor characteristics. The system of the present invention. On the semiconductor substrate, and on top of a M 0 S transistor, and on the bottom of a trench crystal silicon layer, the source-drain conductive layer and the non-conductive layer of the pegmatite layer are precocious spar. The gate dielectric layer table below the evening layer is respectively covered with a t 1 0. The manufacturing method and structure have been faced with applications. A new design must be used to improve the accumulation of M0S transistors and the main purpose is to provide a method that can provide four A channel of gold transistors is provided to improve the accumulation and operation of MOS transistors. A MOS transistor provided on a semiconductor wafer includes a broken substrate. An insulating layer is provided in the active area of the Shi Xiji. One of the insulating layers is on a predetermined area. The monolithic silicon layer has an insulating layer provided on the active region, and a channel is provided on the surface of the insulating layer of the active region, and passes through the unilateral side to divide the active region into a source region and a region and the drain A source conductive layer and-are connected to the single crystal silicon layer, respectively, and the source conductive layer and a side wall are respectively surrounded by the source conductive layer and the gate, and a gate electrode is covered on the four sides of the trench. Dielectric layer. In addition, the trench is further filled with a gate conductive layer and covers the surface, and the source conductive layer and the drain conductive layer have another source dielectric layer and a drain dielectric layer.

f (448 5 6 3 (… .- .. T-fit ------ ...-_ _ I --------! V. Description of the invention (4) Because of the MOS of the invention The transistor is provided with the gate dielectric layer and the gate conductive layer on the four sides of the single crystal silicon layer, so when an initial voltage is applied to the gate conductive layer, the four sides of the single crystal silicon layer A channel will be formed in the surface layer of the edge, so that the M0S transistor can control the gate channel from four directions, which can speed up the conduction of the source conductive layer and the drain conductive layer. In addition, since four channels can be formed in the surface layer of the single crystal silicon layer, the area occupied by the single crystal silicon layer can be appropriately reduced, and the accumulation degree of the semiconductor process of the present invention is greatly improved.

I

I Detailed description of the invention j As shown in FIG. 2 'FIG. 2 is a schematic diagram of a metal oxide semiconductor transistor 30 according to the present invention. The present invention provides a MOS transistor 3 provided on a semiconductor wafer 32 (the L semiconductor wafer 32 includes a silicon substrate 34, and an insulating layer 36 composed of silicon oxide is provided on the semiconductor wafer 32 Shi Xiji

On the bottom 34, and an active area 3 8 is provided on a predetermined area of the insulating layer 36j. The M0S transistor 30 includes the following components: a single crystal silicon layer 40, a trench | 42, a protective layer 44 (FIG. 2_only one of which is drawn), a source electrode Conductive layer 46, a drain conductive layer 48, a source dielectric layer 50, a drain dielectric layer | 5 2, two side walls 5 4, a gate dielectric layer 5 6 and a gate conductive layer 5 8. As shown in FIG. 3, '3 is a top view of the M0S transistor 30 in FIG. 2, and FIG. 2 only shows the relative positions of the single crystal wonderful layer 40 and the trench 42, and the remaining components

448563 I V. Description of the invention (5) and i are not shown in Figure 3. The single crystal silicon layer 40 is provided on the insulating layer 36 in the active region 38. The trench 4 2 is provided on the surface of the insulating layer 36 in the active area 38, and is cut downward from the surface of the insulating layer 36. In addition, the trench 4 2 penetrates the bottom of the monocrystalline silicon layer 40 below the active area 38 is divided into a source region 60 and one; and a pole region 62. !

I

As shown in FIG. 4, circle 4 is a schematic cross-sectional view of the MOS transistor 30 of FIG. 2 along the tangent line A-A. The single crystal silicon layer | 40 in the range of the source region 60 and the drain region 62 is covered with two protective layers 44 respectively, and source conduction is provided in the source region 60 and the drain region 62 respectively. The layer 46 and the drain conductive layer 48 allow the source conductive layer 46 and the drain conductive layer 48 to cover the surface of the insulating layer 36 and the protective layer 4 4. In addition, the source conductive layers 46 and 6 and the electrode conductive layers 4 8 and i respectively cover the source dielectric layer 50 and the drain dielectric layer 52. Among them, the protective layer 44 and the source | electrode dielectric layer 5 0 and drain dielectric layer 5 2 are mainly composed of dielectric substances (such as tritium |

Silicon), and the source conductive layer 46 and the drain conductive layer 48 are both doped polysilicon layers or other conductive materials.丨 i;! | The MOS transistor 30 is provided with two sidewalls 54 on the sidewalls of the source conductive layer 46 and the drain conductive layer 48 next to the trench 42, and the sidewalls 5 4 are due to the manufacturing process. It may also surround the remaining sidewalls of the source conductive layer 46 and the drain conductive layer 48 at the same time. The side wall member 54 is made of a dielectric substance. In the present invention, the 'side wall member 54 is made of a silicon nitride (Si 3N 4).

Page 9 4 4 8 5 6 3 V. Description of the invention (6) As shown in the fifth figure, FIG. 5 is a schematic cross-sectional view of the MOS transistor 30 of FIG. 2 along the tangent line B-B. In the present invention, the gate dielectric layer 56 is the exposed four-sided surface of the single crystal silicon layer 40 over the trench 42, and the gate conductive layer 58 fills the entire trench 42 and covers the entire surface of the trench 42. The surface of the gate dielectric layer 56. That is, the periphery of the single crystal silicon layer 40 is surrounded by the gate dielectric layer 56 and the gate conductive layer 58 | to form a wrap-around MOS capacitor. When the voltage applied by the gate conductive layer 58 is greater than the starting voltage, four channels 64 will be formed in the surface layer of the single crystal silicon layer 40 adjacent to the four sides, thereby conducting the source conductive layer 46 and the drain conductive layer 48. The gate dielectric layer 56 of the MOS transistor 30 is a silicon dioxide (SiO 2) layer, and the gate conductive layer 58 is a doped polycrystalline silicon layer or other conductive material. Please refer to FIG. 6 To FIG. 13, FIGS. 6 to 13 are schematic diagrams of a process for forming the MOS transistor 30 of the present invention. As shown in FIG. 6, the MOS transistor 30 of the present invention first uses a film deposition, lithography, and silver etching process to sequentially form a single unit on the active region 38 of the semiconductor wafer 32. A crystalline silicon layer 40 and a protective layer 44 made of silicon oxide. Next, as shown in FIG. 7, a method of forming a doped polycrystalline silicon layer 4 7 β on the surface of the semiconductor wafer 32 and forming the doped polycrystalline silicon layer 47 is performed simultaneously in a chemical vapor deposition (CVD) process. After injecting a dopant-containing gas, the polycrystalline silicon layer can be formed first, and then the polycrystalline silicon layer is doped by an ion implantation (i on i mp 1 antat i on) process.

Page 10 448 56 3 I V. Description of the invention (7) — As shown in FIG. 8 'After the doped polycrystalline silicon layer 47 is formed, a chemical mechanical polishing (CMP) process is performed' or other The planarization process makes the top of the doped polycrystalline silicon layer 47 | relatively flat, and then forms a silicon oxide on the surface of the doped polycrystalline silicon layer 47 | Guang 51. The chemical mechanical polishing process or the planarization process may be omitted depending on the subsequent processes and other factors. ί! As shown in FIG. 9 'Next, a yellow light and etching process is used, and the | protective layer 44 is used as a hard mask to remove the doped polycrystalline silicon layer outside the active area 38 4 7 The silicon oxide layer 51 and the silicon oxide layer 51 define the source conductive layer 46, the drain conductive layer 48, the source dielectric layer 50, and the drain dielectric layer 52's patterns. As shown in FIG. 10, after the production of the source and the drain is completed, the protective layer 4 4 between the source conductive layer 46 and the drain conductive layer 48 is removed first, and then the source conductive layer 4 6 is removed. Side walls 5 4 made of silicon nitride i are formed on the peripheral sidewalls of the drain conductive layer 48. Among them, the present invention may also first form the side walls 5 4 | before removing the protective layer i 丨 44 between the source conductive layer 46 and the non-electrode conductive layer 48. i

I j 丨 as shown in the figure-, then the trench 42 is produced. First apply 钸 —i photoresist (not shown) to define the pattern of the trench 4 2 and then use —buffered oxide oxide #etching liquid (buffered oxide etcher, boe) to etch the insulation 丨 丨 layer 3 6 ^ 向 向The insulation between the source conductive layer 4 6 and the drain conductive layer 4 8

448 56 3 V. Description of the invention (8) The edge layer 36 and the insulating layer 36 under the bottom of the single-crystal silicon layer 40 are removed at the same time, thereby forming a trench-shaped trench 42 «and finally removing the photoresist completely. As shown in Fig. 12, the gate dielectric layer 56 is then manufactured, and a high temperature thermal oxide process is used to uniformly form a thickness of about 20 angstroms on the exposed surface around the single crystal silicon layer 40. (Angstrom, &) gate dielectric layer 56 »then uses a CVD process and simultaneously introduces a dopant-containing gas 'to form a doped polycrystalline silicon layer 5 7' and fills the doped polycrystalline silicon layer 5 7 The trenches 42, especially the trenches 42 under the single crystal silicon layer 40, must ensure that no voids are generated. Finally, the pattern of the gate conductive layer 58 is defined by a yellow light and etching process, and the fabrication of the MOS transistor 30 shown in FIG. 4 is completed. Please refer to FIG. 14. FIG. 14 is a top view of an active region 38 of a transistor 30 according to another embodiment of the present invention. In order to simplify the illustration, FIG. 14 only shows a single crystal silicon layer 40, a trench 42, and a source. The relative relationship between the positions of the electrode conductive layer 46 and the drain conductive layer 48. As shown in FIG. 14, the source conductive layer 46 and the drain conductive layer 48 are respectively disposed on a part of the source region 60 and the drain region 62, and the source conductive layer 46 and the drain The pole conductive layer 48 is not covered on the surface of the single crystal evening layer 40. The side wall on the right side of the source conductive layer 46 is connected to the side wall on the left end of the monocrystalline stone layer 40, and the drain conductive layer 48 is formed into a concave-like structure to connect with the single crystal silicon layer 40. The connection methods of the source conductive layer 46, the non-electrode conductive layer 48 and the single crystal silicon layer 40 can be interchanged left and right or the same connection method can be used. It is even possible to design the source conductive layers 46 and drains of different geometric shapes according to different conditions Electrode conductive layer 48, as long as the source is ensured

Page 12 448563 V. Description of the invention (9) The conductive layer 46 and the non-polar conductive layer 48 have good contact with the single crystal silicon layer 40.

In order to electrically connect the three together. J The MOS transistor 30 of the present invention is characterized in that a gate dielectric layer 56 and a gate conductive layer 58 are provided on the periphery of the single crystal silicon layer 40, thereby forming an approximately tubular MOS capacitor. Therefore, the formation of the channel 64 can be controlled by the μ 0 S transistor 30 in four directions, and when the MOS transistor 30 is in the “on” state, four planar channels 64 can be formed, thereby increasing the efficiency of current transmission. Therefore, the MOS capacitor structure of the present invention can greatly reduce the area occupied by the MOS transistor 30, and can be applied to electronic components with high speed and high integration. Compared with the conventional MOS transistor 1 〇, the MOS transistor 30 of the present invention can form four planar channels 64, while the MOS transistor 10 can only form one planar channel 28. Therefore, in terms of the efficiency of current transmission and the control of the channels, Better than MOS transistor 1 0. In addition, the width of each channel 64 of the I MOS transistor 30 is almost only the channel 28 with respect to the channel length of the same length (between the source and the drain). Therefore, the MOS transistor 30 can reduce the occupied area, thereby increasing the integration degree of the MOs transistor 30. The above description is only the preferred embodiment of the present invention. Range doing Changes and modifications also belong to the scope of the present invention patent.

Page 13 4 4 8 5 6 3 Brief description of the diagram Brief description of the diagram Circle 1 is a schematic cross-sectional view of a conventional MOS transistor. FIG. 2 is a schematic diagram of a metal oxide semiconductor transistor according to the present invention. FIG. 3 is a top view of the MOS transistor of FIG. 2. FIG. 4 is a schematic cross-sectional view of the M 0 S transistor of FIG. 2 along the tangent line A-A. FIG. 'Figure 5 is a schematic cross-sectional view of the MOS transistor of Figure 2 along the tangent line B-B. FIG. 6 to FIG. 13 are schematic diagrams of a process for forming a MOS transistor of the present invention. Fig. 14 is a top view of an active region of a MOS transistor according to another embodiment of the present invention; Symbol description

10 MOS transistor 12 Silicon substrate 14 Field oxide layer 16 Gate 18 Drain 20 Source 22 Gate oxide layer 24 Side wall 26 LDD 28 Channel 30 MOS transistor 32 Semiconductor wafer 34 Silicon substrate 36 Insulating layer 38 Active area 40 Single Crystalline silicon layer 42 trench 44 protective layer 46 source conductive layer 47 doped polycrystalline silicon layer ^ 448563

Page 15 48 Drain conductive layer 50 Source dielectric layer 51 Oxide layer 52 Drain dielectric layer 54 Side wall 56 Gate dielectric layer 57 Doped polycrystalline silicon layer 58 Gate conductive layer 60 Source region 62 Drain 1¾ 64 channels

Claims (1)

448 5 6 3 Six 'application patent scope 1. A metal-oxide semiconductor (MOS) transistor provided on a semiconductor wafer, the semiconductor wafer includes a silicon substrate, an insulating layer It is disposed on the broken substrate and an active area is disposed on a predetermined area of the insulating layer. The MOS transistor includes: a single crystal silicon layer disposed in the active area On the insulating layer; a trench is provided in the active region and passes through the bottom of the monocrystalline layer, and the active region is divided into a source region and a liquid region; a source electrode A conductive layer and a drain conductive layer are respectively disposed in the source region and the drain region, and are respectively connected to the single crystal silicon layer; a source dielectric layer and a drain dielectric layer are respectively covered On the source conductive layer and the drain conductive layer; two spacers surround the source conductive layer and the non-conductive layer respectively; and a gate dielectric layer is coated Four of the single crystal silicon layer above the trench The side i surface; and an intervening electrode conductive layer 'fills the trench below the single crystal silicon layer and covers the surface of the gate dielectric layer; wherein when the voltage applied to the gate conductive layer is greater than the threshold voltage (threshold voltage), four channels are formed in the surface layer of the single crystal silicon layer adjacent to the four sides, and the source conductive layer and the non-polar conductive layer are conducted. No. 6 page 4 4 8 5 6 3 VI. Application scope of patent 2. For example, if the MOS transistor of item 1 of the scope of patent application is applied, the middle layer or the drain conductive layer covers part I of the single crystal silicon layer 3. For example, the MOS transistor of the second patent application scope, wherein the body further includes a protective layer provided on the upper surface of the source region and the drain single crystal silicon layer, and the source conductive layer or the drain is guided by the protection. Layer above. 4. For example, the MOS transistor in the third item of the patent application scope, wherein a silicon oxide layer. |! 5. For example, the MOS transistor in the scope of patent application No. 1, which includes a layer of oxide. I 6. If the MOS transistor of item 1 of the scope of patent application, both the layer and the drain conductive layer are a doped I; poly-silicon layer ° 7. If the scope of patent application is the first In the M0S transistor, the layer and the drain dielectric layer are both silicon oxide layers. 8. The MOS transistor of item 1 of the patent application scope, which is composed of silicon nitride (Si 3N 4). The source is on a conductive area. The electrical layer within the M0S transistor region covers the protective layer, the insulating layer is the source conductive, the source dielectric, and the sidewall subsystem. 448 56 3 A _________-__ __A. One · — ^ —-—__ 16. The scope of patent application 9. If the patent ^, the closed-dielectric layer in one item is silicon dioxide (siliC〇 n dloxlde, Sl02) layer. 10 · As for the M0S transistor in the first item of the patent application scope, wherein the gate conductive layer is a doped polycrystalline silicon. U. A metal oxide semiconductor (MOS) transistor provided on a semiconductor wafer, the semiconductor wafer On the substrate, and an active MOS transistor includes a single-crystal silicon layer, a trench is arranged on the side to pass through, and the active two protective layer is respectively connected to the source conductive layer in the sum region. And a source dielectric layer and an electrical layer on the insulating layer in the drain region and two side walls of the drain conductive layer, which are adjacent to the sidewall of the trench, respectively; a gate dielectric layer on the four sides; and It includes a silicon substrate, an insulating layer is provided on the silicon region on a predetermined region of the insulating layer, and is on the insulating layer in the active region; in the active region, it is divided from the lower region of the bottom of the single crystal silicon layer A source region and a non-polar region; covering the single crystal dream layer on the single crystal silicon layer within the source region; a drain conductive layer covering the source region and the 'and covering the Over the protective layer; a drain dielectric layer 'respectively To cover the source over the guide; disposed on the conductive layer of the source electrode and the drain conductive layer coated on the single crystal silicon layer immediately above the trench of the exposed Page 18 448563 VI. Patent application scope A gate conductive layer fills the surface of the gate dielectric layer below the single crystal silicon layer; wherein when the voltage applied by the gate conductive layer is larger, the single crystal silicon layer is adjacent to A four-source conductive layer and the drain conductive layer are formed in the surface layers on the four sides. 12. If the MOS transistor of item 11 of the scope of patent application is a monolithic oxide layer. 1 3. If the MOS transistor of item 11 of the scope of patent application is a dream oxide layer. 1 4. If the MOS transistor layer and the drain conductive layer of the 11th patent scope are a doped polycrystalline silicon layer 1 5 _If the MOS transistor layer and the drain of the 11th patent scope of the application The dielectric layers are all silicon oxide layers. I 1 6. The MOS transistor according to item 11 of the scope of patent application is composed of nitride nitride. 1 7. If the MOS transistor in item 11 of the patent application scope, the electric layer is a silicon dioxide layer. And the channel is covered at the initial voltage, and the channel is turned on, in which the protective layer, the insulating layer, where the source is conductive, where the source is medium, where the sidewall is, and where the gate is Page 19 448 56 3 VI. Patent Application Range 1 8 _If the MOS transistor of item 11 of the patent application range, the gate conductive layer is a doped polycrystalline silicon layer. Page 20