455689 五'發明說明α) 1 ·發明領域 本發明是關於一種積體電路裝置之測試方法，特別是 指利用薄膜探針進行測試之方法。 2 *發明背景 封裝一顆無法工作的晶粒對於封裝材料及工時無疑是 一種浪費，特別是對於多晶片模組（M u 11 i - c h i ρ Module; MCM)而言，其影響尤其嚴重，原因是因為多晶 片模組包括了數個半導體晶粒，若其中的一顆晶粒壞掉， 這個多晶片模組便可能報廢，這意謂著其他好的晶粒被浪 費。 半導體業者已警覺到這個問題，其解決之道係提高良 晶片（Known Good Die; KGD)的可靠度，所謂的良晶片是 指經過許多電性測試的半導體晶粒，以確保其良率至一定 程度，而對於多晶片模組而言，良晶片的可靠度尤其重 要，藉由提高良晶片之可靠度，預先篩選出壞的晶粒以中 斷其後續之封裝製程，可以降低半導體封裝的成本。 在習知技術中，一種測試半導體晶粒的方法係以探針 (probe )直接與半導體晶粒表面的電路接點接觸。然而逞 種方式的成本較高，並且晶粒上的電路接點可能由於與探 針之間的接觸而造成損害。 再者，隨著積體電路裝置高度的集積化，單位面積的 電路接點之密度亦將大幅的增加，相鄰電路接點間的距離 則愈來愈小，若使用植針式（bed-o f-na i 1 )的測試設備，455689 Five 'invention description α) 1 · FIELD OF THE INVENTION The present invention relates to a method for testing integrated circuit devices, and particularly to a method using a thin-film probe for testing. 2 * Background of the Invention Packaging a die that does not work is undoubtedly a waste of packaging materials and man-hours, especially for multi-chip modules (M u 11 i-chi ρ Module; MCM), which has a particularly serious impact. The reason is that the multi-chip module includes several semiconductor chips. If one of the chips is broken, the multi-chip module may be scrapped, which means that other good chips are wasted. The semiconductor industry has been aware of this problem, and the solution is to improve the reliability of Known Good Die (KGD). The so-called good wafer refers to the semiconductor die that has passed many electrical tests to ensure its yield to a certain level. For multi-chip modules, the reliability of good chips is particularly important. By improving the reliability of good chips, screening out bad dies in advance to interrupt their subsequent packaging processes can reduce the cost of semiconductor packaging. In the conventional technology, a method for testing a semiconductor die uses probes to directly contact circuit contacts on the surface of the semiconductor die. However, this method is more costly and the circuit contacts on the die may be damaged due to contact with the probe. Furthermore, with the integration of the height of integrated circuit devices, the density of circuit contacts per unit area will also increase significantly, and the distance between adjacent circuit contacts will become smaller and smaller. If a bed-type (bed- o f-na i 1) test equipment,
第4頁 455689 五、發明說明（2) 不僅其製作較為複雜困難，其成本也較為昂貴。 因此’有必要提出一種較佳的改良方式，以改善習知 技術的缺失。 3 ·發明目的與概述 本發明之主要目的即在提出一種積體電路裝置之測試 方法，能夠在封裝晶粒之前，預先篩選不良之晶粒，以避 免封裝材料及工時被浪費，降低成本之損失， 本發明之另一目的亦在提出一種積體電路裝置之測試 方法，能夠提高良晶片之可靠度，增加多晶片模组的良 率。 本發明之再一目的更在提出一種積體電路裝置之測試 方法，能夠以較為低廉的測試治具，為未封裝之晶粒進行 測試。 根據本發明，一種積體電路裝置之測試方法係提供一 測試座承載待測之積體電路裝置，測試座内具有一薄膜， 其表面形成許多導電凸塊，導電凸塊經由線路連接至位於 薄膜邊緣的導電端子。將待測之積體電路裝置放入測試 座，使積體電路裝置之電路接點與導電凸塊電連接之後， 接著提供測試信號由導電端子經導電凸塊傳送至受測之積 體電路裝置，以測試積體電路裝置各項功能與電性參數是 否正常。 底下配合圖式及詳細說明，當更能瞭解本創作之特徵 及内容。Page 4 455689 V. Description of the invention (2) Not only its production is more complicated and difficult, but its cost is also relatively expensive. Therefore, it is necessary to propose a better way to improve the lack of conventional technology. 3 · Purpose and summary of the invention The main purpose of the present invention is to propose a test method for integrated circuit devices, which can pre-screen bad dies before packaging dies to avoid wasting packaging materials and man-hours and reduce costs. Loss. Another object of the present invention is to provide a test method for integrated circuit devices, which can improve the reliability of good chips and increase the yield of multi-chip modules. Yet another object of the present invention is to provide a test method for an integrated circuit device, which can test an unpackaged die with a relatively inexpensive test jig. According to the present invention, a test method for an integrated circuit device is to provide a test stand for supporting the integrated circuit device to be tested. The test stand has a thin film therein, and a plurality of conductive bumps are formed on the surface thereof, and the conductive bumps are connected to the thin film via a line. Conductive terminals on the edges. Put the integrated circuit device to be tested into the test base, and then electrically connect the circuit contacts of the integrated circuit device with the conductive bumps, and then provide a test signal to be transmitted from the conductive terminals to the integrated circuit device under test through the conductive bumps. In order to test whether the functions and electrical parameters of the integrated circuit device are normal. With drawings and detailed descriptions below, you can better understand the characteristics and content of this creation.
第5頁 455689 五、發明說明（3) 外 座 試 測 之 。粒 圖晶 意體 示導 觀半 外載 之承 粒來 晶用 體明 導發 明 半本 說明一示 單說為顯 簡式圖圖 式圖一二 圖1第第 · ο 4 4 觀 第三圖為第二圖所示裝置之立體分解圖。 第四圖顯示第三圖所示裝置之薄膜之外觀示意圖。 第五圖為本發明之動作示意圖。 第六圖顯示晶粒與薄膜電連接之示意圖。 第七圖為測試座對應一測試基座之示意圖。 4 _ 2圖號說明 1 0 晶 粒 1 2 電 路 接點 2 0 基 座 2 0 2 開 口 1 0 4 凹 U 2 0 6 螺 孔 2 0 8 間 隙 2 1 薄 膜 2 1 2 凸 塊 2 1 4 線 路 2 1 6 導 電 端 子 2 2 壓 合 座 2 2 2 槽 體 2 2 4 凹 Π 9 2 6 定 位 孔 2 2 8 穿 孔 2 4 底 板 2 4 2 橡 膠 墊 2 6 結 合 銷 2 6 2 螺 柱 2 8 伸 縮 彈 簧 3 0 基 座 3 2 導 電 端 子 455689 五、發明說明（4) 5 ·詳細說明 第一圖首先提供一半導體晶粒之外觀示意圖，在半導 體晶粒1 Q表面具有許多的電路接點1 2提供信號輸入輸 出，意即測試半導體晶粒1 〇必須藉由電路接點1 2送入 測試訊號。 在本發明中提供了一測試座承載半導體晶粒1 〇 ，此 測試座之外觀圖及立體分解圖係如第二圖及第三圖所示， 其包括一壓合座2 2與一底座2 0 ，二者藉由二結合銷2 6而結合，結合銷2 6向下延設一螺柱2 6 2 ，其穿過底 座2 0上之穿孔2 2 8而鎖固於底座2 0二端之螺孔2 0 6 ，結合銷2 6套設有伸縮彈簧2 8 ，伸縮彈簧2 8 —端 抵住壓合座2 2 ，使壓合座2 2與底座2 0結合。 底座2 0具有一開口 2 0 2 ，開口 2 0 2之一侧壁具 有一凹口 204 。一薄膜2 1位於底板2 4表面與開口 2 0 2之底端蓋合而形成一凹槽，薄膜2 1係用來作為測試 訊號之傳輸界面，其結構請併參第四圖所示，在薄膜2 1 表面形成有數個導電凸塊2 1 2 ，其藉由線路2 1 4連接 至薄膜2 1周邊之導電端子2 1 6 。其中，底板2 4係用 以提供薄膜2 1 —支撐作用，其對應凸塊2 1 2設置橡膠 墊2 4 2 ，以便使凸塊2 1 2與待測之晶粒1 0的電路接 點1 2獲得良好的接觸。並且薄膜2 1上的導電端子2 1 6的一部份露出底座20 ^ 壓合座2 2於中央部位向下形成一面開口之槽體2 2Page 5 455689 V. Description of the invention (3) Tested by an outside seat. The grain picture crystal body shows the guided semi-outloaded bearing grains. The crystal is guided by the body. The description is shown as a simple diagram. Figure 12 shows the first picture. Figure 4 shows the third picture. This is an exploded perspective view of the device shown in the second figure. The fourth figure shows the appearance of the film of the device shown in the third figure. The fifth figure is a schematic diagram of the operation of the present invention. The sixth figure shows a schematic diagram of the electrical connection between the die and the thin film. The seventh figure is a schematic diagram of a test base corresponding to a test base. 4 _ 2 Description of drawing number 1 0 die 1 2 circuit contact 2 0 base 2 0 2 opening 1 0 4 concave U 2 0 6 screw hole 2 0 8 gap 2 1 film 2 1 2 bump 2 1 4 circuit 2 1 6 Conductive terminal 2 2 Crimp seat 2 2 2 Slot body 2 2 4 Concave Π 9 2 6 Positioning hole 2 2 8 Perforation 2 4 Base plate 2 4 2 Rubber pad 2 6 Coupling pin 2 6 2 Stud 2 8 Telescopic spring 3 0 Base 3 2 Conductive terminal 455689 5. Description of the invention (4) 5 · Detailed description The first picture first provides a schematic diagram of the appearance of a semiconductor die. There are many circuit contacts on the surface of the semiconductor die 1 Q. 2 Provides signal input The output means that the test semiconductor die 10 must be fed into the test signal through the circuit contact 12. In the present invention, there is provided a test seat for carrying the semiconductor die 10. The external view and the three-dimensional exploded view of the test seat are shown in the second and third figures, which include a crimping seat 2 2 and a base 2 0, the two are combined by two coupling pins 26, and the coupling pin 2 6 is extended downward with a stud 2 6 2, which passes through the perforation 2 2 8 on the base 20 and is fixed to the two ends of the base 2 0 The screw hole 2 0 6 and the coupling pin 2 6 are provided with a telescoping spring 2 8. The telescoping spring 2 8 —ends against the pressing seat 2 2, so that the pressing seat 2 2 is combined with the base 20. The base 20 has an opening 202, and one side wall of the opening 202 has a notch 204. A film 21 is located on the surface of the bottom plate 2 4 and is covered with the bottom end of the opening 202 to form a groove. The film 21 is used as a transmission interface for the test signal. Please refer to the fourth figure for its structure. A plurality of conductive bumps 2 1 2 are formed on the surface of the film 2 1, and are connected to the conductive terminals 2 1 6 around the film 2 1 through a line 2 1 4. Among them, the bottom plate 2 4 is used to provide a thin film 2 1-supporting function, which is provided with a rubber pad 2 4 2 corresponding to the bump 2 1 2 so that the bump 2 1 2 and the circuit contact 1 of the die 10 to be tested 1 2 Get good contact. And a part of the conductive terminal 2 1 6 on the film 21 is exposed to the base 20 ^ The crimping seat 2 2 forms a groove body 2 with an open surface at the center.
第7頁 455689 五、發明說明（5) 2對應開口 202 ，槽體222底面具有一凹口 224對 應凹口 2 0 4 ，其二側各穿設一定位孔2 2 6 。 在為晶粒1 0進行測試作業時，係將第一圖所示裝置 之壓合座2 2向上移動至如第五圖所示，使槽體2 2 2與 凹口 204之間具有一適當的間隙208 ，藉由一真空吸 嘴A吸附晶粒1 〇背面，由間隙2 0 8沿著凹口 2 2 4將 晶粒1 0放入底座2 0。然後使壓合座2 2降下，使槽體 2 2 2底面對晶粒1 0施壓，使晶粒1 0之電路接點1 2 與薄膜2 1上的凸塊2 1 2緊密的接觸，成為如第六圖所 示之狀態。為了確定電路接點1 2與凸塊2 1 2是否準確 的接觸，可以藉由定位孔2 2 6暸解晶粒1 0的位置，若 有偏差，即可藉由凹口 224作適當的調整。 其中，若是待測晶粒面積小於吸嘴的面積，則可以先以一 具有較大面積且形成有穿孔的薄板覆蓋晶粒表面，然後利 用真空吸嘴透過薄板上的穿孔將晶粒吸附起來，再放入底 座2 0 ，以槽體2 2 2底面對此薄板與晶粒施壓，使晶粒 之電路接點與薄膜2 1上的凸塊2 1 2接觸。 晶粒1 0與凸塊2 1 2電連接後 '便開始輸入測試信 號進行測試，露出底座2 0底端的導電端子2 1 6被作為 外部測試信號進入測試座的輸出入接點，其中的一種方式 係如弟七圖所不’將測試座放入測試基座（s 〇 c k e t) 3 0 進行測試，由測試基座連接之測試電路提供測試信號，其 中，基座3 0可以是目前業界用在預燒板（burn - in board)或測試機台所使用的測試基座，其内部具有數導電Page 7 455689 V. Description of the invention (5) 2 corresponds to the opening 202, the bottom face of the groove body 222 has a notch 224 corresponding to the notch 2 0 4 and a positioning hole 2 2 6 is formed on each of the two sides. When testing the die 10, the crimping seat 22 of the device shown in the first figure is moved upwards as shown in the fifth figure, so that there is an appropriate space between the groove 2 2 2 and the recess 204. In the gap 208, the back surface of the crystal grains 10 is adsorbed by a vacuum nozzle A, and the crystal grains 10 are placed in the base 20 along the notches 2 2 4 through the gaps 208. Then, the pressing seat 2 2 is lowered, and the bottom of the groove body 2 2 2 is pressed against the die 10, so that the circuit contact 1 2 of the die 10 is in close contact with the bump 2 1 2 on the film 2 1 , As shown in Figure 6. In order to determine whether the circuit contact 12 and the bump 2 12 are in accurate contact, the position of the crystal grain 10 can be understood through the positioning hole 2 2 6. If there is a deviation, the recess 224 can be appropriately adjusted. Wherein, if the area of the grain to be measured is smaller than the area of the suction nozzle, the surface of the grain may be covered with a thin plate having a large area and a perforation formed, and then the vacuum suction nozzle is used to adsorb the grain through the perforation of the thin plate. Then, the base 20 is put, and the bottom surface of the groove body 2 2 2 is used to press the thin plate and the crystal grains, so that the circuit contacts of the crystal grains contact the bumps 2 1 2 on the film 21. After the die 10 and the bump 2 1 2 are electrically connected, a test signal is input for testing, and the conductive terminal 2 1 6 at the bottom of the base 2 is exposed to the input and output contacts of the test base as an external test signal. The method is as described in the seventh figure. Put the test base into the test base (socket) 30 for testing. The test circuit connected to the test base provides the test signal. Among them, the base 30 can be used by the current industry. The test base used in the burn-in board or test machine has a number of conductive parts inside.
第8頁 455689 五、發明說明（6) 端子3 2與薄膜2 1之導電端子2 1 6電連接，換言之， 第一圖所示之裝置可以適用在現行的測試機台進行測試， 並不需另外製作特別規格的測試設備。並且對於不同種類 的晶粒，或者是多晶粒模組（M u 11 i - Ch i ρ Μ〇 d u 1 e ; M CM) 而言，只需要置換相對應之薄膜1 1即可適用，應用範圍 相當的廣泛，而增加的額外成本則較習知技術低。 再者，由於薄膜2 1上的凸塊面積非常小，其配置能 夠配合半導體晶粒之電路接點密集化的趨勢，且薄膜2 1 内層更可製作電路以增加其他功能。 雖然前述實施例系以未經封裝的半導體晶粒作為說 明，然而對於某些完成封裝的半導體裝置而言，例如球柵 陣列構裝（Ball Grid Array; BGA)，本發明亦可適用，其 步驟與測試晶粒1 0的步驟大致相同，只是換成使球柵陣 列構裝之銲球與薄膜2 1之凸塊2 1 2電連接而己。 以上所述係藉由實施例說明本創作之特點，其目的在 使熟習該技術者能暸解本創作之内容並據以實施，而非限 定本創作之專利範圍，故，凡其他未脫離本創作所揭示之 精神所完成之等效修飾或修改，仍應包含在以下所述之申 請專利範圍令ϋPage 8 455689 V. Description of the invention (6) The terminal 3 2 is electrically connected to the conductive terminal 2 1 6 of the film 21, in other words, the device shown in the first figure can be applied to the current test machine for testing, and it is not required In addition, special test equipment is made. And for different types of grains, or multi-die modules (M u 11 i-Ch i ρ Modu 1 e; M CM), only the corresponding thin film 1 1 needs to be replaced and applicable. The scope is quite extensive, and the added cost is lower than conventional technologies. Furthermore, since the area of the bumps on the thin film 21 is very small, its configuration can meet the trend of dense circuit contacts of the semiconductor die, and the inner layer of the thin film 21 can be used to make circuits to add other functions. Although the foregoing embodiments have been described with unpackaged semiconductor dies, for some semiconductor devices that have been packaged, such as Ball Grid Array (BGA), the present invention is also applicable, and the steps The steps are the same as those for testing the die 10, except that the solder balls configured by the ball grid array are electrically connected to the bumps 2 1 2 of the thin film 21. The above is the description of the characteristics of this creation through the examples. The purpose is to enable those skilled in the art to understand the content of this creation and implement it, not to limit the scope of patents for this creation. Therefore, all others do not depart from this creation. Equivalent modifications or amendments made by the disclosed spirit should still be included in the patent application order described below: