TW457570B - Self-aligned process for stack gate radio frequency transistor - Google Patents

Abstract

In the present invention, a first dielectric layer is formed over a device, wherein the first dielectric layer has a protrusion disposed on the device, and then a hard mask layer is formed on the first dielectric layer. The protrusion is removed by chemical mechanical polishing and using the hard mask layer as a stopper and a self-aligned window is formed to expose the first dielectric layer. Thereafter, a second dielectric layer is formed on the hard mask layer and the first and second dielectric layers are etched to form a contact window therein for connecting the device. A photoresist layer is formed on the second dielectric layer to expose the part of the second dielectric layer disposed on the device. The second dielectric layer is etched to form a stack gate region by using the hard mask layer as an etching barrier, and the first dielectric layer is etched to form a self-aligned contact window therein. Next, the photoresist layer is removed and the conductive material is filled into the contact window, the stack gate region and the self-aligned contact window, by which a stack gate having a larger contact area for reducing resistance is formed.

Description

457570 V. Description of the invention (1) Field of the invention: ^ month and stack semiconductor interfering emitter (stack gate RF MOSPFT, ancient aa ^ ol a liqian 1: self-alignment of Japan-Japan electric crystal ^ SFET), In particular, a kind of stacked gate has invented the size of back-stacked electrical components, and the size of the semiconductor can be reduced after the challenge of size. The components are connected by a dielectric. Scene: The circuit (IC) technology density is already high enough to increase the semiconductivity and reduce it. For example, the accumulation of electrical components is used to make memory cells behave. The special layer of isolation, or the area of the contact window that has become the volume of the electrical state of the electric capacity, the extent of the decrease in the random capacity is that when the circuit resistance has a significant trend, the circuit circuit has less memory and leads to increase. , Shrinking, high-level features will increase. . Through shrinking the density of the manufacturing process (DRAM) is simple and reliable, usually each of several technologies, the integrated circuit structure is smaller than in the past, but small electronics. With the continuous output of dimensional memory cells that have been cited for a long period of time, the weight has been reduced to increase the number of components and electrons. How new are the electronic ruler components. Dangji will improve the connection. The typical metal-oxygen half-field transistor has mostly replaced the bipolar transistor in the same frequency application. For example, a personal mobile phone or personal communication service amplifier at GHz. wireless communication amplifier; PCS). The main reason is that MOSFETs have better linear characteristics than bipolar components.

4 5 7 5 7 0 V. Description of the invention (2) For bipolar 'it has less nonlinear transfer characteristics (non-Hnear transfer character). The use of high-efficiency power amplifiers is usually included in the application of personal mobile phones or PCS. United States Patent United States Pat. No. 6, 0, 6, 0, 8 8 discloses a power transistor, the invention name is "RF power MOSFET device with extended linear región of transconductance characteristic at low drain current". Another U.S. patent discloses a high-power transistor. See U.S. Patent No. 6,046,641, and the invention name is Paral lei HV MOSFET high power stable amplifier ". Figure 1 shows a metal-oxide-semiconductor (MOSFET) used in the prior art, which generally includes a gate oxide layer 21 formed on a substrate 2 and a gate electrode 6 located on the gate oxide layer 21. The partition wall 8 is located around the gate electrode 6 for insulation. The drain electrode 12 and the source electrode 10 are located on the side of the substrate 2 adjacent to the gate electrode 6. In order to reduce the resistance value, the metallization layer 14 can be silicided on the gate 6, the drain and the source 12, 10 respectively. For a plan view, see Figure 2. As the person skilled in the art knows: f T / 2 ((Rs + Rg) / Root + 2pei * fT RgCgd) 0 · 5 where fMA is the unit power gain frequency, and f is the unit current Gain frequency (unit current gain freque π cy) 'R is the source resistance' R is the gate resistance 'C pole and the inter-electrode capacitance.

45757ο V. Description of the invention (3) > Buckle & & Based on the trend of component shrinking, the narrower chirped electrode causes a slightly higher doped pole (LDD) with a higher surface resistance concentration and higher gate Capacitance between drains. In addition, smaller contact windows will result in higher contact resistance. OBJECTS AND SUMMARY OF THE INVENTION The object of the present invention is a method for fabricating a stack gate RF metal oxide semiconductor (stack gate RF MOSFET) for reducing contact resistance. Another object of the present invention is a stack gate RF MOS transistor to reduce higher gate resistance. Another object of the present invention is a self-aligning process for a stacked gate RF metal oxide semiconductor transistor. The present invention discloses a self-aligned process for stacked gates, which provides a wafer including a general transistor region and an RF transistor region, respectively, with a general transistor and an RF transistor formed therein. The present invention includes forming a first dielectric The electrical layer is on the general transistor region and the RF transistor region. The first dielectric layer includes a protruding structure on the general transistor and the RF transistor. After that, a hard mask layer is formed on the first dielectric layer. The protruding structure is polished by chemical mechanical polishing and stopped on the hard mask to form a self-aligning window to expose the first dielectric layer. Next, a second dielectric layer is formed on the hard mask layer, and then the first and second dielectric layers are etched to form a contact window therein to facilitate connection with the general transistor and the RF transistor. Forming a photoresist on the second dielectric layer to expose the RF transistor

457570 V. Description of the invention (4) The second dielectric layer above the gate electrode, and then the second dielectric layer is etched to facilitate the area of the stack electrode of the RF transistor, and the hard mask layer, The barrier 'etches the first dielectric layer to form a self-aligned contact window in Z. After that, the photoresist is removed and the conductive material is backfilled in the contact window, the area where the stack gate is formed, and the self-aligned contact window. The formed stack 2 includes a larger contact surface to reduce the resistance. 1 pole Detailed description of the invention: What is disclosed in the present invention is a stacked closed-pole radio frequency gold stack gate RF «〇SFET) ^ ^ ^ Out 'The disclosed in the present invention is a stacked gate emitter, which is a quasi-manufacturing process. In the subsequent process, when making the self-aligned contact window of the pile = milk + transistor and the hard cover smart pole, the self-aligned contact window of the body gate can be continued to be used. In addition, in the present invention where stacked gates aligned with RF transistors are used to reduce transistors, the following can be used by widening. Resistance. The method of the present invention will be referred to FIG. 3. As a semiconductor material, a single plate or wafer 20 with a crystal orientation of < 1 0 0 > is used. For example, it can be rounded to 20. As one skilled in the art knows, ,also. The crystal according to the embodiment of the present invention is the substrate 20. It is divided into wafers 2 and 4 which can be made of gallium arsenide or germanium 4 0 and radio frequency device area 2 0. “'" Zhi rarely includes general device areas and barrier areas such as shallow trench isolation

45757ο 5. Description of the invention (5) Shallow trench isolation (STI) is first fabricated in wafer 20 using known techniques. Generally, shallow trenches are formed in wafers by lithography and surface engraving, and then backfilled into the shallow trenches with an oxide layer deposited by chemical vapor deposition. In addition, other isolation technologies can also be used to make the isolation area. For example, a field area can be formed on the wafer 20 using LOCOS or other related field oxide insulation area technology to provide insulation between components. Generally, It is possible to etch the silicon nitride and silicon oxide composite layer by lithography and etching technology, and then form a field oxide region on the wafer 20 by an oxidation process. After completion, the above silicon nitride layer is removed by hot phosphoric acid, and Hydrofluoric acid removes the silicon oxide layer β. Next, the transistor 22 is produced, which includes at least a layer of stone dioxide formed on the wafer 20 as a gate oxide layer. In order to form by thermal oxidation, the process temperature is about 700 to 110 (the thickness between TC is about 50 to 200 angstroms). Of course, common techniques such as chemical vapor deposition can also be formed using TEOS as a reactant. Oxide layer. The gate structure is patterned on the wafer using traditional techniques. The gate structure can include a polycrystalline layer deposited on a silicon dioxide layer. Chemical milk Phase deposition (CVD) is used to form a 'metal-lithium oxide compound, such as a tungsten oxide layer, formed on the above-mentioned multi-crystalline fragment layer. Then, a nitride oxide layer is deposited on the gate structure' and then micro-scaled. The gate structure is formed with the etching technique. Then, a doped region or a slightly doped doped electrode (LDD) is formed by ion implantation. The above process is made by a known technique and is not the focus of the present invention. Detailed. It is worth noting that

Page 9 457570 V. Description of the invention (6) The materials used include silicon nitride, and then ion implantation is used to make the electrode and source. As shown in Figure 3, an insulating layer such as an oxide layer (ο X ide) 2 4 with a thickness of about 2500-300 0 angstroms covers the gate structure and the surface of the wafer 20. In a preferred embodiment, the dielectric layer The electrical layer 24 is an oxide or silicon dioxide formed of TEOS. It can be seen from the figure that the structure corresponding to the gate electrode includes a protruding structure 2 8, which is mainly the result of chemical vapor deposition deposited along the bottom pattern. Next, a hard mask 26 is deposited and deposited along the surface of the above-mentioned oxide layer (ox i de) 2 4 to a thickness of about 2 50-3 50 angstroms. The material of the hard mask layer 26 can be nitride nitride. In general, the nitride nitride layer 26 can use Low Pressure Chemical Vapor Deposition (LPCVD), plasma enhanced chemical vapor deposition ( Plasma Enhance Chemical Vapor Deposition (PECVD) or High Density Plasma Chemical Vapor Deposition (HDPCVD). The reaction gas can be SiH4, NQ3, N2, N20 or SiH2Cl2, NQ3, N2, N20. After that, the above-mentioned protruding structure 28 is polished to a level of 'forming self-aligned openings 24a on the surface of the dielectric layer 24' by using a chemical mechanical polishing method (see FIG. 4). It can be seen from the figure that the self-aligned 〇pening 24 a is aligned with the gate β of the transistor as shown in FIG. 5 'deposit an insulating material such as an oxide layer 3 〇 on the hard mask layer 26 The thickness is about 2 0 0-2 50 0 Angstroms. So, insulation layers 30, 24

Page 10 457570 V. Description of the invention (7) The total thickness is about 45 0 0-55 0 0 to protect the components. The above-mentioned insulating layer 3 0, 24 is etched using the micro-image # etch process to form a contact window 3 丨 corresponding to the drain and source of the component, as shown in FIG. The contact window is exposed above the RF element, and a large opening is formed until the hard cover 26 is formed. At this time, 'the above-mentioned opening has exposed the alignment window 24a. If you continue to etch, you can use this hard mask 26 as a button etch. The barrier layer will form a self-aligned contact window that exposes the RF transistor gate by itself. The larger opening will be used as the area where the stacked gates are formed, as shown in Figure 7. Remove the photoresist when finished. Next, a conductive plug 3 2 is made in the contact window 31 ′ using a metal bolt, such as a tungsten plug, and is back-filled in the larger opening to form a stacked gate 34. Before implementation, a barrier layer consisting of TiN can be deposited, and then a tungsten material can be deposited thereon. Then, etch-back or grinding is performed to form the metal plug 32 and the stacked gate as shown in the figure. If necessary, contact pads 3 2 a can be made in advance to form a path for connection with the component. The above-mentioned stacked gates 34 can be used as the gate signal transmission. It has a larger contact area or provides a wider gate, which can not only reduce the resistance value, but also integrate general components and RF transistor processes. Finally, the conductive pattern is made on the known technology, as shown in Figure 8 = Figure 9 is a top view of the present invention. In the present invention, first, the protrusions caused by chemical vapor deposition are used, and with the use of a hard mask, a self-aligning contact window can be formed by a chemical mechanical polishing process. In subsequent processes, when making stacked gates, you can continue

Page U 457570 V. Description of the invention (8) Use the self-aligned contact window and the hard cover as described above to make a self-aligned contact window aligned with the RF transistor gate. In addition, in the invention, a widened stacked gate can be used to reduce the resistance of the RF transistor. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. Field-specific.

Page 12 457570 The illustration of the drawing is simple and decent. Figure Guide. . Columns of semicircular faces. The screenshot of the crystal below the picture is cut off by the round surface of the screen, and the auxiliary guide is used to cut the round. The Chinese semi-circular crystal is hard and the latter is the guide. . The guide half of the mill is used to describe the half of the map layer, and the half of the layer is viewed from the side of the electrical pole. Learn the second touch-up electrogram in the body, and then take the guided tour of the body. The crystals will be formed into a regular electric shape. The shape of the shape of electricity: half and a half clearly explain the oxygen and oxygen. Fafafafafafafa good analysis of gold and gold. Textbooks Textbooks: All the pictures are shown for the sake of the sake of the sake of the details of the detailed information on the surface of the show, show the show, the description is detailed for the interception of the place of the show more than one two three round four. Fifty-six, seven, eight, nine, nine, nine, nine, nine, nine, nine, nine, nine, nine, nine, eight, eight, two, eight, insulating, 3, conductive, wafer 20, transistor 22, dielectric layer 24, hardmask 2 6 Pin 32 Contact window 3 1 Stacked gate 34

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Claims (1)

457570 6. Scope of patent application: quasi-alignment of self-polarity gate stack xuan = ° quasi-alignment of self-polarity gate stack ΛΕ · * one contains one — | encapsulation protrusion 1 contains cladding dielectric 1 On the upper element, the electric element on the upper layer-the first position in the formation structure D window alignment to the self-formed upper layer of the curtain cover is electrically hardened-the first stop on the stop layer and the curtain structure. The hardening process should be performed to remove the layer on the first exposure layer, the cover layer, the dielectric layer, the dielectric layer, the second layer, and the second layer of the dielectric layer; And then ° 1 ί a piece of element dielectric engraved and etched on the element should be exposed in place to use the layer of dielectric two; the first layer of electricity is formed in the square shape of the dielectric two; to use the field The stack of layers of dielectrics and gates in each layer is etched as an etch, and the barriers are formed in the etch. In the etch, the layers are made on the electrical layer, the window screen, the second screen, and the first type. Eclipse formation This, and the window to abut., Material photoelectric barrier in addition to the conductive filler to abut the back relatively large packages containing gate electrode stack to the shape of its. The electrical resistance of the resistance window is lowered to lower the accuracy to match the gates of the process. $ Stacked layers of daggers 1 ^ Contains the enveloping layer Fan Dilishen, please specifically refer to the second application as described above 2 The middle of the process system is to match the items of the self-polar gate stack Page 15 457570 6. Scope of patent application The above-mentioned second dielectric layer includes an oxide layer. 4. The self-aligned process of stacked gates as described in the patent application item 1, wherein the hard mask described above includes a nitride layer. 5. For the self-aligned process of stacked gates according to item 4 of the patent application, where the above silicon nitride layer is a low pressure chemical vapor deposition method (L 0 w Pressure Chemical Vapor Deposition; LPCVD), plasma enhanced Chemical vapor deposition (Plasma Enhance Chemical Vapor Deposition; PECVD) or High Density Plasma Chemical Vapor Deposition (HDPCVD). 6. If the self-aligned process of the stacked gate is applied for item 5 of the patent scope, the above reaction gas is SiH4 'NH3, N2, N20. 7 · The self-aligned process of stacked gates according to item 5 of the patent application, wherein the above reaction gas is SiH2Cl 2, NH3, N2 > N20. 8 The self-aligning process of the stacked gates as described in the first patent application scope, wherein the above-mentioned method for forming the conductive material includes a conductive plug process. 9 · If the self-aligning process of the stacked gates according to item 1 of the patent application scope, wherein the above-mentioned conductive pick-up process includes a tungsten plug process. Page 〖6 457570-...-. — -—— ~-VI. Application for patent scope 10. For example, the self-alignment process of the stacked gate of the patent application scope item 1, where the first dielectric layer mentioned above The thickness is between 2500-300 Angstroms. 1 1. The self-aligned process of the stacked gate according to item 1 of the patent application, wherein the thickness of the second dielectric layer is about 2000-250 Angstroms. 12. The self-aligning process of the stacked gate according to item 1 of the patent application, wherein the hard mask layer is removed by chemical mechanical polishing technology. 1 3. —A self-aligned process of a stacked gate, which includes a wafer including a general transistor region and an RF transistor region. The self-aligned process of the stacked gate includes: forming a first dielectric layer on the general electrode; Above the crystal region and the RF transistor region, the first dielectric layer includes a protruding structure on top of the general transistor and the RF transistor; forming a hard mask layer on the first dielectric layer; Grinding the protruding structure and stopping on the hard mask, forming a self-aligned window to expose the first dielectric layer; forming a second dielectric layer on the hard mask layer; etching the first and the second A dielectric layer is formed into a contact window to facilitate connection with the general transistor and the RF transistor; and a photoresist is formed on the second dielectric layer to expose a first electrode located above the gate of the RF transistor. Two dielectric layers Page 17 45757〇 —__________ VI. Patent application scope: The second dielectric layer is engraved with silver to facilitate the formation of the area as the stacked gate of the RF transistor; the hard mask layer is used as the #etch barrier, and the rest Engraving the first dielectric layer to form a self-aligned contact window therein; removing the photoresist; and backfilling a conductive material in the contact window, the area where the stacked gates are formed, and the self-aligned contact window, wherein The formed stacked gate includes a larger contact surface to reduce resistance. 1 4. According to the self-aligned process of the stacked gate according to item 13 of the patent application scope, the above-mentioned first dielectric layer in L includes an oxide layer. 15 · The self-aligned process of the stacked gate according to item 13 of the patent application, wherein the above-mentioned second dielectric layer includes an oxide layer. 16. The self-aligned process of the stacked gate according to item 13 of the patent application, wherein the hard mask described above includes a nitride layer. 17 · If the self-aligned process of the stacked gate is applied for item 16 of the scope of the patent application, the above silicon nitride layer is formed by using Low Pressure Chemical Vapor Deposition (LPCVD), electrical Polymer enhanced chemical vapor deposition (Plasma Enhance Chemical Vapor Deposition; PECVD) or high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition; HDPCVD) Page 18 d 57 51 (} 6. The scope of patent application is formed. 1 8. The self-aligned process of stacked gates as described in item 17 of the scope of patent application, where the above reaction gas is Si Η 4, ΝΗ3, Ν2 Ν20. 1 9. If the self-aligning process of the stacked gate is applied for item 17 in the scope of patent application, the above reaction gas is Si H 2C1 2, NH3, N2, N20. 2 0. If the scope of patent application is 1 3 The self-aligned manufacturing process of the stacked gate of the item, wherein the above-mentioned method for forming the conductive material includes a conductive plug process. 2 1. The self-aligned process of the stacked gate according to item 13 of the patent application scope, wherein the above-mentioned conductive plug The manufacturing process includes a tungsten plug manufacturing process. 2 2. The self-aligned manufacturing process of the stacked gate according to item 13 of the patent application scope, wherein the thickness of the first dielectric layer is about 2500-300 Angstroms. The self-aligned process of stacked gates in the scope of application for patent No. 13 wherein the thickness of the second dielectric layer is about 2000-250 Angstroms. Page 19