473940 A7 五、發明說明（） 5-1發明領域： 本發明係關於一種半導體記憶元件，且特別是有關 於一種使用非揮發性（Nonvolatile)氧化矽-氮化矽-氧化石夕 (ΟΝΟ)閘極之動態隨機存取記憶體（Dram)。 5-2發明背景： 目前在電腦中用於資料儲存的裝置主要分為兩種， 包括非揮發性（Nonvolatile)記憶裝置與揮發性（v〇latiu) 快 佳 記憶裝置。一般非揮發性記憶裝置包括有已知的唯讀記 憶體（Read Only Memory，R〇M)、可抹寫唯讀記憶體 (EPROM)、電子式可抹寫唯讀記憶體（EEpR〇M)、以及 閃記憶體（FUsh EEPR0M)。其中，以快閃記憶體為較 的儲存裝置。這些非揮發性記憶裝置在電源關閉之後 仍然能夠維持儲存的資料，所以其為非揮發性。 …揮發性記憶裝置包括動態隨機存取記憶體⑽與 要 快 置 靜態隨機存取記憶體(SRAM)。過去隨機存取記憶” 用在暫時性的資料館存，比如是f料的操控時 速且容易地將資料寫入及讀出。然而，這些揮 經 濟 部 智 慧 財 產 局 的缺點是其必須維持電源的供給，藉以更新： 的 在記憶體中的資料。一旦電源中冑，儲存在;己惟：： 資料將會消失。 隐體中 消 費 合 作 社 印 製 本紙張尺度適用中國國家標準（CNS)A4規格（ x 297公£ 473940 經濟部智慧財產局員工消費合作社印製 本發 在一半導 極、第一 線，且第 接至控制 資料之儲 閃記憶胞 二閘極連 且第二源 發性可抹 換電路， 資料可以 A7 五、發明說明（） 因此，若能夠將揮發性與非揮發性記愫 將可提供一種非揮發性半導體記憶裝置:置結合， 量，簡單的記憶胞結構，快速存取資 、具高記憶容 等優點。 M及非揮發性 5-3發明目的及概述： 本發明針對上述需求，提供一種非揮 、 憶兀件，使用製程相容性高的的非揮發性可牛導體記 作為快閃記憶元件，其製作成本低廉，且操4寫電晶體 具動態隨機存取記憶體與快閃記憶體之優點、。簡單，兼 明提供一種非揮發性半導體記憶元 體基底上’包括：一控制電晶體， 源極與第一汲極，第一閘極連接至 一源極連接至一第一位元線；一餘 電晶體之第一汲極，控制電晶體控 存；以及一非揮發性可抹寫電晶體 ’其具有第二閘極、第二源極與第 接至一第二字元線，第二汲極連接至 極連接至一第二位元線；其中健存 寫電晶體透過第一與第二位元線， 使儲存電容與非揮發性可抹寫電晶 相互轉換。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 件，係架 具有第一 細丨 第一字 存電容， 制儲存電 ’如 〇Ν〇 二汲極， 第—及極 電容與非 連接至— 體内儲； * ^ 裝·] —«.—訂--------- Γ 请先閱讀背面之注意事項再填寫本頁) 473940 A7 _B7_ 五、發明說明（） 本發明亦提供一種非揮發性記憶體電路，係架構在 一半導體基底上，包括：複數個動態隨機存取記憶胞、 複數個非揮發性可抹寫電晶體，如ΟΝΟ快閃記憶胞，以 及一資料緩衝區。每一個動態隨機存取記憶胞包括一控 制電晶體，具有第一閘極、第一源極與第一汲極，第一 閘極連接至一第一字元線，且第一源極連接至一第一位 元線；以及一儲存電容，連接至控制電晶體之第一汲極， 控制電晶體控制儲存電容資料之儲存。每一個非揮發性 可抹寫電晶體具有第二閘極、第二源極與第二汲極，第 二閘極連接至一第二字元線，第二汲極連接至相鄰之控 制電晶體的第一汲極，且第二源極連接至一第二位元線。 資料緩衝區則連接每一條第一與第二位元線。其中，儲 存電容與非揮發性可抹寫電晶體透過資料緩衝區移轉， 使儲存電容與相鄰之非揮發性可抹寫電晶體内儲存的資 料可以相互轉換。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 作括，第，性，汲容 操包極 一極發極一電 之，汲至汲揮汲第存 件件一接一非二至儲 元元第連第 一 第接該 憶憶與極之及與連中 記記極源體以極極其 體體源 一晶·，源沒 ， 導導一第電存二二線 半半第且制儲第第元 生 生 、 ， 控 之、， 位 發發極線至料極線二 揮揮閘元接資閘元第 非非一 字連容二字一 種之第一$電第二至 一 明有第電存有第接 供發具一#儲具一連 提本，至儲制，至極 亦於體接4控體接源 明用晶連.，體晶連二 發適電極線晶電極第 本，制閘元電寫閘且 法控一位制抹二， 方一第一控可第極 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 473940 在電源開 在電源關 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（） 與非揮發性可抹寫電晶體透過該第一與-一 接至一轉換電路，該方法包括下列步驟： 70線連 ⑴存在之電二二啟之後，將非揮發性可抹寫電晶體所健 轉換電路ί!第二位元線傳送至轉換電路，再從 轉換電路經由第一位元線傳送至儲存 (2) 在資料轉移之後，關閉非揮發性 d Μ左Φ > 抹寫電晶體， 乂儲存電各進行資料存取；以及 (3) 在電源關閉之前，將儲存電 毯一你-祕你 雨什电奋所儲存之資料透過 皆—^ 一认 丹從轉換電路經由 第一位凡線傳送至非揮發性可抹寫電晶體。 5-4圖式簡單說明： 本發明的較佳實施例將於往後 1又心祝明文字中輔以下 列圖形做更詳細的闡述： 第1圖繪示本發明之非揮發性 u兀件之電路圖。 第2圖繪示本發明之非揮發性 庄。己It 70件中，ΟΝΟ快 閃δ己憶胞之結構剖面示意圖。 第3圖繪示本發明之非揮發性記憶元件 啟使用情況下，使用DRAM操作模式。 第4圖繪示本發明之非揮發性記憶元件 閉前，將DRAM記憶胞内儲存之眘祖 ^ ........ 貝抖轉移至對應的ΟΝΟ 快閃記憶胞。 第5圖繪示本發明之非揮發性 — 千义〖生Α憶疋件，在電源開 啟時，將ΟΝΟ快閃記憶胞内儲存欠 兩俘之資料轉移至對應的 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) | 裝 i,-------訂---------. 473940 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） DRAM記憶胞。 圖號對照說明： TC 控制電晶體 C 儲存電容 TS非揮發性可抹寫電晶體 WL-F非揮發性可抹寫體之字元& WL-D㈣隨機存取記憶體之字元線 BL-F 非揮發性可抹 寫電晶體之位元線 BL-D 動態隨機存取 記憶體之位元線 10 ΟΝΟ快閃記憶胞 12 半導體基底 14 源極 16 汲極 18 氧化矽層 20 氮化矽層 22 氧化矽層 24 閘極導電層 5-5發明詳細說明： 本發明揭露一種非揮發性半導體記憶元件之電路結 構及其操作方法，其製程整合性高，製作成本低廉，而 且兼具動態隨機存取記憶體（DRAM)與快閃記憶體（Fiash EEPROM)之優點’具有高記憶容量’快速資料存取 作簡單以及非揮發性等優點。 μ 請參照f 1圖’其繪示本發明之非揮發性記憶元件 I I I I I I ΙΓ I AW · I 1 I I 1 I I ^ ·11111111 l· I I (請先閱讀背面之注意事項再填寫本頁) 473940 A7 B7 五、發明說明（ 之電路圖。本發明之非揮發性記憶元件，装 ’、母一個單亓 包括一個DRAM記憶胞，以及一個非揮發性可袜。 體。DRAM記憶胞以1 τ-丨c結構較佳，每—倔寫電日日 1固dram印 (請先閱讀背面之注意事項再填寫本頁) 憶胞包括一個控制電晶體tc，以及一個儲存雷办 ° 制電晶體TC具有第一閘極、第一源極與第 工 一閘極連接到第一字元線，即DRAM的字元線WL 第一源極連接到第一位元線，即DRAM的位元線Bl d 第一汲極則連接到儲存電容c。透過字元線wl_d與位 元線BL_D操作控制電晶體TC，可將資料存入儲存/電六 C中’或是從儲存電容c中讀取資料。 谷 經濟部智慧財產局員工消費合作社印製 另外，在DRAM記憶胞旁鄰接有一非揮發性可抹寫 電晶體TS，例如是快閃記憶胞，以作為非揮發性儲存記 憶元件，其中，以ΟΝΟ快閃記憶胞最佳，其結構近似“ DRAM的控制電晶體TC，製程整合性極高，使其容易與 dram記憶胞整合在同一區塊中。以qNC)快閃記憶胞為 例，非揮發性可抹寫電晶體Ts具有第二閘極、第二源 極與第二汲極，第二閘極具有一層氧化矽_氮化矽-氧化 石夕（ΟΝΟ)層，以及在其上之閘極導電層，例如是複晶矽 (Polysilicon)層。資料即是儲存在中間的氮化矽層中， 使電晶體TS具有非揮發性。其中，第二閘極連接到第 二字元線，即快閃記憶胞之字元線WL-F，第二源極連 接到第二位元線，即快閃記憶胞之位元線bL_f，第二汲 極則連接到控制電晶體TC的第一汲極，由於控制電晶 體TC與可抹寫電晶體TS鄰接且第一汲極與第二源極相 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 473940 五、發明說明（ B7 經濟部智慧財產局員工消費合作社印製 接，因此第一汲極與第- 區，以提高元件的積及極可使用一個共用源極/沒極 第一與第二位元線BL_D與BL-FBuffer), 、、、口。儲存電容C與可抹寫 為貝科的連 可透過此資料緩衝區”、、θ日 戶斤儲存的資料即 _ {互轉換’將儲存雷交r h 2傳送到資料緩衝區，再從資料緩衝區傳 曰:體TS;或是反向將可抹寫電晶體 =電 送到資料緩衝區，再從資料緩衝區傳送到储存電容， ，者將近-步說明0N0快閃記憶胞之 月b 了解使用ΟΝΟ快閃却掊 使閱者 絡干一。…， 優點。請參照第2圖，盆 …、〇Ν〇快閃記憶胞之結構剖面示意圖。如八 =閃記憶胞10係架構在一半導體基底，二 源極14與没極16，以及架構源極14與 匕括 道上的閘極堆疊層。閘極堆疊層包括由氧化” η 氧广夕層22所組成的0Νο層，以及在όνο 曰曰上的閘極¥電層24。其中，閘極導電層u比如 由複晶矽所構成。利用熱電子注入技術，將 或”!，，藉由健存電荷存入…6側的氣化石夕層二即 圖中的圓圈處。並且’利用熱電洞注入技術，中和所儲 存的電荷，以抹除氮化矽層20所儲存的資料。 由於麵快閃記憶胞10(即非揮發性可抹寫電晶體 # 473940 A7 B7 五、發明說明（) TS)與傳統的DRAM的控制電晶體TC之結構極為相似， 僅多出氧化矽層1 8與氮化矽層2〇，因此在製作過程中， 其製程整合性極高，僅需先沉積氧化矽層1 8與氮化石夕層 20即可，其他的製程步驟均可與控制電晶體整合， 共同製作。所以其製作成本低廉，不需要增加其他^作 費用，且很容易可以製作出高積集度的記憶元件。至於 關於ΟΝΟ快閃記憶胞之詳細說明可參照u s. pat^t N〇 5，1 68,334 與 No. 5,768，192。 · 至於本發明之非揮發性記憶元件的操作方法，主要 包括三個部分。首先請參照第3圖，在電源開啟_段時 間後’進行資料的存取，此時可抹寫電晶體τ !態’僅以DRAM記憶胞(包括控制電晶體TC與= 谷C)作為记憶兀件，如圖中的圓圈473940 A7 V. Description of the invention (5) 5-1 Field of the invention: The present invention relates to a semiconductor memory element, and more particularly to a non-volatile (Nonvolatile) silicon oxide-silicon nitride-stone oxide (ON) gate. Extreme dynamic random access memory (Dram). 5-2 Background of the Invention: Currently, there are mainly two types of devices used for data storage in computers, including non-volatile (Nonvolatile) memory devices and volatiu fast memory devices. General non-volatile memory devices include known read-only memory (ROM), rewritable read-only memory (EPROM), and electronic rewritable read-only memory (EEpROM). , And flash memory (FUsh EEPR0M). Among them, flash memory is used as the storage device. These non-volatile memory devices are capable of maintaining stored data even after the power is turned off, so they are non-volatile. … Volatile memory devices include dynamic random access memory and fast static static random access memory (SRAM). "Random access memory in the past" is used for temporary storage of materials, such as f materials, which can be written and read quickly and easily. However, the disadvantage of the Intellectual Property Office of the Ministry of Economic Affairs is that it must maintain the power supply. In order to update: the data in the memory. Once the power is stored, store it in; Jiwei :: the data will disappear. The paper printed by the consumer cooperative in the hidden body applies the Chinese National Standard (CNS) A4 specification (x £ 297,473,940 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed on the half lead, the first line, and the flash memory cell connected to the control data, the second gate is connected, and the second source is the erasable circuit. The data can be A7 V. Invention description () Therefore, if the volatile and non-volatile memory can be provided, a non-volatile semiconductor memory device can be provided: combination, volume, simple memory cell structure, fast access to data, It has the advantages of high memory capacity, etc. M and non-volatile 5-3 Purpose and summary of the invention: The present invention aims to provide a non-volatile and memory device for the above-mentioned needs. Highly compatible non-volatile cattle conductors are used as flash memory components, which are inexpensive to manufacture, and have the advantages of dynamic random access memory and flash memory. They are simple, easy to understand Provided on a non-volatile semiconductor memory cell substrate includes: a control transistor, a source and a first drain, a first gate connected to a source connected to a first bit line, and a residual transistor A first drain electrode, which controls the transistor's memory; and a nonvolatile erasable transistor, which has a second gate electrode, a second source electrode, and a second word line, and the second drain electrode is connected to the electrode Connected to a second bit line; the storage write transistor passes the first and second bit lines to convert the storage capacitor and the non-volatile rewritable transistor to each other. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm pieces, the frame has the first thin 丨 the first word storage capacitor, the system stores electricity, such as 〇Ν〇 second drain, and the first and second capacitors and non-connected to-internal storage; * ^ Install ·] — «.— Order --------- Γ Please read the back Please fill in this page again for attention) 473940 A7 _B7_ 5. Description of the invention () The invention also provides a non-volatile memory circuit, which is structured on a semiconductor substrate, including: a plurality of dynamic random access memory cells, a plurality of non-volatile memory cells Volatile rewritable transistors, such as 0NO flash memory cells, and a data buffer. Each dynamic random access memory cell includes a control transistor with a first gate, a first source, and a first drain. A first gate is connected to a first word line, and a first source is connected to a first bit line; and a storage capacitor is connected to the first drain of the control transistor, and the control transistor controls the storage capacitor Data storage. Each non-volatile rewritable transistor has a second gate, a second source, and a second drain. The second gate is connected to a second word line, and the second drain is connected to the phase. The first drain of the adjacent control transistor and the second source are connected to a second bit line. The data buffer connects each first and second bit line. Among them, the storage capacitor and the non-volatile rewritable transistor are transferred through the data buffer, so that the storage capacitor and the data stored in the adjacent non-volatile rewritable transistor can be converted to each other. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, including the first, the second, the last, the last, the last, and the last. Pieces are connected one by one to the first in the Yuan Yuan, and then the first and second in the memory and the pole, and the pole source body is connected to the pole and the body source is a crystal. The first half of the first and the first storage and storage of the first Yuan Shengsheng,, control, and, the hair pole pole line to the material pole line two swing gate access to the bank gate non-non-single-character and two-character first $ electricity second To Yiming has the first electric storage, the first receiving supply, a # storage device, a series of notebooks, to the storage system, and the body is also connected to the 4 control body, and the source is used for crystal connection. The first electrode of the electrode, the brake element is electrically written, and the second one is controlled by the law. The first control of the first electrode can be used. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 473940 When the power is turned on Printed A7 in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Ministry of Economic Affairs. 5. Description of the invention () and non-volatile erasable transistor By connecting the first AND-A to a conversion circuit, the method includes the following steps: After the electricity of the 70-line connection is turned on, the conversion circuit of the non-volatile erasable transistor is turned on! Second bit Line to the conversion circuit, and then from the conversion circuit to the storage via the first bit line (2) After the data transfer, turn off the non-volatile dM left Φ > erase the transistor, and store the data for storage ; And (3) before the power is turned off, the data stored in the electric blanket will be stored through you-^ you transfer from the conversion circuit to the non-volatile erasable via the first line Write transistor. 5-4 Schematic illustration: The preferred embodiment of the present invention will be described in more detail in the following text with the following figures: Figure 1 shows the non-volatile elements of the present invention Circuit diagram. Figure 2 illustrates the non-volatile bank of the present invention. In 70 cases, it is a schematic cross-sectional view of the structure of ONO flash δHY cells. FIG. 3 shows the non-volatile memory device of the present invention using the DRAM operation mode when it is used. FIG. 4 shows the non-volatile memory element of the present invention. Before closing, the ancestor stored in the DRAM memory cell ^... Is transferred to the corresponding ONO flash memory cell. Fig. 5 shows the non-volatile of the present invention, the Qianyi Health Awareness File. When the power is turned on, the data stored in the flash memory cells of the NONO flash memory is transferred to the corresponding paper standard. The Chinese standard is applicable. (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) | Install i, ------- order ---------. 473940 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () DRAM memory cell. Description of drawing numbers: TC control transistor C storage capacitor TS non-volatile rewritable transistor WL-F non-volatile rewritable character & WL-D㈣ random access memory character line BL- F Bit line of non-volatile rewritable transistor BL-D Bit line of dynamic random access memory 10 〇ΝΟ Flash memory cell 12 Semiconductor substrate 14 Source 16 Drain 18 Silicon oxide layer 20 Silicon nitride layer 22 Silicon oxide layer 24 Gate conductive layer 5-5 Detailed description of the invention: The present invention discloses a circuit structure of a non-volatile semiconductor memory element and a method for operating the same. The process integration is high, the manufacturing cost is low, and it also has dynamic random storage. The advantages of memory access (DRAM) and flash memory (Fiash EEPROM) 'has high memory capacity' fast data access is simple and non-volatile. μ Please refer to the f 1 figure ', which shows the non-volatile memory element IIIIII ΙΓ I AW · I 1 II 1 II ^ · 11111111 l · II (Please read the precautions on the back before filling this page) 473940 A7 B7 V. Description of the circuit (circuit diagram. The non-volatile memory element of the present invention includes a DRAM memory cell and a non-volatile socks. The body. The DRAM memory cell has a 1 τ- 丨 c structure. It is better to write a solid stamp every day (please read the notes on the back before filling this page). The memory cell includes a control transistor tc, and a storage mine. The transistor TC has a first gate. The first source, the first source, and the first gate are connected to the first word line, that is, the word line WL of the DRAM. The first source is connected to the first bit line, that is, the bit line Bl of the DRAM. The pole is connected to the storage capacitor c. The transistor TC is controlled by the operation of the word line wl_d and the bit line BL_D, and the data can be stored in the storage / electricity C 'or the data can be read from the storage capacitor c. Ministry of Economic Affairs Printed by Intellectual Property Bureau's Consumer Cooperative, beside DRAM memory cell Connected with a non-volatile rewritable transistor TS, such as a flash memory cell, as a non-volatile storage memory element. Among them, an ON flash memory cell is the best, and its structure is similar to "DRAM control transistor TC, The process integration is extremely high, which makes it easy to integrate in the same block with the dram memory cell. Taking qNC) flash memory cell as an example, the non-volatile erasable transistor Ts has a second gate, a second source, and The second drain electrode and the second gate electrode have a silicon oxide-silicon nitride-silicon oxide (ONO) layer and a gate conductive layer thereon, such as a polysilicon layer. The data is stored In the middle silicon nitride layer, the transistor TS is made nonvolatile. The second gate is connected to the second word line, that is, the word line WL-F of the flash memory cell, and the second source is connected. To the second bit line, that is, the bit line bL_f of the flash memory cell, the second drain is connected to the first drain of the control transistor TC, because the control transistor TC is adjacent to the rewritable transistor TS and the first One drain electrode and second source electrode are in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm 473940 V. Description of the invention (B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, so the first drain and the -th zone can be used to increase the component capacity and the use of a common source / impulse. (The first and second bit lines BL_D and BL-FBuffer), ,,, and the mouth. The connection between the storage capacitor C and the rewritable Beco can pass through this data buffer ", and the data stored in θ-day household weight is _ { Mutual conversion 'will transfer the stored lightning rh 2 to the data buffer, and then from the data buffer: body TS; or reversely transfer the rewritable transistor = electricity to the data buffer, and then from the data buffer to The storage capacitor, which is a step-by-step description of the month of 0N0 flash memory cell b. Learn how to use 〇ΝΟ flash but make readers do it. …, Advantages. Please refer to FIG. 2 for a schematic cross-sectional view of the structure of the basin ……, 〇Ν〇 flash memory cells. For example, the flash memory 10 series is structured on a semiconductor substrate, two source electrodes 14 and 16 electrodes, and the structure source electrode 14 and the gate stack layer on the gate. The gate stacked layer includes an ONO layer composed of an oxidized η oxygen oxidized layer 22, and a gate electrode layer 24 on the front side. Among them, the gate conductive layer u is composed of, for example, polycrystalline silicon. The hot electron injection technology, or "!", Is stored into the gasified stone layer 2 on the 6 side by the stored charge, which is the circle in the figure. And 'using a thermal hole injection technique to neutralize the stored charge to erase the data stored in the silicon nitride layer 20. Because the flash memory cell 10 (ie, non-volatile rewritable transistor # 473940 A7 B7 V. Description of the invention (TS)) is very similar to the structure of the traditional DRAM control transistor TC, only an additional silicon oxide layer 1 8 and silicon nitride layer 20, so during the manufacturing process, its process integration is very high, only need to deposit the silicon oxide layer 18 and the nitride layer 20, and other process steps can be controlled with the transistor Integration, co-production. Therefore, its production cost is low, no additional operation cost is needed, and a memory element with a high accumulation degree can be easily produced. As for the detailed description of ΟΝΟ flash memory cells, please refer to us pat ^ t No. 5, 1 68,334 and No. 5,768,192. As for the method of operating the non-volatile memory element of the present invention, it mainly includes three parts. First, please refer to Figure 3. After the power is turned on for a period of time, 'the data is accessed, and the erasable transistor τ! State' is only recorded by the DRAM memory cell (including the control transistor TC and = valley C) Memories, like the circle in the picture
記憶胞的各種優點，如快速存 ’ DRAM 造成的耗損問題。 子取貝枓，且無循環操作所 接著請參照第4圖，在電源即 記憶胞中儲存電容c所儲存才，將draM 線bl-d傳送到轉換電路，次:咳，經由第—位元 換電路經由第二位元線緩衝區’然後再從轉 晶體TS，寫入非揮發性可 r二非揮發性可抹寫電 電晶體TC均為開啟狀態，:體Ts冲。此時控制 抹寫電晶體TS為非揮發性/生傳導之用。由於可 仍然能保留其儲存的資料。 即使電源關閉之後， 中 297公釐）Various advantages of memory cells, such as the problem of wear and tear caused by fast storage DRAM. Sub-beam, and there is no cycle operation, please refer to Figure 4, then the power is stored in the storage capacitor c in the memory cell, and the draM line bl-d is transmitted to the conversion circuit, times: cough, via the first bit The switching circuit passes the second bit line buffer ', and then writes the non-volatile volatile non-volatile rewritable transistor TC from the transistor TS to the on state: the body Ts. At this time, the erasing transistor TS is controlled for non-volatile / generated conduction. Because it can still retain its stored data. (Even after the power is turned off, medium 297 mm)
-------------· I --------^--------l· I (請先閱讀背面之注意事項再填寫本頁) 473940 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 請參照第5圖，在電源開啟之後，首先將非揮發性 可抹寫電晶體TS中所儲存的資料讀出’經由第二位元 線BL-F傳送到轉換電路，如資料缓衝區’然後再從轉 換電路經由第一位元線BL-D傳送到DRAM記憶胞的儲 存電容C。因此，在DRAM記憶胞正常操作之前，即先 將資料存入DRAM記憶胞之中，使DRAM記憶胞可以根 據前一次的紀錄繼續工作。所以’在資料存入DRAM記 憶胞之後，關閉可抹寫電晶體TS，僅以dram記憶胞 進行存取，如第3圖所示。 使用本發明之非揮發性記憶元件’因為DRAM記憶 胞與可抹寫電晶體TS相對比鄰，所使用之結構相對較 為簡單，並且簡化電路，故使得存取路徑縮短，可大大 增加資料轉換時的存取速度。 以本發明之非揮發性記憶元件為記憶單元可組成一 個記憶陣列，再加上習知的週邊電路即可構成一個完整 的記憶體。此記憶體包括記憶陣列，和資料緩衝區，作 資料的轉換，以及其他的周邊電路，如位址解碼器 (Address Decoder)以及輸入/輸出電路（I/O)等。其中，記 憶陣列由複數個本發明之非揮發性記憶元件所構成，每 一個5己憶元件如前所述至少包括一個控制電晶體TC、一 個儲存電容C、以及一個非揮發性可抹寫電晶體TS。 10 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） -----—,----裝 —I—訂--------- (請先閱讀背面之注意事項再填寫本頁) 473940 A7 五、發明說明（） 綜合以上所述，本發明揭露— 裡非揮發性本莫辦 憶元件，將DRAM記憶胞與非揮發性导體5己 可制Λ、曰士 寫電晶體配合， 了製成具有非揮發性的dram記恃俨 _ ^ 一 ，—θ 體，兩者製程相容性 兩，極谷易結合，且不會增加過多額卜 y邱邛的成本，其製作 成本低廉，而且兼具DRAM記憶胞與非揮發性可抹寫電 晶體的優點，可以快速存取資料，元件壽命長久，並且 為非揮發性，即使電源關閉依然可以長久保持資料完整。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍，凡其它未脫離本發明所揭 示之精神下所完成之等效改變或修飾，均應包含在下述 之申請專利範圍内。 ----\----- ----------------. (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 各紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）------------- · I -------- ^ -------- l · I (Please read the notes on the back before filling this page) 473940 Economy Printed by the Consumers ’Cooperative of the Ministry of Intellectual Property Bureau A7 B7 5. Description of the invention () Please refer to Figure 5, after the power is turned on, the data stored in the non-volatile rewritable transistor TS is first read out via the second The bit line BL-F is transmitted to the conversion circuit, such as a data buffer, and then is transmitted from the conversion circuit to the storage capacitor C of the DRAM memory cell through the first bit line BL-D. Therefore, before the normal operation of the DRAM memory cell, the data is first stored in the DRAM memory cell, so that the DRAM memory cell can continue to work according to the previous record. Therefore, after the data is stored in the DRAM memory cell, the rewritable transistor TS is closed, and only the RAM memory cell is used for access, as shown in FIG. 3. Using the non-volatile memory element of the present invention, because the DRAM memory cell is relatively adjacent to the rewritable transistor TS, the structure used is relatively simple, and the circuit is simplified, so that the access path is shortened and the data conversion time can be greatly increased. Access speed. The non-volatile memory element of the present invention can be used as a memory unit to form a memory array, and the conventional peripheral circuit can be used to form a complete memory. This memory includes a memory array, a data buffer, and data conversion, as well as other peripheral circuits, such as address decoders and input / output circuits (I / O). The memory array is composed of a plurality of non-volatile memory elements of the present invention. Each of the 5 memory elements includes at least one control transistor TC, a storage capacitor C, and a non-volatile erasable electrical device as described above. Crystal TS. 10 This paper size applies to China National Standard (CNS) A4 specification (21〇X 297 mm) -----—, ---- Installation—I—Order --------- (Please read first Note on the back, please fill in this page again) 473940 A7 V. Description of the invention () Based on the above, the disclosure of the present invention is a non-volatile memory device, which can be produced by combining DRAM memory cells and non-volatile conductors. The combination of Λ and Shishi writing transistors has been made into a non-volatile dram 恃 俨 ^ ^ ，, θ body, the two processes are compatible, the valley can be easily combined, and it will not increase too much. Qiu's cost, its low production cost, and the advantages of both DRAM memory cells and non-volatile rewritable transistors, can quickly access data, long component life, and non-volatile, even long time the power is off Keep the information complete. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of patent application. ---- \ ----- ----------------. (Please read the notes on the back before filling out this page} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Each paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm)