478084 五、發明說明（1) 發明之領域： 本發明係有關於一種覆晶晶片，尤指一種易於進行電 路棟針測試之覆晶晶片。 背景說明： 在現代的資訊社會，以積體電路構成的微處理機系 統，早已被普遍運用於生活的各個層面。舉凡自動控制之 家電用品、行動通訊設備、個人電腦’無不可見積體電路 之蹤跡。積體電路的主體，就是經由半導體製程備製的晶 片（ch i p )。 製造晶片的過程，是先由備製一晶圓（wafer)開始。 在一片晶圓上，可區分出多個區域，並在每個區域上，利 用半導體製程形成各種電路；經由晶圓選別，例如以電路 探針（c i r c u i t p r 〇 b e )測試各區域中電路之品質後，再對 晶圓上的各個區域進行切割而成各個晶片。 得到晶片後，還須經過一定的方式，將晶片電連至一 電路板（如印刷電路板）；如此一來，晶片就可透過電路 板得到電源供應，舉例而言：透過電路板接收或發送資 料，達到微處理機系統整體的功能。至於晶片電連至電路 板的方式，可以是將晶片直接電連至電路板之裸晶（bare478084 V. Description of the invention (1) Field of the invention: The present invention relates to a flip-chip wafer, especially a flip-chip wafer that is easy to perform a pin test of a circuit. Background: In the modern information society, microprocessor systems composed of integrated circuits have long been used in all aspects of life. Jufan's automatic control of home appliances, mobile communication equipment, and personal computers' has no visible traces of integrated circuits. The main body of the integrated circuit is a wafer (ch i p) prepared through a semiconductor process. The process of manufacturing a wafer begins by preparing a wafer. On a wafer, multiple regions can be distinguished, and on each region, various circuits are formed using semiconductor processes; after the wafer is selected, for example, the quality of the circuits in each region is tested with a circuit probe (circuitpr). Then, each area on the wafer is cut into individual wafers. After the chip is obtained, the chip must be electrically connected to a circuit board (such as a printed circuit board) through a certain method; in this way, the chip can receive power supply through the circuit board, for example: receive or send through the circuit board Data to achieve the overall function of the microprocessor system. As for the way to electrically connect the chip to the circuit board, it can be to electrically connect the chip directly to the bare die of the circuit board.
478084 五、發明說明（2) ch i p)配置法，或是將晶片封裝於一封裝體後，經由封裝 體内的電連通路，再電連至電路板；也就是循晶片、封裝 體至電路板之電連通路。 請參考圖一及圖二。圖一為一習知晶片1 0之上視圖。 圖二為晶片1 〇經打線方式電連於外部電路（未顯示）之示 意圖。習知晶片1 0在晶片的周圍設有銲墊（bonding pads) 1 2，可以經由導電的聯結線（b ο n d i n g w i r e ) 1 4電連至外界 的電路，像是電路板或是封裝體中的電連通路。這種習知 晶片在業界已沿用許久，對這種類型的晶片進行電路探針 測試之方法與設備均廣為熟知，技術已成熟且成本低廉。 雖習知以打線方式電連於外之晶片1 0已為業界習用， 但其聯結線長，易導致電感增生其上，對晶片在高頻的運 作極為不利；近年來已有另一種電連方式正在發展中。請 參考圖二與圖四。圖二為^一習知晶片2 0之上視圖。圖四則 為晶片2 0電連至外部電路2 6之示意圖。晶片2 0的下表面具 有複數個排列成格狀陣列的銲墊2 2。當晶片2 0要電連至外 部電路2 6 (請參考圖四）時，會在每一個銲墊2 2上附上可 導電的凸塊（bump) 24，以電連至外部電路2 6上與各銲墊22 位置對應的銲點2 8。外部電路2 6可以是電路板或是封裝體 的基板。因為這種電連接方式是將晶片2 0覆置於外部電路 2 6之上，故稱為覆晶（flip-chip)。478084 V. Description of the invention (2) ch ip) configuration method, or the chip is packaged in a package, and then electrically connected to the circuit board through the electrical communication path in the package; that is, through the chip, the package to the circuit Electrical connection of the board. Please refer to Figure 1 and Figure 2. FIG. 1 is a top view of a conventional wafer 10. Figure 2 is a schematic diagram of the chip 10 electrically connected to an external circuit (not shown) by wire bonding. The conventional chip 10 is provided with bonding pads 12 around the chip, and can be electrically connected to an external circuit through a conductive bonding wire 1 4 such as a circuit board or a package. Electrical communication. This conventional chip has been used in the industry for a long time. The methods and equipment for circuit probe testing of this type of chip are widely known, the technology is mature and the cost is low. Although it is known that the chip 10, which is electrically connected to the outside by wire, has been used in the industry, the length of the connection wire easily leads to the increase of inductance, which is extremely detrimental to the operation of the chip at high frequencies. In recent years, there has been another type of electrical connection. Ways are developing. Please refer to Figure 2 and Figure 4. FIG. 2 is a top view of a conventional wafer 20. FIG. Figure 4 is a schematic diagram of the chip 20 electrically connected to the external circuit 26. The lower surface of the wafer 20 has a plurality of pads 22 arranged in a grid array. When the chip 20 is to be electrically connected to the external circuit 2 6 (refer to FIG. 4), a conductive bump 24 is attached to each of the pads 2 2 to be electrically connected to the external circuit 2 6. The solder joints 2 8 corresponding to the positions of the respective solder pads 22. The external circuit 26 may be a circuit board or a substrate of a package. Because this electrical connection method is to place the chip 20 on the external circuit 26, it is called a flip-chip.
五、發明說明（3) 丨好，ί ϊ ΐ連之？連通路短〜 ' '^-— 在進行電路探針測試；片”旦其排列成格狀：工控制的很 插槽(响)，“；行：須要有特；的i:L口塾， 測試時’必須要將電路探：路探針測試。在進行電：j或 )中的銲墊電連接，* 與晶圓上各區* (晶J t: 晶片2_列成格狀陣列的鲜以域質。要； 的格狀陣列的電連探頭，或是特鉍針也要有對應 特殊的測試設備需求，使得覆晶之晶 J :soc^et)。這些 格高昂。況且覆晶晶片的規格不_ s，曰使二f，針測試價 針測試無法普及’且成本居高不下。另:g ,路探 係覆置於外部電路26上，使得工程人員盔 ^ ^ =晶片 L, (debug) ^ ^ ^ ^ 因此，本發明之主要目的在 探針測試 於提供一種覆晶晶片 以適用價格低廉之習知電路^〃一… 路探針測試的成本 以降低覆晶晶片 可 電 發明之詳細說明 為了解決習知覆晶晶片進行電路探針測試的難題，本V. Description of the invention (3) 丨 Good, ί ϊ ΐ 之The connection path is short ~ '' ^ -— The circuit probe test is being performed; the piece "Once it is arranged in a grid: the industrial control is very slot (loud),"; the line: requires special features; i: L 口 塾, During the test, the circuit must be probed: the way probe test. The electrical connection of the pads in the electrical: j or), * and the various regions on the wafer * (crystalline J t: wafer 2_ row of the grid array array of fresh domain quality. To; the electrical connection of the grid array Probes, or special bismuth needles, also need to correspond to special test equipment requirements, so that the flip-chip crystal J: soc ^ et). These are high. Moreover, the specifications of flip-chip wafers are not _s, that is, two f, the pin test price cannot be popularized and the cost is high. In addition: g, the road detection system is placed on the external circuit 26, so that the engineer's helmet ^ ^ = wafer L, (debug) ^ ^ ^ ^ Therefore, the main purpose of the present invention is to provide a flip chip wafer for probe testing. Applicable to low-cost conventional circuits ^ 〃 ... The cost of circuit probe test is to reduce the detailed description of flip chip wafers.
j 五、發明說明（4) ^明ί覆晶晶片設有複數個凸塊墊幽 圖f f本發明覆晶晶片30之上視圖’: 面设有排列成格狀陣列的複 32陣列之外的複數個銲塾 ，列，可用於覆晶時與一外部 f 本f明覆晶晶片30的周緣。本 以提供電路探針測t式時之電連通^覆 > θ由於電路探針測試要以電 京f是晶片的前身）電連，而習 2列排列，必須以特製高密度 2 f試之成本無法降低。本發 34,提供電路探針測試時 ΪΪΙ4排列的方式可以在規格 =方式，覆晶晶片30便可沿 日t ^，則试，以銲墊34作為電連 】：用的電路探針，可以沿用 打線晶：5袼狀陣列特 展又计之電路探針測試 電=，本發明之覆晶晶片能； 叙針本身之維修 果也非常可靠。 鲜塾。請參考圖五。 在覆晶晶片3 0的上表 墊3 2與排列在凸塊墊 凸塊墊3 2成格狀陣列 連。銲塾3 4可排列在 晶晶片的鮮塾3 4可用 與日日圓上各區域（也 晶晶片之銲墊成格狀 捸針測試，使電路探 晶片30中具有複數個 通路。因為晶片3 〇的 知之打線晶片鲜塾之 用於打線晶片之電路 探針的電連通路。此 2線晶片設計之電路 密度之電路探針。為 本低廉，且技術已發 電路探針測試，不僅 本降低，測試的結 於本發明之一實施例中 覆晶盖 3 〇在電連於外部電 478084 五、發明說明（5) ，時，仍會使用排列成格狀陣列的凸塊墊3 2。請參考圖 六。圖六為本發明覆晶晶片3〇與外部電路56電連之示意 ，二，晶晶片30與外部電路56電連時，各凸塊塾32上$具 =電的凸塊3 8 ;外部電路5 6上則有與凸塊塾3 8位置對 當=58，來和晶片3°形成電連接通道。這裡的“ 電路板，或是封裝體中的-塊基板…於 ^路^十^式之銲墊34則不與外部電路56電連，也就是 ^ *曰曰片30被實際使用時’銲墊34可以沒有任何作用。 線封Ϊ ί :明J ::施例’ ’銲墊34則可提供晶片30打 之封驻士士 l ^適用於晶片3 0之後段測試，以節省可颧 、 及便於覆晶晶片電路特性之探測（pr〇be )。 明覆的電路探針測試，本發 通路給電路探m2多的鈐墊，以提供足夠多的電連 另一# f = t針。清參考圖七。圖七為本發明覆曰日= 貝％例4 ί!。曰u d λ , kQ ^ Ί復曰曰曰曰片的 ^ ^ (sta^e!)^\ 1 , ^ ^ ^ ^ ^ ^ ^ ^ ijt j：» 」之方式排列，而凸塊塾4 2仍紐# =Z需個數較多之銲塾，則鲜=持格狀陣列 路=2;數量之測試塾…提供提 排列為二塔4木針測试。當然’本發明中 的— (trl—tier)結構，進一步提供另可 的選擇。 另一種銲塾排列j V. Description of the invention (4) ^ Ming flip chip is provided with a plurality of bump pads. ff Top view of the flip chip 30 of the present invention. A plurality of welding pads and columns can be used to clarify the periphery of the flip-chip wafer 30 with an external chip f. The purpose of this article is to provide electrical probes when measuring t-type electrical connections. ^ Because the circuit probe test is based on the electrical connection of the chip f (the predecessor of the chip), and the two-row arrangement, you must use a special high-density 2 f test The cost cannot be reduced. The hairpin 34 provides the circuit probe test when the ΪΪΙ4 arrangement can be in the specification = mode, the flip-chip wafer 30 can be along the day t ^, then try to use the pad 34 as the electrical connection]: The circuit probe used can Continued use of wire-bonded crystals: The circuit of the 5 pin-shaped array is specially designed to test the electrical test, the chip-on-chip wafer of the present invention can be used; and the maintenance of the needle itself is also very reliable. Fresh. Please refer to Figure 5. On the top surface of the flip-chip wafer 30, the pad 32 is connected to the bump pads 32, which are arranged in a grid array. The solder pads 3 4 can be arranged on the wafer. The pads 3 4 can be tested with various areas on the Japanese yen (also the pads of the wafers are grid-shaped pin tests, so that there are multiple paths in the circuit probe 30. Because the wafer 3 〇 The wire connection chip of the Zhizhi wire is fresh, and the electrical communication circuit of the circuit probe for the wire chip. The circuit density circuit probe of this 2-wire chip design. It is cheap and the technology has sent the circuit probe test, which not only reduces the cost, The test result is that the flip-chip cover 3 in one embodiment of the present invention is electrically connected to the external electrical 478084. V. Description of the invention (5), the bump pads 3 arranged in a grid array will still be used. Please refer to Figure 6. Figure 6 is a schematic illustration of the electrical connection of the flip-chip wafer 30 and the external circuit 56 of the present invention. Second, when the wafer 30 is electrically connected to the external circuit 56, each bump 塾 32 is provided with an electric bump 3 8 ; On the external circuit 5 6 there is a position corresponding to the bump 塾 38 and the position = 58 to form an electrical connection channel with the wafer 3 °. Here, the "circuit board, or the-substrate in the package body ... on the road ^ The ten-type solder pad 34 is not electrically connected to the external circuit 56, that is, the ^ * film 30 is actually used When the 'pad 34 can have no effect. Wire seal :: Ming J :: Example' 'The pad 34 can provide a seal of 30 dozen wafers in the taxi ^ It is suitable for the subsequent test of the wafer 30 to save It can be used to facilitate the detection of the characteristics of the flip-chip circuit (pr0). In the overlying circuit probe test, this circuit can detect more m2 pads in the circuit to provide enough electrical connections to another # f = t needle. Refer to Figure VII for reference. Figure VII shows the date of the present invention = shell% Example 4 ί !. ud λ, kQ ^ Ί 曰 ^ (sta ^ e!) ^ \ 1, ^ ^ ^ ^ ^ ^ ^ ^ ijt j: »", and the bumps 塾 4 2 are still new # = Z requires a larger number of welding 塾, then fresh = grid-like array road = 2; the number of Test 塾 ... provides a test arrangement of two towers and 4 wooden needles. Of course, the '(trl-tier) structure in the present invention further provides another option. Another welding 塾 arrangement
第8頁 478084 發明說明（6) 本發明中的 成電連接，使銲 係。舉例來說， 試，便可將這些 些銲墊進行所需 試，便不用設置 規格，也可在本 連接之銲墊。另 會由凸塊墊輸出 輸出，以增加額 (layout)中形 電連接對應關 之訊號進行测 ，就可透過這 不須進行測 片電路探針的 任何凸塊塾電 使某些訊號不 欲之測試訊號 銲墊與凸塊墊可在電路佈局 墊與凸塊墊之間具有特定的 若測試時需要對某些凸塊墊 凸塊墊電連接至對應之銲墊 之訊號測試。若某些凸塊墊 對應之銲墊。為符合打線晶 發明之覆晶晶片上設置未與 外，在本發明之晶片中，即 ’仍可設置額外之銲墊將所 外的輸出供測試及除錯。 相車父於習知晶片1 〇，本發明之覆晶晶片可藉由凸塊塾 或銲墊形成不同封裝而與外部電路電連接，故可為覆晶晶 片提供封裝形式之彈性選擇；而習知覆晶晶片2 0必須另行 發展特製的高密度電路探針進行電路探針測試，本發明之 覆晶晶片則可以沿用習知用於打線晶片之電路探針測試， 不僅測試成本可降低，也可得到可靠的測試結果，確保晶 片的品質；在實際構裝後，本發明覆晶晶片仍然具有習知 覆晶晶片的優點，可適用於高速、高時脈之場合。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所作之均等變化與修飾，皆應屬本發明專利之涵 蓋範圍。Page 8 478084 Description of the invention (6) In the present invention, the electrical connection is made and the welding is performed. For example, if you try, you can test these pads. You don't need to set the specifications. In addition, the bump pad output will be used to measure the signal of the corresponding medium-sized electrical connection in the layout. You can make certain signals undesired through any bumping of the bump without the need for the test circuit probe. The test signal pads and bump pads can have a specific signal test between the circuit layout pads and the bump pads. If a test is required, some of the bump pads and the bump pads must be electrically connected to the corresponding pads. If some bump pads correspond to the solder pads. In order to comply with the invention of a wire-bonded wafer, a flip-chip wafer is not provided. In the wafer of the present invention, that is, an additional pad can still be provided to test and debug the external output. The car driver is familiar with the chip 10. The flip-chip wafer of the present invention can be electrically connected to external circuits by forming different packages with bumps or pads, so it can provide a flexible choice of package form for the flip-chip chip; It is known that the flip-chip wafer 20 must separately develop a special high-density circuit probe for circuit probe test. The flip-chip wafer of the present invention can continue to use the conventional circuit probe test for wire-bonded wafers. Not only the test cost can be reduced, but also Reliable test results can be obtained to ensure the quality of the wafer; after the actual assembly, the flip-chip wafer of the present invention still has the advantages of the conventional flip-chip wafer and can be applied to high-speed, high-clock occasions. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.
第9頁 478084 圖式簡單說明 圖式之簡單說明： 圖一為習知打線晶片之上視圖。 圖二為圖一中習知晶片以打線方式與外部電路電連之 示意圖。 圖三為習知覆晶晶片之上視圖。 圖四為圖三中晶片以覆晶方式與外部電路電連之示意 圖。 圖五為本發明晶片實施例之一的上視圖。 圖六為本發明晶片以覆晶方式與外部電路電連之示意 圖。 圖七為本發明晶片另一實施例的上視圖。 圖式之符號說明： 3 2、4 2 凸塊墊 38 凸塊 58 銲點 3 0、4 0 本發明之晶片 3 4、4 4 鮮塾 56 外部電路Page 9 478084 Brief description of the drawings Brief description of the drawings: Figure 1 is a top view of a conventional wire bonding wafer. FIG. 2 is a schematic diagram of the conventional chip in FIG. 1 electrically connected to an external circuit by wire bonding. Figure 3 is a top view of a conventional flip-chip wafer. FIG. 4 is a schematic diagram of the chip in FIG. 3 electrically connected to an external circuit in a flip-chip manner. FIG. 5 is a top view of one embodiment of a wafer of the present invention. FIG. 6 is a schematic diagram of a chip of the present invention electrically connected to an external circuit in a flip-chip manner. FIG. 7 is a top view of another embodiment of a wafer of the present invention. Explanation of symbols in the drawings: 3 2, 4 2 bump pad 38 bump 58 solder joint 3 0, 4 0 wafer of the present invention 3 4, 4 4 fresh 56
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