TW480668B - Silicon-on-insulator diode and its electrostatic discharge protection circuit - Google Patents

Abstract

This invention provides silicon-on-insulator (SOI) diode and its electrostatic discharge protection circuit. A SOI gated diode and a non-gated diode are described. PN junction of the SOI gated diode is located below the central area of the gate electrode, which has more junction area than the conventional diode. PN junction of the SOI non-gated diode is located at the central area, which also has more junction area than the conventional diode. Therefore, the inventive SOI diode has a better protection capability due to its larger junction area to sustain heat produced by electrical overstress and electrostatic discharge. The inventive I/O electrostatic discharge circuit includes a plurality of major diodes, a plurality of first diodes and a plurality of second diodes. These diodes are the inventive SOI diodes. When an electrostatic discharge event occurs, this electrostatic discharge circuit can effectively drain electrostatic discharge current and thus reduce its parasitic input capacitance, which can be applied to radio frequency (RF) circuit or high frequency (HF) circuit.

Description

480668 V. Description of the invention (1) 5-1 Field of invention: The present invention relates to a diode structure having silicon on an insulating layer; in particular, it relates to a diode having silicon on an insulating layer having electrostatic protection ability Body structure and its electrostatic discharge protection circuit. 5-2 Background of the Invention: Due to Shi Xi on the insulation layer (si 1 ic ο η-ο η-insu 1 a ΐ 〇r) in the Shi Xi block technology has reduced process complexity, latch-up immunity ) And smaller junction capacitance, it is a mainstream technology in low-voltage, high-speed technology applications. However, electrostatic discharge is a major concern with silicon on the insulating layer. The protection capability of an ESD protection device is determined by the amount of current it can absorb. During an electrostatic discharge pulse, thermal runaway (then runaway) and subsequent devastating damage will cause the device to fail. In the silicon device on the insulating layer, there is a buried oxide layer having a thermal conductivity of 1/1000 times that of silicon, which will reduce the heat dissipation function of the circuit and accelerate the heat dissipation. The first picture is a description published in 1986? 1 * 〇 (: .〇! £ 03 / ^ 30 Symp. A conventional insulating layer on pages 291 to 301 has a cross section of a silicon diode

Page 5 480668

7F Intent 'The diode structure was proposed by the United States IβM company and is called a Lubistor diode. If the Shi Xi layer above the buried oxide layer 100 is doped with N-type # f ', then there is a Shi Xi r pole junction on this I marginal layer, which is P + m /. The two ends; + 1 ° 2 V1 ~ connected to 〇1 ". If V1 is" positive voltage "relative to" this is a silicon diode system on the insulation layer under forward bias

Vi is negatively charged M with respect to V2, so this bipolar system has a reverse bias =: static = during the period of 'power generation ρ + ι ° 2 / N well junction area compared to' 1; the degree and thermal energy will increase. This Thermal energy is generated at the junction of PN: one: the region, which is mainly Joule heat. When this insulation layer ΪΠ: pole body Ϊ temperature reaches its intrinsic temperature (Tintrins. Sundial, it may be recognized that the electric power is broken) (Second breakdown). In order to obtain better electrostatic discharge protection, its power density and Joule heat must be reduced. Therefore, it is urgent to develop a low power density diode with electrostatic discharge protection on silicon circuits on the insulation layer. … 5-3 Purpose and summary of the invention: The main purpose of this Is Ming is to provide an SOI diode with an SOI diode on its insulation layer, which has a larger bonding area than ordinary diodes. Obtain low-density power and thermal energy, and then improve the protection ability of electrical overvoltage (Eo magic electrostatic discharge (ESD). '480668 V. Description of the invention (3) There is the area of Shi Xi's diode on the edge layer, in Shun Electrostatic discharge of V dd to V ss under a bias Another object of the present invention is to provide a kind of insulation, which has more connections than ordinary diodes, and can be used in I / 0 electrostatic discharge protection circuits and protection circuits. Another object of the present invention is to provide General diodes with more junction area of SOI diodes; [/ 0 Electrostatic discharge protection circuit, which can reduce its parasitic input capacitance ', so it can be applied to radio wave frequency circuits (HF circuits) or high frequency circuits (HF circuits) According to the above-mentioned object, the present invention provides a silicon diode on an insulating layer and an electrostatic discharge protection circuit thereof. The silicon diode (SOI diode) on the insulating layer includes a substrate, an insulating layer, Two shallow trench isolation regions' and a PN junction diode. This pn junction diode system is formed by a first well having a first conductivity and a second well having a second conductivity. This first conductivity The conductivity can be N-type or P-type, and the second conductivity is opposite to the first conductivity. The insulating layer is formed on the substrate, and the two shallow trench isolation regions are formed on the insulating layer. On. PN junction diode system is formed here Between shallow trench isolation areas, and an electrostatic discharge protection circuit having a diode on the insulation layer includes an electrically conductive ive pad, a conductor segment, and a first A first voltage supply rail, a second voltage supply rail,

Page 7 480668

V. Description of the invention (4) King Yue Yi The first main diode and a plurality of second diodes. All are formed on this insulating layer. This conductive pad node. The first main two-pole system is connected between the columns, and the second main two-pole system is provided between the columns. The directions between the plurality of first dipole voltage supply columns are the same. Between a plurality of second dipole system connection columns, their directions are opposite to the f-th diode, the plurality of first dipoles, and some ESD protection element systems are connected to the first via this wire !: Dry A node and a first voltage supply are connected to the first node and a second voltage system are connected to the first node and the first phase, and a main diode is provided at the first node and the second voltage on the side of the first main diode. Direction. The purpose and many advantages of the present invention will be explained in detail by referring to the accompanying drawings and the following specific embodiments.

-4 Detailed description of the specific embodiment The second figure is the intention of the diode structure of s0〗 proposed by the present invention. The structure of the second figure includes a substrate 2000, for example, a PV or P + substrate, and an-insulating layer 201, such as a buried silicon dioxide layer: formed on the substrate 2000. Two shallow trench isolation regions 2 0 2 [above the insulating layer 201, and a silicon p-well (p wei i on e siiia layer ·) 2 0 3 and a silicon material N-well 2 04 are formed in the insulating layer Between the two shallow trench isolation regions 202 above the 201. Wells P 03 and N? 〇 4 constitutes a structure with silicon (SOI) on the insulating layer. First first doping ^

V. Description of the invention (5) The $ put area 2 05 is formed at the top corner of the ρ well 2000, and a second adjacent-shallow trench isolation area 2 ~ well 2. 4 adjacent another-" The diffusion zone 2 ◦ 6 series is formed at the top corner of the MOS pole 2 07 series to form the φP well m02.-It seems that the P wells 203 and "20%" are in: 2: 3, well 2 Above 0 4 and below 7 „The F ^ mouth is located in the Q region like M0S gate V. This is like M 0s gate plant P n Z ◦ Yan f, — polycrystalline stone _, a dielectric Including a dielectric layer 22 and a pole system formed on the dielectric layer 208; ". The polycrystalline silicon region 209a and a fourth heavy dopant are composed of a third heavily doped P + diffusive spacer P! N, which is expanded and conditioned by 209b. The thunder-thickness I 〇 system is formed on the mother side of the MOS-like closed electrode 207/1 / the first heavily doped P + diffusion 恧 9 n q ^ 7. 9 b # w " 9 a and the fourth heavily doped N + diffusion region? The second series of Ω is formed on top of this polycrystalline silicon closed electrode, the 20 p + diffusion region 205 and the -d, the first heavy doping is aligned with the ""! Ϊ́ doped N + diffusion region The 2 0 6 series are respectively half-doped in the second heavily doped P + diffusion region? Knife is J mesh region 2 0 9 b., The shape 2 0 9a and the fourth heavily doped N + diffusion one have silicon on the insulating layer. The (S〇I) bipolar system is formed by p well 2 0] and 2 0 4, and this S0I diode 2 ″ ″ well Μ〇ς ^ ο π 丄 4 is located here. Like the middle area below A η 207. Because the present invention has a p-well 2 0 4 bipolar body which has more than ρ + / N or N + / ρ well 浐 < bistor diode (as shown in Figure _) has more The connection area, the S01 unipolar body has lower power density and heat, and improves electrostatic discharge protection. This is OK

Page 9 V. Description of the invention (6) The first picture is the second picture. A 305 series is formed at p <a variation. A first lightly doped P-diffusion region is at the top corner, and a second 303 adjacent to a shallow trench isolation region 302 is adjacent to another shallow ^ hetero-N-diffusion region 306 is formed at N Well 3 crystalline silicon gate 307 package ^ at the top corner of the f region 3 002. This is similar to M0S. A fourth lightly doped diffusion ^ | a third lightly doped p-diffusion region 3 09a and ytterbium and a fourth lightly doped two P 9 b. The third lightly doped P-diffusion region 3 0 9 a above the second 3 7 f region 3 0 9 b is formed by a polysilicon gate, and is connected by conduction. The V electric layer 'is preferably a self-aligned metal silicide, an insulating layer on the right, and the N-well 304-the pole body (S01 dlode) is composed of the P-well 303 polycrystalline silicon gate electrode 300. The PN junction of this diode is located in the muscle-like § υ υ (middle region below. Five-well 02 corner groove trench 4 three light 9 b &lt; 4 η doped ρ diagram + i ΐ :: one Variation. In this variation, the first and the first light i; p are between the-shallow trench isolation region 4: the sixth heavily doped diffusion region 4 and the top of the syring well 4 0 3 = region ... And the second lightly doped N_㈣; the open region = at the other- shallow top corner. This is like a doped P-diffusion region 4 0 9a between the M0S polycrystalline gate and the fourth lightly doped. : NO: Including-the third lightly doped p-diffusion region 4 0 a and the fourth lightly-doped diffusion region 4 0 b are conductive with one formed over the polycrystalline silicon gate 4 0 ^ hetero-N-diffusion region 480668 V. Description of the invention (7) The layer 'preferably is a self-aligned metal silicide layer for conducting connection. /, There is a silicon diode system on the edge layer? Wells 403 and 1 // well 4 0 The PN junction formed by 4 is located in the middle area below the MOS-like polycrystalline silicon pole 4 07. = The fifth picture is another variation of the second picture. The insulating layer has silicon (S01) structure 2 silicon thickness Is completely a first heavily doped P + diffusion region 5 0 5 and a jth doped doped + Diffusion zone 5 Q 6 is occupied (hlly depleted). The insulation: Shiyou Shixi bipolar system is formed by ... 〇3 well 5 〇 2 = t-PN junction of the pole body is located like M0S The middle area below the polycrystalline silicon gate 5 07. / w Hyun 3 J :, is another variation of the second picture. Here the diode is formed in the polycrystalline silicon gate 6 0J like M0S for a long time. The pole 6 0 7 can be a lightly doped or 0 heavy 7 doped mid-doped ::, this is similar to _. An insulating layer has a silicon diode system made of p-well 6 〃 n or N-type regions, and its PN junction It is located in the area shaped by the MOS polycrystalline silicon gate well 604. The seventh layer of the middle layer below U 7 is another variation of the second figure. E The diode with silicon on it does not have a gate structure In the modified example, the insulator is an insulator. There is a silicon diode wound on the insulation layer: it is called the gateless junction 2. It is formed by P ”〇3 and N” 〇 $ 11 pages 480668 V. Invention Description (8)

The eighth figure is a specific embodiment of the SOI electrostatic discharge protection circuit including the SOI diodes of the second to seventh figures. Electrostatic discharge protection circuit 800 includes a conductive input pad 801, two main diodes D1 803, 1) 2 8 〇4, a Vdd voltage supply column 805, a Vss voltage supply column 806, an input Resistance (input resistor) 8 0 7. A plurality of first diodes (Du 1 to Dun) connected in series 8 0 8. A plurality of second diodes (Ddl to Ddn) 8 0 9 connected in series. All these diodes are

The insulating layers in the specific embodiments shown in FIGS. 7 to 7 are formed by silicon diodes. The input 塾 8 0 1, the Vdd voltage supply line 8 0 5, the Vss voltage supply line 8 0 6, and the input resistance 8 0 7 are all the same as the two-pole system with silicon on these insulation layers formed on the same insulation layer. Connect to the 8th series of the second diode. Connect these two directions. The direction of the complex node 8 is 〇 7 and 0 801 is connected to a first node 802 through a conductor segment. The main diode D1 8 0 3 is connected between a node 8 0 2 and the Vdd voltage supply line 8 05, and the main body D 2 8 4 is connected between the first node 8 0 2 and the Vss voltage supply 0 f. Plural first diodes (Dul to!) ^) 8 〇 8

Between the first node 802 and the Vdd voltage supply column 805, the direction of the polar body is opposite to that of the main diode D1 8 0 3-the number of diodes (Ddl to Ddn) 8 0 9 It is connected between the first 0 2 and the V ss voltage supply line 8 0 6. These diodes are opposite to the direction of the main one D 2 8 0 4. Input resistance 8 is connected to 泫 ΛΛ-, Le-Lang point 8 0 2 and the inside to be protected by electrostatic discharge

Page 12 480668 Description of the invention (9) :: 8 1 〇 However, the input resistance 8 007 can also be coupled to the input buffer of the two circuits 8 1 〇, and a "input resistance 807" and this input buffer. Occupation is located when an electrostatic discharge event will be relative to The Vdd voltage supply line 8 is positive, and when the pressure is applied to the input pad 800, the main diodes m 8… f are forward biased, and because the Vss voltage supply line 8 is drifted ^ the main pole The body D 2 8 〇4 has not been opened. Therefore, the electrostatic discharge is discharged through the main diode D1 8 0 3 to the Vdd voltage supply line 8 U 5. Similarly, when an electrostatic discharge event occurs, a voltage relative to Vss The negative voltage of the supply line 8 06 is applied to the input pad 8 0 丄, the main diode 2 8 04 is forward biased, and because the Vdd voltage supply line 8 05 is floating, the main diode D1 is 8 0 3 has not been opened. Therefore, the static electricity ..., the discharge current is discharged to the Vss voltage column 8 0 6 via the main diode D2 8 0 4.,, Should, when an electrostatic discharge event is to supply a voltage relative to Vdd The negative voltage of column 8 5 is applied to the input pad 8 0 1. The main diode D 1 8 0 3 is reverse biased. The Vss voltage supply line 8 0 is floating. The plurality of first diodes (Du 1 to Dun) 8 0 8 are forward biased in this case, so the electrostatic discharge current passes through the plurality of first Diode

Dun).

Page 13 480668 V. Description of the invention (10) When the electrostatic discharge event is to supply a positive voltage to the input pad 8 0 1 with respect to the Vss voltage supply line 8 0. The main diode 804 is reverse biased. During this electrostatic discharge event, the Vdd voltage supply column 805 was in a floating state. The plurality of second diodes (Ddl to Ddn) 8 009 are forward biased in this case, so the electrostatic discharge current passes through the plurality of second diodes (Ddl to Ddn) 8 0 9 emission. The ninth figure is another specific embodiment of a circuit including a diode having silicon diodes on an insulating layer according to the second to seventh figures. This electrostatic discharge protection electricity :: Contains a conductive output pad 9 0 i, main diode D1 9 0 3 and 1) 2 0 4, Vdd voltage supply line 9 0 05, Vss voltage supply line 9 0 6, a : Double-diodes (Dul to Dun) 9 0, and plural second dipoles (Ddl to Ddn) 9 0 9. All of these two poles are formed by the Shi Xi diodes on the insulation layers of the second to seventh pictures. 9 V1, Vdd voltage supply line 9 0, Vss voltage supply line '::: In these insulation The two-pole system of Shi Xi is formed on the layer to form a same absolute output. The 9 0 1 series is directly connected to a node 9 2 via a wire. The main diode D1 9 0 3 is connected between nodes 9 0 2 and 9 05, and the main diode 9 0 4 is expected to coincide with 2 2 2 Γ κ Γ between 9 0 6. A plurality of -diodes (Dul to Dun) 908 # 远 技 在 浐 机 股 9 0 5 ， and this = connected, the direction of a bit is opposite to the main diode 480668

:. 1 into 0 3 direction. The plurality of second diodes (Ddi to Ddn) 9 0 9 2 are connected between the node 'point 9 0 2 and the Vss voltage supply line 9 0 6, and the direction of some of the diodes is opposite to that of the main diode D 2 The square of 9 0 = f point 9 0 2 is connected to the output terminal of the-output buffer. This output buffer is composed of a -P channel transistor 9 and an N channel transistor 9. And the input terminal of this output buffer is connected to a pre-driver 9. When an electrostatic discharge event is applied, a negative voltage relative to the VSS voltage supply line g 0 6 is applied to an output pad 9 0. ^ D2 g 0 4 is forward biased and due to Vdd voltage supply state 'main diode D1 9 0 3 has not been turned on. The static electricity 5 is discharged as: electricity; it is discharged through the main diode]) 2 9〇4 to the Vss voltage supply line 906 〇 When an electrostatic discharge event is a negative voltage relative to the Vdd voltage supply line 905 When applied on the output pad 90 丄, the main diode D1; 03 is the reverse bias. The VSS voltage supply column 906 is in a floating state. The

The plurality of first diodes (Du 1 to Dun) 9 0 8 are forward biased in this case, and the electrostatic discharge current passes through the plurality of first diodes Du 1 to Dun) 9 0 8 Emissions. When an electrostatic discharge event occurs, a positive voltage is applied to the output pad 9 0 1 with respect to the V s s voltage supply line g 0 6, and the main diode g 0 4

Du 668 5. Description of the invention (12) This is reverse bias. During this electrostatic discharge, the Vdd voltage supply column 9 Q [is floating. The plurality of second diodes (D d 1 to D d η) 9 〇 In this case, they are forward biased, so the electrostatic discharge current passes through the plurality of second diodes (D d 1 to D d η) 9 0 9 emissions. When an electrostatic discharge event occurs, a positive voltage is applied to the output pad 9 Q relative to the Vdd voltage supply line 9 Q. In this case, the Vss voltage supply line 9 0 6 is in a floating state. In this case, the main diode D1 9 0 3 is forward biased, so the electrostatic discharge current is discharged through the main diode! ^ 9 0 3. The tenth figure is another specific embodiment of an electrostatic discharge protection circuit including a silicon diode on an insulating layer of the second to seventh figures. The electrostatic discharge protection circuit includes a conductive input pad 1001, main diodes D1 1003, D2 1004, D3 1005 and D4 1 0006, an input resistance 1 0101, a N-channel transistor 1 0 1 1, a Vdd voltage for f column 1 007, a Vss voltage supply column 1 08 and an electrostatic discharge

ESD clamp circuit 1 009. The main diodes 1003 and 02 10 04 are connected in series, and the main diodes D3 1 05 and D 4 1 0 06 are connected in series. All of these two-pole systems are formed by diodes with silicon on the insulating layers in the second to seventh figures. The input pad 1 0 0 1, the wheel-in resistance 1 〇 1 〇, the Vdd voltage supply line 丄 〇 〇 07, and the Vss voltage supply line 1 ο 0 8 are the same as these insulation layers with silicon two

Page 16 V. Description of the invention (13) The pole system is formed on the same insulation layer. The input 塾 1 〇 〇 1 is directly connected to a first node i ○ ^, the spring segment) 3 and D 2 i through a lead. . 4 series connection; ^ th-r f; polar body D1 1 0 0 supply gate 1 0 0 7. The first sub-point of φ 1 〇 2 and Vdd voltage 0 0 6 are connected between the first section f &quot; ^ 5 and D4 1 ◦8. Input resistance i 〇 / 0 = and, relay line 1 0 is connected in series with input 塾 i 0 〇 '=: electric f body 1 0 1 1 series 〇1 3 series via-the first fi Λ 1 and internal circuit 1 η Τ ί The first-point 1 〇 2 2 coupling. The N-channel transistor is coupled to the Vss voltage supply column 108. π 7 .... _ ◦ 0 9 is connected between the Vdd voltage supply line 〇 〇 07 and the Vss voltage supply line 〇 〇 08. Twenty-two diodes D1 1 0 3 and D2 1 0 04 replace the main connection between the input pad 1 000 and the Vdd voltage supply column χ 0: and the other two main diodes D 3 1 0. 〇5 &amp; d4 〇 Diode D2 is connected between the input pad 001 and the Vss voltage supply ':' J 1 0 0 8. If the parasitic junction capacitance of the diode D1 is C1,: the parasitic junction capacitance of the diode D2, the parasitic junction capacitance of the diode D3, C3, and the parasitic junction capacitance of the diode D4 is C4. The eighth figure is due to M ...: The input capacitance generated is Cin = cl + C2, but in the tenth figure of this specific embodiment, the input capacitance becomes Cin, = [clC2 / (CHC2)] + 480668

[C3C4 / (C3 + C4)]. If the diodes (D1, D2, D3, D4) are all the same, that is, C1 = C2 = C3 = C4 = C, then Cin = 2c and Cin, = c. Therefore, the parasitic input capacitance of each specific embodiment is reduced by half, and its RC time constant is also reduced. By reducing this input delay, the electrostatic discharge protection circuit of this embodiment can be applied to a radio frequency circuit (RF circuit) or a high frequency circuit (HF circuit). V. Description of the invention (14) The eleventh figure is a modification of the tenth figure. The VDD to ^^ electrostatic discharge clamping circuit includes a plurality of diodes (Dpl to Dpn) 1 10 with silicon on the first insulation layer and a diode with silicon on the second insulation layer in parallel with one of them. Dx 1 1 1 0. All diodes of this ESD protection circuit use diodes with silicon on the insulation layers in Figures 2 to 7. The twelfth figure is a modified example of the tenth figure. In this electrostatic discharge protection circuit, three diodes D1 1203, D2 1204, and D3 1 2 0 5 are connected in series between the Vdd voltage supply column 1 2 0 9 and the input pad 1 201, and three diodes The bodies D4 1206, D5 1 2 0 γ, and D6 1 2 0 8 are connected in series between the Vss voltage supply column 1 2 1 0 and the input pad 1 2 0 1. All the two-pole systems of this electrostatic discharge protection circuit use the diodes on the insulation layer of the second to seventh figures. Its input capacitance becomes Cin, = [Cl .C2 .C3 / (C1 .C2 + .C2 .C3 + C1 .C3)] + [C4 .C5 .C6 &gt; / (C4 .C5 + C5 .C6 + C4 · 〇6 )] = 2/3 (:, its capacitance is further reduced.

Page 18 668 668 668 5. Description of the invention (15) The twelfth picture is a modified example of the twelfth picture. The Vdd to Vss electrostatic discharge circuit includes a plurality of diodes (Dpi to Dpn) on the first insulation layer; l 3 χ 1 and a second insulation layer in parallel with silicon two. The polar body is i 3 i 2. All of the two-pole systems of this ESD protection circuit use diodes with silicon on the insulation layers in Figures 2 to 7. According to the above, the present invention has the following advantages: 1. The present invention provides a diode with silicon on the insulating layer having a low power density, which has a larger PN junction area than a general diode. 2. The present invention provides a diode having silicon on an insulating layer having improved electrostatic discharge protection capability. 3. The present invention provides a diode that can be used on the insulating layer of mixed voltage and analog / digital circuits. 4 · This matter provides an electrostatic discharge protection circuit with reduced input capacitance, which can be used as radio frequency circuit (RF circuit) or high frequency circuit (HF Clrcuit) iI / 0 electrostatic discharge protection circuit. , = The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the patent in the present invention; &amp; others that do not depart from the present invention; Equivalent changes or modifications should be included in the following

Page 19 480668

Page 480668 Brief description of the diagram The first diagram is a cross-sectional schematic diagram of a conventional SOI polysilicon-bounded Lub is tor; the second diagram is proposed by the present invention The schematic diagram of the cross section of the diode, whose PN junction is located in the middle area below the gate; the third diagram is a schematic diagram of the cross section of another type of polycrystalline silicon diode structure proposed in the present invention, whose PN junction is located at the gate The lower middle region; the fourth figure is a polycrystalline silicon diode structure with a source / drain implantation region formed on a so! Wafer according to the present invention, and the PN junction is located in the middle region of the gate; the fifth figure is One is a diode with a gate defined by polycrystalline silicon, which is a fully-depleted) polycrystalline silicon proposed by the present invention; the sixth diagram is a schematic cross-sectional view of another body proposed by the present invention, the PN junction is located at the gate Pole; ^ $ The middle area of the gate with stacked poles Γ is shown in Figure 7. The intention of the present invention is that the pole-free junction 2 is located in the middle area; the middle area; the cross section of the pole body shows the eighth The figure and the ninth figure are based on the second Specific examples of the S0I electrostatic discharge s of the I / O I / O pins from 7 to 7 are schematic diagrams of the electric protection 4 circuit; 480668 on page 21 The diagram is briefly explained The tenth and eleventh diagrams are based on the second and third diagrams. Schematic diagram of the SOI electrostatic discharge protection circuit of the specific embodiment of figure 7; and Figures 12 and 13 are modified examples of Figures 10 and 11 respectively. Representative symbols of the main parts: 10 0 buried oxide layer 1 0 1 N well · 10 2 P + diffusion region 2 0 0 substrate 2 0 1 buried oxide layer 2 0 2 shallow trench isolation region 2 0 3 P well 2 0 4 N well 2 0 5 first heavily doped P + diffusion region 2 0 6 second heavily doped N + diffusion region 2 0 7 like M 0 S-polycrystalline gate 2 0 8 dielectric layer 2 0 9 a JL heavily doped P + diffusion region 2 0 9b fourth heavily doped N + diffusion region 2 1 0 dielectric spacer 3 0 2 shallow trench isolation region

Page 480668 Simple illustration of the 3 0 3 P well 3 0 4 N well 3 0 5 First lightly doped P-diffusion region 3 0 6 Second lightly doped N-diffusion region 3 0 7 Like M0S polycrystalline silicon gate 3 0 9 a Third lightly doped P-diffusion region 3 0 9 b Fourth lightly doped N-diffusion region 4 0 2 Shallow trench isolation region 4 0 3 P well 4 0 4 N well 4 0 5 First light Doped P-diffusion region 4 0 6 Second lightly doped N-diffusion region 4 0 7 M0S-like polycrystalline silicon gate 4 0 9 a Third lightly doped P-diffusion region 4 0 9 b Fourth lightly doped N- Diffusion zone

Page 23 4 1 0 Fifth heavily doped P + diffusion region 4 1 1 Sixth heavily doped P + diffusion region 5 0 2 shallow trench isolation region 5 0 3 P well 5 0 4 N well 5 0 5 first lightly doped Miscellaneous P + diffusion region 5 0 6 Second lightly doped N + diffusion region 5 0 7 Similar to M0S polycrystalline silicon gate 5 0 9 a Third lightly doped P + diffusion region 480668 Illustration of simple illustration 5 0 9 b 23473401234567890012345 oooooooooooooooooooooooo 66667788888888888999999 fourth light Doped N + diffusion region, shallow trench isolation region, P well, N well, M0S polycrystalline silicon gate, P well, N well, electrostatic discharge protection circuit, input pad, first node, main diode D1, main diode D2, Vdd voltage supply column, V ss voltage supply Column input resistance multiple first diodes multiple second diodes internal circuit electrostatic discharge protection circuit output pad first node main diode D1 main diode D2 Vdd voltage supply column

I

Page 24 480668 Illustration of the diagram 9 0 6 9 0 8 9 0 9 9 1 0

123456789012390234 ow IX IX IX IX IX C3 1000000000000011222 IX IX IX IX IX IX 1 ± IX 1 ± Tx IX ix 1 ± IX IX rH V ss voltage supply line multiple first diodes multiple second diodes P-channel electricity Crystal N-channel transistor pre-driver input pad first node main diode D1 main diode D2 main diode D3 main diode D 4 Vdd voltage supply column V ss voltage supply column electrostatic discharge clamping circuit input resistance N Channel transistor second node internal circuit with silicon diode on the first insulation layer Shi Di diode on the second insulation layer Main diode D1 Main diode D2 _

I

480668 on page 25 Brief description of the diagram 1 2 0 5 Major diode D3 1 2 0 6 Major diode D4 1 2 0 7 Major diode D5 1 2 0 8 Major diode D 6 1 2 0 9 V dd voltage supply column 1 2 1 0 V ss voltage supply column 1 2 1 1 electrostatic discharge clamping circuit 1 3 1 1 silicon diode on the first insulation layer 1 3 1 2 silicon diode on the second insulation layer Body Φ

Page 26

Claims (1)

Application scope 1 • An insulation layer has a substrate; an insulation layer, which is—moxibustion trench isolation—PN junction two poles, adjacent to each other has an electrical property of N-type and p :: electrical electrical opposite = Between the trench isolation regions, two first heavily doped diffusion regions are adjacent to each other—a vertex angle formed by a heterodiffusion region at the vertex angle. The broken (S 01) "-polar body" at least includes: formed on the substrate; the region 'is formed on the insulating layer; and the body is formed by one of the first wells having a first conductivity and the second conductivity One of the second wells is formed, wherein any one of the first type is conductive, the second conductivity and the first, and the first well and the second well are formed on the insulating layer of the two, one having The first conductive region is formed between the first well and the shallow trench, and one of the second conductive regions has a second conductivity that is heavier than the second well and the other. Adjacent to the fire trench isolation zone, where 2. Insulation according to item 范围 of the scope of the patent application The above-mentioned insulation layer is formed of a layer of stone dioxide with stone lining 3. · Insulation layer as in the scope of patent application 2 The previous MOS-like gate system is formed on the first well and the first pole body, wherein the gate includes a dielectric layer and a lightning conductor; above the 5_ well, the MOS-like conductive layer is formed on Above the dielectric layer, ambiguous spacers are formed, and each of them is formed on each side of the MOS-like gate. The sub-region and the second heavily doped diffusion region respectively ^ the first heavily doped diffusion side by themselves. The target is aligned with the MOS-like gate. 480668 6. Scope of patent application 4. If there is a silicon diode on the insulating layer of the third scope of the patent application, the above-mentioned M0S-like gate includes a third heavily doped diffusion region and a fourth heavily doped diffusion region. Region, the third heavily doped diffusion region and the fourth heavily doped diffusion region are short-circuited to each other, and the first heavily doped diffusion region and the second heavily doped diffusion region are respectively aligned with the first heavily doped diffusion region. The triple-doped diffusion region and the fourth heavily-doped diffusion region. 5. For example, if there is a silicon diode on the insulating layer of the third patent application range, the first heavily doped diffusion region and the second heavily doped diffusion region are formed on the insulating layer, and A shallow trench isolation region is between the shallow trench isolation region and the first well, and another shallow trench isolation region is between the shallow trench isolation region and the second well. 6. A diode with silicon on the insulating layer, which includes at least: a substrate; an insulating layer formed on the substrate; two shallow trench isolation regions formed on the insulating layer; first conductive A PN junction diode with the first conductivity is formed by a first well having a first conductivity and a second well adjacent thereto having a second conductivity, wherein the system is P Conductivity of either the N-type or N-type, the second conductivity is opposite, and the first well and the second well are formed between the two shallow trench isolation regions, and the first well is adjacent to A first lightly doped diffusion region having the first conductivity is formed at a vertex of a shallow trench isolation region, and a second well is formed adjacent to a vertex of another shallow trench isolation region. With Page 28 480668 6. The scope of the patent application is one of the second conductivity, the second lightly doped diffusion region; and a M0S-like gate formed between the first well and the M0S-like gate. The gate includes a dielectric An electric layer, a conductive layer, and a 28: well, the conductive layer is formed above the dielectric layer, and the 218 &quot; electrical spacers are formed on each side of the MOS-like gate, respectively Where the 誃 \ beam wall is one of the first conductive third lightly doped diffusion region and the second electrically conductive ^ 罾 includes a fourth lightly doped diffusion region having electrical properties, the third lightly doped diffusion region The second and fourth lightly doped diffusion regions are turned on in a short circuit, and the two political regions and the second lightly doped diffusion region are respectively aligned with the = j diffusion region and region and the fourth lightly doped diffusion region. Area. ~~ Two lightly doped diffusions7. The above-mentioned insulation layer on the insulation layer of the 6th patent scope of Shen Qing is formed by a layer of stone dioxide and a polar body of stone evening, where i is lighter and mixed with inclusions. Right access on the insulating layer of the expanded application for patent No. 6 * Including the gate with the first conductivity-the fifth diffusion body 2 in the heterodiffusion region and a gate trench isolation region = two = in β The first conductivity is the sixth heavy doping with one of the second conductivity; = = the second one on the well, the scattered region and the other shallow trench isolation region, the second light grid. Electric = / 〇: Electric discharge protection circuit, its protection-circuit, the electrostatic discharge protection circuit includes at least one of "Shi Xi's conductive pads formed on the insulating layer" &lt; ι-wire 'formed on the Insulation layer · h, the material line is directly connected to the conductor 480668 VI. This should be the first 10. 11. The electricity Λ / Γ is the patent application range of 12. The first node is the first node; the first ~ the voltage supply column, the second voltage supply column, The first to the main diode, the 苐 lang point and the _ voltage main diode, and the second voltage first node are a plurality of first diodes, and the first node is mainly connected to the first voltage diode. There are multiple second diodes in the direction, the first Lang point is opposite to the second voltage, and the second main diode is formed on the far insulation layer, formed on the insulation layer, and formed on the insulation layer ± supply column Θ is formed between the supply columns on the insulating layer; 9 is formed between the insulation; between the supply columns, the Asian Games are connected to the reverse; and the μnet two-pole system and the system are formed in the feat展 # / δ π &gt; Μ layer, and connected to the direction of the volume. The direction of the polar body is connected to and connected to and connected to the first section of the electrostatic discharge such as the scope of the patent application No. 9, the point i is connected to the product = circuit ′ where the above output buffer. For example, the ninth resistor in the scope of the patent application is formed between the upper points of the insulating layer, and the second resistor is between the second resistor and the resistor. • ... Again, it ’s more inclusive, and 1 horse is in the reward ... ^ J Qiao first Lang point and one ", 糸 is located on one of the integrated circuits. If the scope of the patent application is 9th, there is a two-pole system. '&quot; 〇 / Eight electric decoration patent range 1 to 8, among which the above must be 480668 6. The scope of the patent application has a silicon diode formed on the edge layer. 13 ·-An electrostatic discharge protection circuit, which protects A silicon integrated circuit is provided on the insulating layer, and the electrostatic discharge protection circuit includes at least: a conductive pad formed on the insulating layer; a wire formed on the insulating layer, and the wire is directly connected to the conductive pad At a first node; a first voltage supply column is formed on the insulating layer; a second voltage supply column is formed on the insulating layer; and is connected to a first main diode and is formed on Between the first node on the insulating layer and the first voltage supply column; and connected to a second main diode, formed between the first node on the insulating layer and the second voltage supply column; An electrostatic discharge clamping circuit Formed on the insulating layer, and between the first voltage supply column and the second voltage supply column; and, 'to meet a resistor, is formed on the insulating layer, and is connected to the first and a coupling to Between a second node of a part of the integrated circuit, and one of the body = channel and transistor, which are formed on the insulation layer, and a gate and a source of the channel electrical body are connected to The second voltage supply ^ 窀 said that one of the n-channel transistors is connected to the second node. ~ ',' And the ^ electrostatic discharge protection circuit described in the electrostatic discharge guarantee of item 13 of the patent application scope Including a plurality of serial two beer, the direction of the upper body of the two is opposite to that of the first main I_ version, the two main poles-the main body and the second main body-page 31, 480668 6. Application for a patent 15. The direction of the scope 15. If the electrostatic discharge protection circuit of item 13 of the patent application scope further includes a third main diode and a fourth main diode, wherein the third main diode system is formed on the insulation Layer, and connected to the first main diode and the first voltage Should be listed, and the fourth main diode system is formed on the insulating layer, and is connected between the second main diode and the second voltage supply column. An electrostatic discharge protection circuit, wherein the above-mentioned electrostatic discharge protection circuit includes a plurality of diodes connected in series, and the directions of the diodes are opposite to the directions of the first main diode and the second main diode. For example, the electrostatic discharge protection circuit of the scope of application for patent No. 15 further includes a fifth main diode and a sixth main diode, wherein the fifth main diode system is formed on the insulating layer and connected to Between the third main diode and the first voltage supply column, and the sixth main diode system is formed on the insulation layer and connected between the fourth main diode and the second voltage supply column between. ^ 18. The electrostatic discharge protection circuit according to item 17 of the scope of patent application, wherein the above-mentioned electrostatic discharge clamping circuit includes a plurality of diodes connected in series, and the directions of the diodes are opposite to the first main diode The second major diode Page 32 480668 VI. Direction of Patent Application Scope. 19. The electrostatic discharge protection circuit according to item 13 of the patent application, wherein all of the above-mentioned two-pole systems are formed by broken diodes on the insulation layer of any one of the application claims 1 to 8.