TW486512B - Method of manufacturing a substrate for electronic device by using etchant and electronic device having the substrate - Google Patents
Method of manufacturing a substrate for electronic device by using etchant and electronic device having the substrate Download PDFInfo
- Publication number
- TW486512B TW486512B TW88120996A TW88120996A TW486512B TW 486512 B TW486512 B TW 486512B TW 88120996 A TW88120996 A TW 88120996A TW 88120996 A TW88120996 A TW 88120996A TW 486512 B TW486512 B TW 486512B
- Authority
- TW
- Taiwan
- Prior art keywords
- film
- titanium
- acid
- substrate
- aluminum
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- ing And Chemical Polishing (AREA)
Abstract
Description
486512 _案號88120996_年月曰 修正_ 五、發明說明（1) 【發明領域】 本發明係關於一種餘刻劑，與使用該I虫刻劑之電子機 器用基板之製造方法，與具有以該方法製造出之基板之電 子機器者，特別是關於一種蝕刻劑，為可將積層有鋁膜或 鋁合金膜及鈦膜或鈦合金膜的配線之各膜以略相同之蝕刻 率作一體性之钱刻者。 【習知技術】 作為配線材料之铭材，因具有低阻抗之優點，故常被 使用於電子機器之基板上之電極等之配線材料上。 第1 2圖為電子機器之一例，為揭示一般的薄膜電晶體 型液晶顯示裝置之薄膜電晶體部份之概略圖。 此薄膜電晶體8 2係於基板8 3上設置閘電極8 4 ’並設置 一閘絕緣膜8 5覆蓋此閘電極8 4。於閘電極8 4之上方之閘絕 緣膜8 5上設有由非晶形矽（以下略記為a - S i )所形成之半導 體能動膜8 6，介以由包含磷等之η型不純物之非晶形矽（以 下略記為η+型a-Si )所形成之歐姆接觸層87自半導體能動 膜8 6上起遍及閘絕緣膜8 5上設有源電極8 8及漏電極8 9。 又，設有包覆前述源電極8 8、漏電極8 9與閘電極8 4等所構 成之薄膜電晶體8 2的鈍化膜9 0，於漏電極8 9上之鈍化膜9 0 上設有接觸孔9卜又，通過前述接觸孔9 1設有與漏電極8 9 電連接之由銦氧化錫（以下略記為I TO)等之透明電極層所 形成之畫素電極92。 又，第1 2圖左側之部份係揭示位於顯示範圍外之閘配 線端部之閘端子電極部9 3之斷面構造。於基板8 3上之由閘486512 _Case No. 88120996_ Modification of the month and month _ V. Description of the invention (1) [Field of the invention] The present invention relates to a method for manufacturing a substrate and an electronic device substrate using the insecticide I, and a method having The electronic machine of the substrate manufactured by this method, in particular, relates to an etchant, which is capable of integrating each film of the wiring with an aluminum film or an aluminum alloy film and a titanium film or a titanium alloy film at a substantially same etching rate. Money Carver. [Knowledge technology] As a wiring material, it has the advantage of low impedance, so it is often used for wiring materials such as electrodes on the substrate of electronic equipment. Fig. 12 is an example of an electronic device, and is a schematic view showing a thin film transistor portion of a general thin film transistor type liquid crystal display device. The thin film transistor 8 2 is provided with a gate electrode 8 4 ′ on a substrate 8 3 and a gate insulating film 8 5 is provided to cover the gate electrode 8 4. A gate insulating film 85 above the gate electrode 8 4 is provided with a semiconductor active film 86 formed of amorphous silicon (hereinafter abbreviated as a-S i), interposed by a non-pure substance containing n-type impurities such as phosphorus. An ohmic contact layer 87 formed of crystalline silicon (hereinafter abbreviated as η + type a-Si) is provided with a source electrode 8 8 and a drain electrode 89 from the semiconductor active film 86 and the gate insulating film 85. In addition, a passivation film 90 is formed to cover the thin-film transistor 8 2 composed of the source electrode 88, the drain electrode 89, and the gate electrode 84, and the passivation film 90 is provided on the drain electrode 89. The contact hole 9b is further provided with a pixel electrode 92 formed of a transparent electrode layer such as indium tin oxide (hereinafter abbreviated as I TO) electrically connected to the drain electrode 8 9 through the contact hole 91. The part on the left side of FIG. 12 shows the cross-sectional structure of the gate terminal electrode portion 93 at the end of the gate wiring outside the display range. By the gate on the substrate 8 3
486512 通閘絕緣膜8 5與 觸孔95而與下部 上部電極層9 6。 成為直接接續形 層’與形成閘配 阻抗，使用由鋁 會產生突起短路 生於鋁膜表面上 多巴緣層而與其他 。又，使ITO與 其結果將使接486512 turns on the insulating film 85 and the contact hole 95 and the lower upper electrode layer 96. Become a direct connection layer 'and form a gate impedance, using a short-circuited bump generated by aluminum, and a dopa edge layer on the surface of the aluminum film, and other layers. In addition, making ITO and its results will make
案號 88120996 五、發明說明（2) =線材料所形成之下部電極I 94上設有貫 ;化膜90之接觸孔95’又，設有通過此接 :極層94作電連接之由透明電極所形成之 又’於源配線端部設有相類似之構造。 線 如上述，例如於薄膜電晶體者，係構 成閑端子、源端子與畫素電極之透明電極 源配線及漏電極之配線用金屬。 惟，於此種電子機器i^降低配線 所形成之金屬膜作為配線用材料時，會有 現象之問題。此突起短路係指熱處理二產 之針狀突起，此突起會穿過積層於鋁上之 導電層短路而有引發絕緣不良之情形之處 鋁直接接觸時，IT〇中之氧氣會把^氧化 觸部份之電阻值昇高。Case No. 88120996 V. Description of the invention (2) = The lower electrode I 94 formed by the wire material is provided with a contact; the contact hole 95 'of the chemical film 90 is provided through this connection: the electrode layer 94 is electrically connected by transparent The electrodes are formed with a similar structure at the end of the source wiring. As described above, for example, in a thin film transistor, it is a metal for wiring a source electrode and a drain electrode of a transparent electrode that constitutes a free terminal, a source terminal, and a pixel electrode. However, there is a problem with the phenomenon that a metal film formed by wiring reduction in such an electronic device is used as a wiring material. This protrusion short circuit refers to the needle-shaped protrusion produced by heat treatment. This protrusion will pass through the conductive layer laminated on the aluminum and short-circuit, which may cause poor insulation. When the aluminum directly contacts, the oxygen in IT0 will contact the oxide. Part of the resistance increased.
為回避上述問題乃多使用於鋁膜上形成鉬膜或鉻膜等 之其他金屬膜之積層膜（以下略記為相異金屬之積層膜）。 利用此種相異金屬之積層膜形成閘電極84時，例如如第i4 圖之A所不’於在基板8 3上所形成之鋁膜8 4 a上積層鉬膜 84b所成之積層膜84c之表面以光蝕刻法形成既定圖樣之光 草97後，使用H3P〇 48 0重量％與HNO和CH3CO〇^ H2〇所形成之 钱刻劑作一體性之蝕刻即可得到上述積層膜84c。 惟，對上述相異金屬積層膜施以一體性蝕刻而形成圖 樣時，因金屬膜間之電位差之影響，於蝕刻劑中會產生電 池反應，而使下層之鋁膜較上層之鉬膜快速鍅刻，故會產 生例如第1 4圖B所示般之下層之鋁膜8 4 a之線寬為較上層之In order to avoid the above problems, a laminated film (hereinafter referred to as a laminated film of dissimilar metals) is used to form a metal film such as a molybdenum film or a chromium film on an aluminum film. When the gate electrode 84 is formed by using a laminated film of such dissimilar metals, for example, a laminated film 84c formed by laminating a molybdenum film 84b on an aluminum film 8 4 a formed on a substrate 8 3 as shown in A of FIG. I4 After forming the photograss 97 with a predetermined pattern on the surface by a photo-etching method, a monolithic etching using H3P0480 0% by weight and a money engraving agent formed of HNO and CH3CO0 ^ H2O is performed to obtain the laminated film 84c. However, when the dissimilar metal multilayer film is subjected to integrated etching to form a pattern, due to the potential difference between the metal films, a battery reaction will occur in the etchant, so that the aluminum film in the lower layer is faster than the molybdenum film in the upper layer. For example, the line width of the lower aluminum film 8 4 a as shown in FIG. 14B is higher than that of the upper layer.
$ 7頁 486512 案號 88120996 Λ_Ά 修正 五、發明說明（3) 鉬膜8 4 b之線寬為窄之基I虫現象（undercut)，有時會引起 絕緣耐壓不良等之問題。 為此，作為解決前述問題之方法，有於上述一體蝕刻 後使用過碘酸對屋簷狀之鉬膜8 4 b實行追加蝕刻而形成圖 樣之分法。 發明欲解決之課題】 惟，於習知之電子機器用基板之製造方法中，於形成 由相異金屬積層膜所形成之積層配線時，因至少須要兩次 之蝕刻工程，故生產性不佳，且製造工程亦較長，有提高 成本之問題。又，實行上述之追加蝕刻時，上層之鉬膜 8 4 b係較下層之鋁膜8 4 a稍快地蝕刻，如第1 4圖C所示般， 會有下層之鋁膜8 4 a會稍微突起之問題，而難以控制構成 積層配線之上層與下層之配線之線寬。 又，作為以相異金屬積層膜形成閘電極8 4之其他形成 方法者，有一方法為例如如第1 5圖A所示，係於基板8 3上 形成鋁膜84a後，於鋁膜84a之表面上塗布光致抗蝕劑97， 而實行光蝕刻，接著如第1 5圖B所示般實行蝕刻，而得到 具有所期之線寬之鋁膜8 4 a，接著如第1 5圖C所示以鉬膜 84b覆蓋鋁膜84a後，如第1 5圖D所示實行光蝕刻而於形成 既定圖樣之光罩9 8後，實行蝕刻而完成工作。惟，此種方 法與先前所述之習知方法相同，因至少須要兩次的蝕刻工 程，故有同樣的問題，又，所得到的積層配線構造如第15 圖E所示係以上層之鉬膜8 4 b覆蓋下層之鋁膜8 4 a之構造， 故上層的線寬必然較下層的線寬為寬，故難以控制上層與$ 7 pages 486512 Case No. 88120996 Λ_Ά Amendment V. Description of the invention (3) The line width of the molybdenum film 8 4 b is a narrow undercut, which may cause problems such as poor insulation withstand voltage. For this reason, as a method for solving the aforementioned problems, there is a division method in which pattern is formed by performing additional etching on the eaves-shaped molybdenum film 8 4 b using periodic acid after the above-mentioned integral etching. Problems to be Solved by the Invention] However, in the conventional method for manufacturing a substrate for an electronic device, when forming a multilayer wiring formed of a dissimilar metal multilayer film, at least two etching processes are required, so the productivity is not good. Moreover, the manufacturing process is also long, which has the problem of increasing costs. In addition, when the above-mentioned additional etching is performed, the upper layer of the molybdenum film 8 4 b is slightly faster than the lower layer of the aluminum film 8 4 a. As shown in FIG. 14C, there is a lower layer of the aluminum film 8 4 a. The problem of a slight protrusion makes it difficult to control the line width of the upper and lower layers of the multilayer wiring. In addition, as another method for forming the gate electrode 84 using a dissimilar metal laminated film, there is a method of forming an aluminum film 84a on the substrate 83 as shown in FIG. A photoresist 97 was coated on the surface, photo-etching was performed, and then etching was performed as shown in FIG. 15B to obtain an aluminum film 8 4 a having a desired line width, followed by FIG. 15C After the aluminum film 84a is covered with the molybdenum film 84b, as shown in FIG. 15D, photoetching is performed, and after forming a photomask 98 of a predetermined pattern, etching is performed to complete the work. However, this method is the same as the conventional method described above. Since it requires at least two etching processes, it has the same problem. In addition, the obtained multilayer wiring structure is shown in Figure 15 as shown in Figure E. The film 8 4 b covers the structure of the aluminum film 8 4 a of the lower layer, so the line width of the upper layer must be wider than the line width of the lower layer, so it is difficult to control the upper layer and the
486512 _案號88120996_年月曰 修正_ 五、發明說明（4) 下層之配線之線寬。 本發明係有鑑於上述情形所完成者，係將在低阻抗之 鋁膜或鋁合金膜上積層其他金屬膜所成之積層膜作為配線 材料使用時，以一次之蝕刻以略相同之蝕刻率蝕刻出構成 上述積層膜之各金屬膜，而提供一種I虫刻劑及使用該钱刻 劑之電子機器用基板之製造方法與具有利用前述方法製造 之基板的電子機器者。 【解決課題之方式】 本發明之發明人為提供一種蝕刻劑，為將在鋁膜或鋁 合金膜上積層其他金屬膜所成之相異金屬之積層膜作為配 線材料使用時，可用一次之餘刻極力抑低基I虫之產生，而 可用略相同之蝕刻率蝕刻出構成上述積層膜之各金屬膜， 其著眼於將構成上述相異金屬之積層膜之各金屬膜作為電 極而浸潰於電解液時之電極電位’反覆各種檢討與貫驗之 結果，發現作為形成上述積層膜之其他金屬膜者若使用與 鋁或鋁合金之電位差之差異為較小之物品時，則蝕刻率之 差別較小，具體上若使用順序形成鋁或鋁合金膜與鈦膜或 鈦合金膜之積層膜作為配線材料使用時，可減低基蝕之產 生，可實現一體性蝕刻之技術。 前述推論係依下述之貫驗取得證貫。 準備如第4圖所示般之電極電位測量裝置。此電極電 位測量裝置為包括有：充滿電解液7 5之容器7 6 ;作為一側 之電極7 7之標準氫電極（以下略記為S ΗE );作為另方電極 7 8之各種金屬試料（鋁、鉬、鈦、銅、鉻）；介以可變電阻486512 _Case No. 88120996_ Year Month Revision_ V. Description of the Invention (4) The line width of the lower wiring. The present invention is made in view of the above circumstances, and when a laminated film formed by laminating other metal films on a low-resistance aluminum film or an aluminum alloy film is used as a wiring material, it is etched with a single etching at a slightly same etching rate Each of the metal films constituting the laminated film is provided, and a method for manufacturing an insecticide and a substrate for an electronic device using the same and an electronic device having a substrate manufactured by the aforementioned method are provided. [Means for solving the problem] The inventor of the present invention provides an etchant for using a laminated film of dissimilar metals formed by laminating other metal films on an aluminum film or an aluminum alloy film as a wiring material. The production of low-level I insects is suppressed as much as possible, and the metal films constituting the laminated film can be etched with a slightly same etching rate. The focus is on using the metal films constituting the laminated film of the dissimilar metals as electrodes to be immersed in electrolysis. The electrode potential at the time of liquid was repeatedly reviewed and checked. It was found that if the other metal film forming the laminated film described above uses an article with a small difference in potential from aluminum or aluminum alloy, the difference in etching rate will be smaller. It is small. Specifically, if a laminated film of an aluminum or aluminum alloy film and a titanium film or a titanium alloy film is sequentially formed as a wiring material, the occurrence of undercut can be reduced, and the technology of integrated etching can be realized. The aforesaid inference is based on the following tests. Prepare an electrode potential measurement device as shown in Figure 4. This electrode potential measuring device includes: a container 7 6 filled with electrolyte 7 5; a standard hydrogen electrode (hereinafter abbreviated as SSE) as the electrode 7 7 on one side; and various metal samples (aluminum as the other electrode 7 8) , Molybdenum, titanium, copper, chromium); via variable resistance
486512486512
7 9接續於前述兩電極7 7及7 8之電源8 〇。使用此種電極電位 測量裝置測量兩極間77、78之電位差時，係於容器76=充 $電解液75後，於該電解液75中浸潰δΗΕ77與試料78，於 $源8 0施加電壓而使電流流通，藉此測量兩極間口與7 8之 電極電位EG。充滿於容器中之電解液75依構成試料之、金屬 之不同而相異，試料為鋁時使用硫酸，為鉬時使用工或 NaOH’為鈦時使用HC1，為銅時使用硫酸，為鉻時使用5 H C 1於在此測置電極電位e聘，係調節可變電阻使電泞 為〇，而讀#取其時之電極間之電位差。其結果如第5^戶^ 不。又’第5圖中，△ Ε為由鋁所形成之試料之電極電位與 其他金屬所形成之試料之電極電位之電位差。由第5圖所、 不之結果可知，與由鋁所形成之試料（Eq=—丨· 66V)之電極 間之電位差之差異度為較小者乃由鈦所形成之試料 α (Ε。二-1 · 6 3 V )，兩者之△ £ 二 〇 . 〇 3 ν。 生惟’使用順序積層鋁膜或鋁合金膜及鈦膜或鈦合金膜 之積層膜（以下略記為鋁與鈦之積層膜）所形成之積層配線 ^，至今尚未被實用化，又，使用其而於形成此種積層配 線時極力抑低基蝕之產生，且使構成上述積層膜之各:屬 膜為可用同一蝕刻率作一體蝕刻之蝕刻劑者亦尚未被實用 化’且將上述積層膜作一體性蝕刻之技術亦未被 = 因此上述推論尚未被證實及實用化。 …《立， 結又〔本發明之發明人經過反覆實行各種檢討及實驗之 i盥，發現以氟酸、過碘酸及硫酸構成蝕刻劑時可將構成 、’呂與欽之積層膜之各金屬膜同時蝕刻，且於蝕刻劑中浸潰 由銘所形成之電極及由鈦所形成之電極而與先前之實驗相 丄 z 丄 z 月 案號 88120996 曰 五、發明說明（6) 司測量電極間之電位差時，卷1帝、， 、 鋁與鈦之積層膜一體性蝕二，、私=是A E為較小時則將 小’特別是使用電極間之1 :之紹之側14量△ L將變 *，可在無實用上之問題：：：E, 4〇〇mV以下之蝕刻劑 情形下減低基钱。又，/為5〇0埃程度以下）之 藉由調整構成上述蝕刻劑之久^述迅極間之電位差△ Ε可 理由係依據下式⑴ 之各成伤之配合量加以變更。其 E^Eo+CRT/nFlna )· · · · (1) (式中，E為電位差，E為標準電極電位，7 9 is connected to the power supply 80 of the two electrodes 7 7 and 7 8. When using this electrode potential measuring device to measure the potential difference between 77 and 78 between the two electrodes, it is connected to the container 76 = filled with electrolyte 75, immerse δΗ 77 and sample 78 in the electrolyte 75, and apply a voltage to source 80. A current was passed to measure the electrode potential EG between the interpolar port and 78. The electrolyte 75 filled in the container varies depending on the sample and metal. The sample is sulfuric acid when it is aluminum, HC1 when it is molybdenum or HC1 when it is titanium, sulfuric acid when it is copper, and chromium when it is chromium. 5 HC 1 is used to measure the electrode potential here, which is to adjust the variable resistance to make the electric voltage 0, and read # to take the potential difference between the electrodes at that time. The result is like 5 ^ 户 ^ No. In Fig. 5, ΔE is a potential difference between an electrode potential of a sample formed of aluminum and an electrode potential of a sample formed of another metal. From the results shown in Fig. 5, it can be seen that the smaller the difference in the potential difference between the electrodes with the sample (Eq = 66V) formed from aluminum is the sample α (E. 2) formed from titanium. -1 · 6 3 V), △ £ 20.03 ν. Shengwei 'uses a laminated wiring formed by sequentially laminating an aluminum film or an aluminum alloy film and a laminated film of a titanium film or a titanium alloy film (hereinafter abbreviated as a laminated film of aluminum and titanium) ^, which has not yet been put into practical use. And in the formation of such multilayer wiring, the occurrence of base corrosion is minimized, and each of the above-mentioned multilayer films: the film is an etchant that can be etched with the same etching rate as a whole has not yet been put into practice. The technology of integral etching has not been = Therefore, the above reasoning has not been confirmed and put into practical use. ... "Li, Jieyou [The inventor of the present invention has repeatedly carried out various reviews and experiments, and found that when the etchant is composed of hydrofluoric acid, periodic acid, and sulfuric acid, the composition, The metal film is etched at the same time, and the electrode formed by Ming and the electrode formed by Titanium are immersed in the etchant, which is similar to the previous experiment. 丄 z 丄 z Month case number 88120996 fifth, description of the invention (6) Division measurement electrode When there is a potential difference between the electrodes, the volume of the layer 1 and the integral film of the aluminum and titanium layer are etched together. When the AE is smaller, it will be smaller, especially when the electrode is used. L will change to *, which can reduce the base cost without the practical problem ::: E, 400mV or less. Also, the reason is that the potential difference ΔE between the electrodes, which constitutes the etchant described above, can be adjusted by adjusting the amount of each wound in accordance with the following formula (1). Its E ^ Eo + CRT / nFlna) · · · · (1) (where E is the potential difference and E is the standard electrode potential,
為絕對溫度’ η為電子數’ F為法拉第常數數，T 離子之活動量） 為洛液相之 所不之Nernst式，因σ值係依蝕刻劑之組 而可改變，故電位差之Ε亦可改變。 、、、成比 第6圖係揭示鋁電極與鈦電極間之電位差△脉 之ί貝層膜之侧I虫量△ L之關係。在此的側蝕量△ l如第1 3圖 所示，係將於基板2a上順序積層之1 3 0 0埃之鋁膜3&與5〇〇 士矢之鈦膜4 a所成之積層膜以由氟酸與過埃酸與硫酸所形成 之#刻劑作蝕刻時，自鈦膜4側面進入而自至鈦膜4側面之 距離。第6圖之電位差△ E為〇 · 1 V時，蝕刻劑之各成份之比 率，氟酸為0· 3wt%，過碘酸為〇· 5wt%，硫酸為 0.5mol/l(2.7wt%)，而當△ E為 0.45V時，氟酸為 0 · 2 5 w t %，過碘酸為 0 . 5 w t °/〇，硫酸為 〇 · 3 m ο 1 / 1 (1 . 6 w t % )， 而當△ E為0· 65V時，氟酸為0· 5wt%，過碘酸為iwt%，硫酸 為 0.5niol/l(2.7wt%)，當△ E為 0.95V時，氟酸為 〇.3wt%， 過蛾酸為 l.Owt%，硫酸為 0.5mol/l(2.7wt%)。Is the absolute temperature, η is the number of electrons, F is the number of Faraday constants, and the activity of T ions is the Nernst formula of the liquid phase, because σ value can be changed according to the group of etchant, so the potential difference E is also Changeable. Figure 6 shows the relationship between the potential difference △ between the aluminum electrode and the titanium electrode △ pulse and the amount of worms △ L on the side of the shell membrane. The side etching amount Δ l here is shown in FIG. 13, which is a laminated layer formed by sequentially laminating an aluminum film 3 & and a titanium film 4 a of 500 Shiya on the substrate 2a. When the film is etched with a #etcher formed of hydrofluoric acid, peracid acid, and sulfuric acid, the distance from the side of the titanium film 4 to the side of the titanium film 4 is entered. When the potential difference ΔE in FIG. 6 is 0.1 V, the ratio of each component of the etchant, the hydrofluoric acid is 0.3 wt%, the periodic acid is 0.5 wt%, and the sulfuric acid is 0.5 mol / l (2.7 wt%). , And when ΔE is 0.45V, hydrofluoric acid is 0.25 wt%, periodic acid is 0.5 wt ° / 〇, sulfuric acid is 0.3 m ο 1/1 (1.6 wt%), And when △ E is 0.65V, hydrofluoric acid is 0.5wt%, periodic acid is iwt%, sulfuric acid is 0.5niol / l (2.7wt%), when ΔE is 0.95V, hydrofluoric acid is 0. 3 wt%, permoic acid was 1.0 wt%, and sulfuric acid was 0.5 mol / l (2.7 wt%).
第11頁 486512 _案號88120996_年月曰 修正_ 五、發明說明（7) 又，本發明之發明人發現以氟酸、過碘酸及硫酸構成 蝕刻劑時，藉由將此等各成份之配合量規定於以下之特定 之範圍内，可得到鋁電極與鈦電極間之電位差△ E為4 0 0 m V 以下之物品，而得到結決上述問題之結論。 為解決上述課題，本發明之蝕刻劑其特徵為具有氟 酸、過碘酸及硫酸，而上述氟酸與過碘酸之重量比率為0. 0 5至30wt%，且上述硫酸之重量比率為0.0 5至2 0 w t %，相對 於上述氟酸之過碘酸之重量比為0.01至2，為由可將積層 鋁膜或鋁合金膜及鈦膜或鈦合金膜所成之配線之各膜以略 相同之蝕刻率作一體性勉刻的材料所形成者。 當上述氟酸與過碘酸之合計之重量比率為未滿 0. 0 5wt%時，蝕刻率將變得過緩，而超過30wt%時則刻率將 變得過快，而變得難以控制。 當上述之硫酸之重量比率為未滿0 . 0 5 w t %時，上述電 位差△ E將超過4 0 0 mV，於將鋁膜或鋁合金膜及鈦膜或鈦合 金膜之積層膜作一體性蝕刻時，將會產生較大的基蝕，而 有時會產生絕緣耐壓不良，當產生絕緣耐壓不良時，即使 添加超過2 0 w t %其效果亦不會增大，氟酸與過碘酸之比率 將變少，蝕刻狀況之面内分布將變劣。 相對於上述氟酸之過碘酸之重量比為未滿0. 0 1時，上 述電位差△ E將超過4 0 0mV，而重量比超過2時其電位差△ E 將超過4 0 0 mV，於將上述積層膜作一體性蝕刻時會產生甚 大的基蝕現象，有時會導致絕緣耐壓不良。 本發明之蝕刻劑因係由氟酸、過碘酸及硫酸所構成， 可將順序形成鋁膜或鋁合金膜及鈦膜或鈦合金膜之積層Page 11 486512 _Case No. 88120996_ Revised Year of the Month _ V. Explanation of the Invention (7) When the inventor of the present invention found that the etchant is composed of hydrofluoric acid, periodic acid, and sulfuric acid, these ingredients are used When the compounding amount is specified in the following specific range, articles with a potential difference ΔE between the aluminum electrode and the titanium electrode of 400 m V or less can be obtained, and a conclusion that the above problems are resolved is obtained. In order to solve the above problems, the etchant of the present invention is characterized by having fluoric acid, periodic acid and sulfuric acid, and the weight ratio of the above-mentioned fluoric acid to periodic acid is 0.05 to 30 wt%, and the weight ratio of the above sulfuric acid is 0.0 5 to 20 wt%, the weight ratio of periodic acid to the above-mentioned fluoric acid is 0.01 to 2, each film is a wiring film made of laminated aluminum film or aluminum alloy film and titanium film or titanium alloy film It is formed of a material that is integrally etched with a slightly same etching rate. When the total weight ratio of the above-mentioned fluoric acid and periodic acid is less than 0.05 wt%, the etching rate will become too slow, and when it exceeds 30 wt%, the etch rate will become too fast and become difficult to control. . When the above-mentioned weight ratio of sulfuric acid is less than 0.05 wt%, the above-mentioned potential difference ΔE will exceed 400 mV, and the aluminum film or the aluminum alloy film and the titanium film or the titanium alloy film are integrated as a single film. During the etching, a large base erosion will occur, and sometimes the insulation withstand voltage failure will occur. When the insulation withstand voltage failure occurs, the effect will not increase even if it exceeds 20 wt%. Fluoric acid and periodine The ratio of the acid will be reduced, and the in-plane distribution of the etching condition will be deteriorated. When the weight ratio of periodic acid relative to the above-mentioned fluoric acid is less than 0.01, the potential difference ΔE will exceed 400 mV, and when the weight ratio exceeds 2, the potential difference ΔE will exceed 4 0 mV. When the above-mentioned laminated film is integrally etched, a large under-etching phenomenon may occur, which sometimes leads to poor insulation withstand voltage. Since the etchant of the present invention is composed of hydrofluoric acid, periodic acid, and sulfuric acid, an aluminum film or an aluminum alloy film and a titanium film or a titanium alloy film can be sequentially formed.
第12頁 486512 _案號88120996_年月曰 修正_ 五、發明說明（8) 膜，或順序形成鈦膜或鈦合金膜、鋁膜或鋁合金膜及鈦膜 或鈦合金膜之積層膜之構成之各金屬膜同時加以蝕刻。 又，依本發明之餘刻劑，藉由調整成使上述氟酸與過 碘酸之合計之重量比率為0.05〜30wt %之範圍内，且使上述 硫酸之重量比率為0. 05〜20wt%之範圍内，且使相對於上述 氣酸之過換酸之重量比為0.01〜2之範圍内，可將在低阻抗 之鋁膜或鋁合金膜上積層其他金屬膜之鈦膜或鈦合金膜所 成之積層膜之構成之各金屬膜以一次钱刻及略相同之#刻 率作钱刻。 又，本發明為解決前述課題乃提供一種電子機器用基 板之製造方法，為於至少表面為絕緣性之基板上順序形成 鋁膜或鋁合金膜及鈦膜或鈦合金膜所成之積層膜（以下略 記為鋁與鈦之積層膜）之表面形成既定圖樣之罩體，而使 用本發明之蝕刻劑蝕刻上述積層膜，而形成上述既定圖樣 之積層配線者，為其特徵者。 又，本發明為解決前述課題乃提供一種電子機器用基 板之製造方法，為於至少表面為絕緣性之基板上順序形成 鈦膜或鈦合金膜、鋁膜或鋁合金膜及鈦膜或鈦合金膜所成 之積層膜（以下略記為鈦與鋁與鈦之積層膜）之表面形成既 定圖樣之罩體，而使用本發明之蝕刻劑蝕刻上述積層膜， 而形成上述既定圖樣之積層配線者，為其特徵者。 依本發明之電子機器用基板之製造方法，藉由使用上 述構成之本發明之餘刻劑钱刻上述積層膜，即可將構成上 述積層膜之各金屬膜以一次之蝕刻工程及略相同之蝕刻率 作蝕刻，其生產效率甚高且可縮短製造工程。又，因係將Page 12 486512 _Case No. 88120996_ Year and Month Amendment _ V. Description of the invention (8) Film, or laminated film of titanium film or titanium alloy film, aluminum film or aluminum alloy film, and titanium film or titanium alloy film Each of the constituent metal films is etched simultaneously. 05〜20wt% Moreover, according to the remaining agent of the present invention, by adjusting so that the total weight ratio of the above-mentioned fluoric acid and periodic acid is in the range of 0.05 ~ 30wt%, and the weight ratio of the above sulfuric acid is 0.05 ~ 20wt% Within the range, and the weight ratio of the acid exchange to the gas acid is in the range of 0.01 ~ 2, a titanium film or a titanium alloy film of other metal films can be laminated on a low-resistance aluminum film or an aluminum alloy film. Each metal film composed of the formed laminated film is engraved with money at one time and a substantially equal # engraving rate. In order to solve the foregoing problem, the present invention is to provide a method for manufacturing a substrate for an electronic device, which is a laminated film formed by sequentially forming an aluminum film, an aluminum alloy film, and a titanium film or a titanium alloy film on a substrate with at least an insulating surface ( Hereinafter, it will be described as a layered film of aluminum and titanium). A cover body having a predetermined pattern is formed on the surface, and the above-mentioned layered film is etched by using the etchant of the present invention to form the above-mentioned layered wiring pattern. In order to solve the foregoing problem, the present invention provides a method for manufacturing a substrate for an electronic device, in which a titanium film or a titanium alloy film, an aluminum film or an aluminum alloy film, and a titanium film or a titanium alloy are sequentially formed on a substrate having at least an insulating surface. The surface of the laminated film formed by the film (hereinafter abbreviated as a laminated film of titanium and aluminum and titanium) forms a cover with a predetermined pattern, and the above-mentioned laminated film is etched with the etchant of the present invention to form the above-mentioned laminated wiring of the predetermined pattern. Is its character. According to the method for manufacturing a substrate for an electronic device of the present invention, by using the above-mentioned composition of the present invention to engrav the laminated film, the metal films constituting the laminated film can be etched in a single process and the same The etching rate is used for etching, and the production efficiency is very high and the manufacturing process can be shortened. Also, because
486512 _案號88120996_年月曰 修正_ 五、發明說明（9) 構成上述積層膜之各金屬膜以略相同之蝕刻率蝕刻，故可 容易地控制構成積層配線之上層與下層之配線之線寬。 又，因使用於鋁膜或鋁合金膜上積層鈦膜或鈦合金膜 之積層膜，於鋁膜或鋁合金膜表面形成阻擋層，於其後之 熱處理等可抑制鋁膜或鋁合金膜表面之突起之成長，故可 防止突起所造成之短路及絕緣不良。又，鈦膜或鈦合金膜 與I T 0之接觸阻抗因較鋁膜或鋁合金膜與I T 0之接觸阻抗為 低，故藉由於鋁膜或鋁合金膜之表面形成鈦膜或鈦合金膜 即可降低接觸阻抗。 因此，依本發明之電子機器用基板之製造方法乃可得 到電子特性良好且可提高產生而能降低成本之電子機器用 基板者。 又，本發明為解決前述課題，乃提供一種具有以上述 請求項第2項或第3項所述之製造方法所製造出之基板的電 子機器者。 依本發明之電子機器，因設有具有作為低阻抗配線之 鋁膜或鋁合金膜的積層用配線，而使用設有該配線之電子 機器用基板，故配線阻抗所引起之訊號電壓降低及配線延 遲等現象不易產生，而可容易地實現配線較長之大面積之 顯示及配線為較細之高密度之顯示之最佳的顯示裝置者。 【較佳實施例之發明詳述】 以下根據圖示詳細說明本發明，但本發明並不只限定 於此等實施型態例。 第3圖為將本發明之電子機器用基板之製造方法適用486512 _Case No. 88120996_ Modification of the month of the year _5. Description of the invention (9) Each metal film constituting the above-mentioned laminated film is etched at the same etching rate, so it is easy to control the wires that constitute the upper and lower layers of the laminated wiring width. In addition, because a titanium film or a titanium alloy film is laminated on an aluminum film or an aluminum alloy film, a barrier layer is formed on the surface of the aluminum film or aluminum alloy film, and subsequent heat treatment can suppress the surface of the aluminum film or aluminum alloy film. The growth of the protrusions can prevent short circuits and poor insulation caused by the protrusions. In addition, the contact resistance between the titanium film or titanium alloy film and IT 0 is lower than the contact resistance between the aluminum film or aluminum alloy film and IT 0. Therefore, since a titanium film or a titanium alloy film is formed on the surface of the aluminum film or aluminum alloy film, Reduces contact resistance. Therefore, according to the method for manufacturing a substrate for an electronic device according to the present invention, it is possible to obtain a substrate for an electronic device that has good electronic characteristics, can increase production, and can reduce costs. In order to solve the foregoing problem, the present invention is to provide an electronic device having a substrate manufactured by the manufacturing method according to the second or third aspect of the aforementioned claim. According to the electronic device of the present invention, since a laminated wiring having an aluminum film or an aluminum alloy film as a low-impedance wiring is provided, and a substrate for an electronic device provided with the wiring is used, a signal voltage drop due to wiring impedance and wiring are caused. Delays and other phenomena are not easy to produce, and it is easy to realize a large-area display with long wiring and an optimal display device with fine wiring and high-density display. [Detailed description of the invention of the preferred embodiment] The present invention will be described in detail below with reference to the drawings, but the present invention is not limited to these implementation examples. FIG. 3 is a diagram showing a method for manufacturing a substrate for an electronic device according to the present invention.
第14頁 486512 案號 88120996 五 於 而 、發明說明（10) — 液晶顯示裝置上所具備之薄膜電晶體基板之製造方法中 ‘ ie出薄膜電晶體之實施型態例之部份斷面圖。 符號a之部份為薄膜電晶體（TFT)部，b之部份為位於 TFT矩陣外側之源配線之端子部，c之部份為閘配線之姊； 部、。又，此等三個部份在具有此薄膜電晶體基板1之徐而降 之液晶顯示裝置上為位於相早后^、土老 ·^十Η “ 貝示 - ^ @ 土 、相距^ ^處，本來是無法同時捃 不㈣面圖ί，但為圖示上之方便乃相接近作圖示。揭 百^ s兄明有關薄膜電晶體部a之部份。 於薄膜電晶體部a上，於基板2上設有由膜厚 2 0 0 0埃左右之鋁膜或鋁合金 0至 鈦膜或鈦合金膜4之積芦配岣略/、、子 0 0 0埃左右之 工肤^你智配線所形成之閘電 有閘絕緣膜γ，於此閘絕緣 ；/、上設 形成之半導體膜8,於此半=上二=晶+性石夕（"〇所 於其上復設有源電極i 2及二' 上；型a—s 1層9， 係由膜厚5 0 〇至1 〇 〇 〇埃左右:° + 源电極1 2與漏電極丄5 13005 ?nnn^ ^ 、 之銳膜或鈦合金膜10，盥膜戶 至2 0 0 0%左右之鋁膜或 ”膜厗 左右之鈦膜或钦人=5金版n，與臈厚5㈣至 又，於、、语η 膜10之積層配線所形成。 ;源％極1 2與漏電極^ ^ 化膜1 7(絕緣膜），於此鈍化 上方形成有復盍其之鈍 鋁合金膜1 1上側之鈦膜或父上形成有通達設於鋁膜或 接觸孔18之内壁面及底= = =10之接觸孔18。又，沿 19。通過此接觸孔u f成為畫素電極之ITO層 電連接。 $極15與ITO層19(畫素電極）被 其次，關於源配線之端 由鈦膜或鈦合金膜1〇及鋁：b，係於閘絕緣膜7上形成 ——___或鋁合金膜11與鈦膜及鈦合金Page 14 486512 Case No. 88120996 Five and, Description of Invention (10) — In the method for manufacturing a thin film transistor substrate provided on a liquid crystal display device, ‘ie, a partial cross-sectional view of an implementation example of a thin film transistor. The part a is the thin film transistor (TFT) part, the part b is the terminal part of the source wiring located outside the TFT matrix, and the part c is the sister of the gate wiring; In addition, these three parts are located on a liquid crystal display device having the thin film transistor substrate 1 and are located at the beginning of the day ^, Tu Lao · ^ Η Η "贝 示-^ @ 土 、 相 相 ^ ^ Originally, it was not possible to view the surface diagram at the same time, but for the convenience of illustration, it is similar to the illustration. Reveal the part of the thin film transistor part a. On the thin film transistor part a, The substrate 2 is provided with an aluminum film or an aluminum alloy 0 with a film thickness of about 2000 angstroms and a titanium film or titanium alloy film 4 with a thickness of about 200,000, and a working skin of about 0.001 angstrom. The gate electrode formed by the intelligent wiring has a gate insulating film γ, which is insulated at this gate; /, a semiconductor film 8 formed thereon, here half = upper two = crystal + nature stone eve (" 〇 on the reset On the active electrode i 2 and the second electrode; the type a-s 1 layer 9 is formed by a film thickness of about 500 to 100 angstroms: ° + source electrode 12 and drain electrode 丄 5 13005? Nnn ^ ^ The sharp film or titanium alloy film 10, the aluminum film to about 20000% of the aluminum film or the "film" or about the titanium film or Chinren = 5 gold plate n, and the thickness of 5 ㈣ to, The word η is formed by the build-up wiring of the film 10.; Source% electrode 1 2 And the drain electrode ^ ^ Transform film 17 (insulating film), on which passivation is formed a blunt aluminum alloy film 1 1 on the upper side of the titanium film or the parent is formed on the aluminum film or the contact hole 18 on the inner wall surface The bottom === 10 of the contact hole 18. Also, along 19. The contact hole uf is electrically connected to the ITO layer of the pixel electrode. The $ pole 15 and the ITO layer 19 (pixel electrode) are followed by the source wiring. The end is made of titanium film or titanium alloy film 10 and aluminum: b, which is formed on the gate insulating film 7-___ or aluminum alloy film 11 and titanium film and titanium alloy
486512 修正 曰 案號88120⑽fi 五、發明說明（11) 膜 0所形成之電極層1 6a，於其上形成有鈍化膜丨7，並形 成有通達設於鋁膜或鋁合金膜丨丨上側之鈦膜或鈦合金膜i 〇 ，，觸孔2 0。又’沿接觸孔2 〇之内壁面及底面形成有由 昆：構成之上部電極層2卜通過此接觸孔20，下部電極 曰1 6 a與上部電極層2丨係被電連接。 其=丄關於閘配線之端子部。，係於基板2上形成由紹 膜或I呂合金膜3盘姑胺々、从入人+ 部電極層16b，；：：:戈=膜4之積層配線所構成之下 化膜…並形成有、、Λ成有Λ絕緣膜7,其上復形成有鈍 % 有通達鈦膜或鈦合金膜4之接觸孔2 2。 之上i電孔、:2之内壁面及底面形成有由1 τ〇所構成 部電極層23係被電;^此接觸孔22’下部電極層16峨上 接之敍1το層與銘層係介以由可與1τ〇作電連 直接接觸所形成f膜或欽合金膜被接續，故不會發生由 上述鈍化膜之=抗值之上昇之情形。 a-二氧化石夕·Η、1例，可舉出a(非晶性）H:H、a-Mx、 其次，根據第？二化;夕等。 基板1之製造工程，弟2圖說明本實施型態之薄膜電晶體 電晶體（TFT)部，h第1圖及第2圖中，符號a之部份為薄膜 端子部’ c之部份之部份為位於TFT矩陣外側之源配線之 首先，如第：：配線之端子部。 序成膜出紹膜或銘人：示，於基板2全體上使用噴濺法順 膜。 σ里膜3與鈦膜或鈦合金膜4而形成積層 486512 _案號88120996_年月日__ 五、發明說明（12) 以光蝕刻法形成既定之圖樣之光罩2 7，其後使用由氟酸、 過碘酸及硫酸所形成之蝕刻劑，於上述積層膜上實施一體 性之儀刻，而形成如第1圖B所示般之由銘膜或铭合金膜3 及鈦膜或欽合金膜4之積層配線所形成之閘電極5。在此所 使用之餘刻劑其上述敦酸與過埃酸之合計之重量比率為在 0. 0 5至3 0wt%之範圍内，且上述硫酸之重量比率為在0. 05 至2 0 w t %之範圍内，而上述過織酸之相對於上述氟酸之重 量比為調整至0 . 0 1至2之範圍内。486512 Amended case number 88120⑽fi V. Description of the invention (11) The electrode layer 16a formed by the film 0 is formed with a passivation film 7 and formed with a titanium layer provided on the upper side of the aluminum film or aluminum alloy. Film or titanium alloy film i 0, contact hole 20. In addition, a core is formed along the inner wall surface and the bottom surface of the contact hole 20: the upper electrode layer 2 is formed through the contact hole 20, and the lower electrode 16a and the upper electrode layer 2 are electrically connected. This is the terminal part of the gate wiring. , Is formed on the substrate 2 to form an underlayer film composed of a laminated film of a Shao film or an Ill alloy film, and a three-layer electrode layer 16b from the entrance + the external electrode layer; Yes, and Λ are formed with Λ insulating film 7, and there are formed contact holes 22 having a passivation of titanium film or titanium alloy film 4 thereon. The upper hole i, the inner wall surface and the bottom surface of the 2 are formed with an electrode layer 23 composed of 1 τ〇; ^ This contact hole 22 ′ is connected to the lower electrode layer 16 Å, and the 1 το layer and the layer are connected. The f film or chin alloy film formed by being in direct contact with 1τ〇 is electrically connected, so the situation where the above-mentioned passivation film = resistance value does not increase will occur. a-stone dioxide x yttrium, an example, a (amorphous) H: H, a-Mx, and second, according to the? Secondization; Xi et al. In the manufacturing process of the substrate 1, the figure 2 illustrates the thin film transistor (TFT) section of this embodiment. In the first and second figures, the part of the symbol a is the part of the thin film terminal part 'c. Part is the first of the source wiring located outside the TFT matrix, such as the first: the terminal portion of the wiring. In order to produce a film or inscribe the film, it is shown that the film is sprayed on the entire substrate 2 using a sputtering method. The σ film 3 and the titanium film or titanium alloy film 4 form a laminated layer 486512 _Case No. 88120996_year month__ V. Description of the invention (12) A photomask 2 7 of a predetermined pattern is formed by a photoetching method, and thereafter used The etchant formed by hydrofluoric acid, periodic acid, and sulfuric acid is integrally engraved on the laminated film to form an ingot film or an ingot alloy film 3 and a titanium film as shown in FIG. 1B. The gate electrode 5 formed by the laminated wiring of the Cin alloy film 4. 05 至 2 0 wt The weight ratio of the total amount of the above-mentioned tunic acid and peracetic acid used in the remaining agent used herein is in the range of 0.05 to 30 wt%, and the weight ratio of the above sulfuric acid is 0.05 to 2 0 wt Within the range of%, and the weight ratio of the above-mentioned weaving acid to the above-mentioned fluoric acid is adjusted to the range of 0.01 to 2.
一方面，閘配線之端子部c者，係於鈦膜或鈦合金膜4 上以光蝕刻法形成既定圖樣之光罩2 8後，使用與前述者相 同之姓刻劑對上述積層膜實施一體性餘刻，而形成如第1 圖B所示之由鋁膜或鋁合金膜3與鈦膜或鈦合金膜4之積層 配線所形成之下部電極層1 6 b。 藉由上述方式之施作，可將構成上述積層膜之鋁膜或 鋁合金膜3與鈦膜或鈦合金膜4同時以略相同之蝕刻率作蝕 刻，可得到上層與下層之配線之線寬為略相等之積層配線 所構成之閘電極5與下部電極層1 6 b，可防止由基蝕所導致 之絕緣耐壓不良等情形之發生。On the one hand, the terminal part c of the gate wiring is formed on the titanium film or titanium alloy film 4 by photolithography to form a photomask 28 of a predetermined pattern, and then the above-mentioned laminated film is integrated with the same name as the former. As shown in FIG. 1B, the lower electrode layer 16 b is formed by the laminated wiring of the aluminum film or aluminum alloy film 3 and the titanium film or titanium alloy film 4 as shown in FIG. 1B. By the above method, the aluminum film or aluminum alloy film 3 and the titanium film or titanium alloy film 4 constituting the laminated film can be etched at the same etching rate at the same time, and the line width of the upper and lower wiring can be obtained. The gate electrode 5 and the lower electrode layer 16 b, which are formed by slightly equal laminated wirings, can prevent the occurrence of poor insulation withstand voltage caused by the base corrosion.
接著於基板2之上表面全體上使用CVD法形成閘絕緣膜 7。接著，關於薄膜電晶體部a者，則於形成半導體膜8、 n+型a-Si層9後，如第1圖C所示般，蝕刻半導體膜8與n+型 a-Si層9使保留成為TFT之通道部之閘電極5之上方部份。 又，薄膜電晶體部a及源配線之端子部b者，如第1圖D 所示般，係順續成膜出鈦膜或鈦合金膜1 0與鋁膜或鋁合金 膜1 1及鈦膜或鈦合金膜1 0而形成積層膜。Next, a gate insulating film 7 is formed on the entire upper surface of the substrate 2 by a CVD method. Next, for the thin film transistor portion a, after the semiconductor film 8 and the n + -type a-Si layer 9 are formed, as shown in FIG. 1C, the semiconductor film 8 and the n + -type a-Si layer 9 are etched so that they remain. Above the gate electrode 5 of the channel portion of the TFT. In addition, as shown in FIG. 1D, the thin film transistor portion a and the terminal portion b of the source wiring are successively formed into a titanium film or a titanium alloy film 10 and an aluminum film or an aluminum alloy film 11 and titanium. Film or titanium alloy film 10 to form a laminated film.
第17頁 486512 _案號88120996_年月曰 修正_ 五、發明說明（13) 其次，薄膜電晶體部a者，係於成為TFT之通道部之閘 電極5之上方之鈦膜或鈦合金膜1 0上以光蝕刻法形成既定 圖樣的光罩3 7後，使用與前述者相同之蝕刻劑於上述積層 膜上實施一體性蝕刻，而形成如第2圖A所示般之由鈦膜或 鈦合金膜1 0及鋁膜或鋁合金膜1 1及鈦膜或鈦合金膜1 0之積 層配線所形成之源電極1 2與漏電極1 4。 一方面，源配線之端子部b者，係於鈦膜或鈦合金膜 1 0上以光蝕刻法形成既定圖樣之光罩3 8後，使用與前述者 相同之蝕刻劑對上述積層膜實施一體性蝕刻，而形成如第 2圖A所示之由鈦膜或鈦合金膜1 0與鋁膜或鋁合金膜1 1與鈦 膜或鈦合金膜1 0之積層配線所形成之下部電極層1 6 a。 藉由上述方式之施作，可將構成上述積層膜之鈦膜或 鈦合金膜1 0與鋁膜或鋁合金膜1 1與鈦膜或鈦合金膜1 0同時 以略相同之蝕刻率作蝕刻，可得到上層與下層之配線之線 寬為略相等之積層配線所構成之源電極1 2、漏電極1 4與下 部電極層1 6 a，可防止由基蝕所導致之絕緣耐壓不良等情 形之發生。 其後使用乾式法或併用乾式法及濕式法將n+型a-Si層 I虫刻而形成通道2 4。 其次，薄膜電晶體部a與源配線之端子部b及閘配線之 端子物c者，係於鈦膜或鈦合金膜4、1 0上形成純化膜1 7。 接著，薄膜電晶體部a者，如第2圖B所示，係以乾式 法或併用乾式法及濕式法蝕刻鈍化膜1 7而於形成接觸孔1 8 後，於全面上形成I TO層，其後藉由實行圖樣化工程，如 第3圖所示般，於接觸孔1 8之底面及内壁面乃至鈍化膜1 7Page 17 486512 _Case No. 88120996_ Rev. _ V. Explanation of the invention (13) Second, the thin film transistor a is a titanium film or a titanium alloy film above the gate electrode 5 which becomes the channel portion of the TFT. After forming a photomask with a predetermined pattern on the photo-etching method on 10, 37, using the same etchant as described above, an integrated etching is performed on the laminated film to form a titanium film or a film as shown in FIG. 2A. The source electrode 12 and the drain electrode 14 formed by the laminated wiring of the titanium alloy film 10 and the aluminum film or aluminum alloy film 11 and the titanium film or titanium alloy film 10. On the one hand, the terminal part b of the source wiring is formed on the titanium film or titanium alloy film 10 by photolithography to form a photomask 38 of a predetermined pattern, and then the same laminated film is integrated with the same etchant as described above. The lower electrode layer 1 is formed by laminating wirings of a titanium film or a titanium alloy film 10 and an aluminum film or an aluminum alloy film 11 and a titanium film or a titanium alloy film 10 as shown in FIG. 2A. 6 a. By the application of the above method, the titanium film or titanium alloy film 10 and the aluminum film or aluminum alloy film 11 and the titanium film or titanium alloy film 10 constituting the laminated film can be etched at the same etching rate at the same time. The source electrode 1 2, the drain electrode 14, and the lower electrode layer 16a, which are formed by laminated wirings with slightly equal line widths of the upper and lower wirings, can be obtained, which can prevent poor insulation withstand voltage caused by base corrosion, etc. The situation happened. Thereafter, the n + -type a-Si layer I is etched using a dry method or a combination of a dry method and a wet method to form channels 24. Next, the thin film transistor portion a, the terminal portion b of the source wiring, and the terminal object c of the gate wiring are formed on the titanium film or titanium alloy film 4, 10 to form a purified film 17. Next, as shown in FIG. 2B, the thin-film transistor portion a etches the passivation film 17 by a dry method or a combination of a dry method and a wet method to form a contact hole 18 and then forms an I TO layer on the entire surface. Then, by implementing a patterning project, as shown in FIG. 3, on the bottom surface and the inner wall surface of the contact hole 18 and even the passivation film 17
第18頁 486512 案號88120996_年月日 修正_ 五、發明説明（14) 之上表面形成IT 0層1 9。 一方面’源配線之端子部b與閘配線之端子部c者，係 同樣地，以乾式法或併用乾式法及濕式法蝕刻鈍化膜1 7而 於形成接觸孔2 0、2 2後（惟，閘配線端子部c除鈍化膜1 7外 亦蝕刻閘絕緣膜7而形成接觸孔2 2 )，於全面上形成I TO 層，其後藉由實行圖樣化工程，如第3圖所示般，於接觸 孔20、2 2之底面及内壁面乃至鈍化膜ι7之上表面形成上部 電極層21、23。 依照此種順序可製造出薄膜電晶體基板。 a本實施型態例之薄膜電晶體基板之製造方法者，係以 二^蝕刻工釭將構成上述積層膜之各金屬膜同時以略相 二愈率作姓刻’故除可容易地控制構成積層配線之上 二、下層之配線之線寬外’丨生產性良好，可縮短製造工 之積層膜：：於鋁膜或鋁合金膜上積層鈦膜或鈦合金膜 成，可抑制】ί為於紹膜f1呂合金膜表面具有阻擋層之構 之突起之成^彳之熱處理等所造成之鋁膜或鋁合金膜表面 又，形点〜可防止因犬起所造成之短路或絕緣不良。 I τ 0層接嘖^鋁膜或鋁σ金膜上的鈦膜或鈦合金膜係與 因此 ^ 、止山 ’ M本實施型態例之帝曰M a … 二^二薄膜電晶體基板丨其電二二^:’^製造方法所製 性而有可減低成本之優點。子4寸性甚良好，可提高生產 又Page 18 486512 Case No. 88120996_Year Month Day Amend_ V. Description of the invention (14) IT 0 layer 19 is formed on the upper surface. On the one hand, the terminal portion b of the source wiring and the terminal portion c of the gate wiring are similarly etched by the dry method or a combination of the dry method and the wet method 17 to form the contact holes 20 and 22 ( However, in addition to the passivation film 17, the gate wiring terminal portion c also etches the gate insulating film 7 to form a contact hole 2 2), and an I TO layer is formed on the entire surface. Thereafter, a patterning process is performed as shown in FIG. 3. Generally, the upper electrode layers 21 and 23 are formed on the bottom surface and the inner wall surface of the contact holes 20 and 22 and even on the upper surface of the passivation film ι7. In this order, a thin-film transistor substrate can be manufactured. aThe manufacturing method of the thin film transistor substrate of this embodiment is to use two etchers to engrav each metal film constituting the above-mentioned laminated film at the same time with a slight phase recovery rate, so the composition can be easily controlled. Laminated wiring above and below the wiring width of the second and lower wiring is good. Productivity can shorten the manufacturing process. Laminated film :: Laminated titanium film or titanium alloy film on aluminum film or aluminum alloy film can be suppressed. The surface of the aluminum film or aluminum alloy film caused by the heat treatment of the protrusions of the barrier layer structure on the surface of the Shao film f1 Lu alloy film, etc., can also prevent the short circuit or poor insulation caused by dogs. The I τ 0 layer is connected to a titanium film or a titanium alloy film on an aluminum film or an aluminum σ gold film, and therefore, ^, Zhishan 'M, the emperor of this embodiment, M a ... two ^ two thin-film transistor substrates 丨Its electric manufacturing method has the advantages of low cost and low manufacturing cost. The 4-inch nature is very good, which can improve production.
’本發明之技術範圍廿τ 口服—认 —亚不/、限疋於上述實施型態， 486512 銮號 88120996’The technical scope of the present invention 廿 τ oral-recognized-Yabu /, limited to the above-mentioned embodiment, 486512 銮 88120996
五、發明說明（15) 關於例如铭膜或銘合金膜、鈦膜或鈦合 膜尸及來#笠，口 I力：τ π姑丄々 孟~及#化膜等之 艇厚及形狀寺，，、要在不脫離本發明精神* 種變更。 伸之耗圍内可作各 又，於上述實施型態中，係說明一 版蚀刻|呂膜式叙人 金膜3與鈦膜或鈦合金膜4之積層膜而形成、:—口 7力乂下部電極層1 β h 之情形，但一體蝕刻鈦膜或鈦合金膜盥叙 工狀一站腠或鋁合金膜盥 鈦膜或鈦合金膜之積層膜而形成者亦可。π ^ 又，係說明一， 蝕刻鈦膜或鈦合金膜1 0與鋁膜或鋁合金膜丨丨與欽膜/敛: 金膜1 0之積層膜而形成源電極2、漏電極丨4與'下部^/1 極 ^層& 16a之情形，但一體蝕刻鋁膜或鋁合金膜輿鈦膜丄=合^ 膜之積層膜而形成者亦可。 第7圖為使用藉由本發明之電子機器用基板之製造方 法所製造出之薄膜電晶體基板的反射型液晶顯示裝置之一 例的概略示意圖。 < 此反射型液晶顯示裝置者，係於夾持液晶層59而相對 向之上側及下側玻璃基板51與52之上側破螭基板51之内面 ’自上側玻璃基板5 1起順序設置上側透明電極層$ 5及上 惻配向膜5 7，而於下側玻璃基板5 2之内側面自下側玻璃基 板5 2側起順序設置下側透明電極層5 6與下側配向膜5 8所 成。 液晶層5 9係配設於上側與下側之配向膜5 7及5 8間。於 側玻璃基板5 1之外表面側上設有上側偏光板6 0，於下側 玻璃基板5 2之外表面側上設有下側偏光板6 1，又，於下側 偏光板6 1之外表面侧上以使反射膜6 4之凹凸面6 5面上下側 偏光板6 1側之方式安裝著反射板6 2。反射板6 2係例如於表V. Description of the Invention (15) For example, the thickness and shape of the inscription film or inscription alloy film, titanium film, or titanium composite film. ,,, Without departing from the spirit of the present invention * changes. The stretched range can be varied. In the above-mentioned embodiment, it is explained that a single version of the etching | Lu film type narrated gold film 3 and a titanium film or a titanium alloy film 4 is formed by a laminated film:-口 7 力 乂In the case of the lower electrode layer 1 β h, it may be formed by integrally etching a titanium film or a titanium alloy film and forming a single layer of an aluminum alloy film or a titanium film or a titanium alloy film. π ^ In addition, it is the first explanation. Etching a titanium film or a titanium alloy film 10 and an aluminum film or an aluminum alloy film 丨 and a thin film / convergence: a laminated film of a gold film 10 to form a source electrode 2 and a drain electrode 4 and 'Lower ^ / 1 pole ^ layer & 16a, but it can also be formed by integrally etching an aluminum film or an aluminum alloy film and a titanium film. Fig. 7 is a schematic diagram showing an example of a reflective liquid crystal display device using a thin film transistor substrate manufactured by the method for manufacturing a substrate for an electronic device of the present invention. < For this reflective liquid crystal display device, the liquid crystal layer 59 is sandwiched between the upper and lower glass substrates 51 and 52, and the inner surface of the substrate 51 is broken. 'The upper surface is transparent from the upper glass substrate 51 in order. The electrode layer is $ 5 and the upper alignment film 5 7, and the lower transparent substrate layer 5 6 and the lower alignment film 5 8 are formed on the inner side of the lower glass substrate 5 2 in order from the lower glass substrate 5 2 side. . The liquid crystal layer 59 is disposed between the upper and lower alignment films 57 and 58. An upper polarizing plate 60 is provided on the outer surface side of the side glass substrate 51, and a lower polarizing plate 61 is provided on the outer surface side of the lower glass substrate 51, and one of the lower polarizing plates 61 is provided. A reflecting plate 62 is attached on the outer surface side so that the uneven surface 65 of the reflecting film 64 is on the upper and lower polarizing plates 61 side. The reflecting plate 6 2 is for example a watch
第20頁 486512 _案號88120996_年月曰 修正_ 五、發明說明（16) 面上形成有任意之凹凸面之聚酯膜片6 3之凹凸面上蒸鍍由 鋁或銀等所形成之金屬反射膜6 4而成膜形成者，其表面上 設有任意之凹凸面6 5。 於此反射型液晶顯示裝置上，玻璃基板5 2係相當於將 本發明之電子機器之製造方法適用於薄膜電晶體基板之製 造方法所製造出之實施型態例之薄膜電晶體基板1之基板 2，而下側透明電極層5 6係相當於I TO層（晝素電極）1 9。 依本實施型態之反射型液晶顯示裝置，因使用具有低 阻抗配線材之鋁膜或鋁合金膜之積層配線的薄膜電晶體基 板1，故起因於配線阻抗之訊號電壓之降低及配線延遲將 不易產生，可容易地實現配線較長之大面積之顯示及配線 為較細之高密度之顯示之最佳的顯示裝置者。 以下以實施例具體說明本發明，但本發明並不限定於 此等實施例。 (實施例1 ) 使用第4圖之電極電位測量裝置以下述之方式調查蝕 刻劑中之過碘酸之含有量及鋁電極與鈦電極間之電位差之 關係。 於容器内充滿餘刻劑後，於此#刻劑中浸潰銘電極及 鈦電極之兩電極，自電源施加電壓使電流流通，測量兩電 極間之電位差。在此之蝕刻劑係使用一定份量之氟酸 0 · 3 w t %與硫酸0 · 1 m ο 1 / 1 ( 0 · 5 4 w t % )，而過峨酸者係在 0. 0 5wt°/。至2. Owt%之範圍作變更。其結果如第8圖所示。 自第8圖所示之結果中可知，於蝕刻劑中包含0. 3wt%Page 20 486512 _Case No. 88120996_ Years and Months Amendment_ Five. Description of the invention (16) Polyester film 6 with any uneven surface formed on the surface 6 The uneven surface of 3 3 is vapor-deposited from aluminum or silver The metal reflective film 64 is formed into a film, and an arbitrary uneven surface 65 is provided on the surface. In this reflection type liquid crystal display device, the glass substrate 52 is a substrate equivalent to the thin film transistor substrate 1 of the implementation example manufactured by applying the manufacturing method of the electronic device of the present invention to the thin film transistor substrate manufacturing method. 2, and the lower transparent electrode layer 5 6 is equivalent to the I TO layer (day element electrode) 19. According to the reflective liquid crystal display device of this embodiment mode, since a thin-film transistor substrate 1 having an aluminum film or an aluminum alloy film laminated wiring with a low-impedance wiring material is used, the decrease in signal voltage and wiring delay due to the wiring impedance will be It is not easy to produce, and it is easy to realize a large-area display with a long wiring and an optimal display device with a thin and high-density display. Hereinafter, the present invention will be specifically described with examples, but the present invention is not limited to these examples. (Example 1) The relationship between the content of periodic acid in the etchant and the potential difference between the aluminum electrode and the titanium electrode was investigated in the following manner using the electrode potential measuring device of FIG. 4. After the container is filled with the remaining etching agent, the two electrodes of the Ming electrode and the titanium electrode are immersed in this #etching agent, a voltage is applied from a power source to cause a current to flow, and the potential difference between the two electrodes is measured. 0 5wt ° /。 Etchant here uses a certain amount of fluoric acid 0 · 3 w t% and sulfuric acid 0 · 1 m ο 1/1 (0 · 5 4 w t%), while permanganic acid is 0. 0 5wt ° /. Change to 2. Owt%. The results are shown in Figure 8. 3wt% As can be seen from the results shown in Figure 8
第21頁 486512 _案號88120996_年月曰 修正__ 五、發明說明（17) 之氟酸與0.1mol/l之硫酸時，當過碘酸之含有量為0.6wt% 以下時，鋁電極與鈦電極之電位差△ E將成為0 . 4 V以下。 電位差△ E為0 . 4 V時之相為於氟酸之過埃酸之重量比為2以 下，因此將相對於氟酸之過碘酸之重量比之上限設為2。 (實施例2)Page 21 486512 _Case No. 88120996_ Year and month amendment__ V. Description of the invention (17) When the hydrofluoric acid and 0.1mol / l sulfuric acid are used, when the content of periodic acid is 0.6wt% or less, the aluminum electrode The potential difference ΔE from the titanium electrode will be 0.4 V or less. When the potential difference ΔE is 0.4 V, the weight ratio of peracid acid to fluoric acid is 2 or less. Therefore, the upper limit of the weight ratio of periodic acid to fluoric acid is set to 2. (Example 2)
以下述方式調查蝕刻劑中之氟酸之含有量與鋁電極和 鈦電極間之電位差，與使用此I虫刻劑颠刻銘膜與I太膜之積 層膜時之側餘刻量△ L之關係。 關於蝕刻劑中的氟酸之含有量與鋁電極及鈦電極間之 電位差，作為蝕刻劑使用一定成份之1. 5 w t %之過碘酸及 lmol/l(5. 4wt% )之硫酸，且使用範圍為變更於0 . 1 w t %至0 . 8wt%之氟酸之物品，其他則以與上述實驗例1相同之方式 作測量。其結果如第9圖所示。 又，關於側蝕量，可用將膜厚1 3 0 0埃之鋁膜與膜厚 5 0 0埃之鈦膜之積層膜以改變氟酸含有量之蝕刻劑作一體 蝕刻時所測得之側蝕量△ L。其結果如第1 0圖所示。The amount of hydrofluoric acid in the etchant, the potential difference between the aluminum electrode and the titanium electrode, and the side engraving amount ΔL when the I film and the laminated film of the I film were etched were investigated in the following manner. relationship. Regarding the potential difference between the content of fluoric acid in the etchant and the aluminum electrode and the titanium electrode, 1.5 wt% periodic acid and 1 mol / l (5.4 wt%) sulfuric acid were used as the etchant, and The range of use is for items that have been changed from 0.1 wt% to 0.8 wt% of fluoric acid, and the others are measured in the same manner as in Experimental Example 1 above. The results are shown in Figure 9. Regarding the amount of side etching, a laminated film of an aluminum film with a thickness of 130 angstroms and a titanium film with a thickness of 500 angstroms can be used. Erosion ΔL. The results are shown in Fig. 10.
從第9圖及第1 0圖所示之結果可知，於蝕刻劑中含有 過埃酸1. 5 w t %及硫酸1 m ο 1 / 1時，當氟酸之含有量為 0 . 6 5 w t %以上之場合，則鋁電極與鈦電極間之電位差△ E成 為0. 4V以下，又，側蝕量△ L亦成為無實用上之問題之500 埃以下。特別是當氟酸之含有量為0 . 7 5 w t %以上時，側蝕 量△ L則成為2 5 0埃。 (實施例3)From the results shown in FIG. 9 and FIG. 10, it can be known that when the etchant contains peraconic acid 1.5 wt% and sulfuric acid 1 m ο 1/1, when the content of hydrofluoric acid is 0.6 5 wt In the case of% or more, the potential difference ΔE between the aluminum electrode and the titanium electrode becomes 0.4 V or less, and the side etching amount Δ L becomes 500 Angstroms or less without practical problems. In particular, when the content of hydrofluoric acid is 0.75 wt% or more, the side etching amount ΔL becomes 250 Angstroms. (Example 3)
第22頁 _案號>_ 881200^ 五、發明說明（18) 關於蝕刻劑中的硫酸之 電位差，作為蝕刻劑使用— 二·=氣酸’且使用範園 Γ第？二 上述實驗例 如弟1 1圖所不。 從第Π圖所示之处果 05wet%及氟酸 0.03W;時 °， 之W D ，則鋁電極與鈦電 ，故硫酸之重量比之下限 曰 知 0· 下 上 發明之效果】 如上所詳知私 ^ , 敘逑者，依 ^ J將低阻抗之# 膜之鈦膜或鍅人人+ 心銘 以-次之：:膜而形成 人 < 独刻及略4 』汉略相冋之蝕Page 22 _Case No.> 881200 ^ V. Explanation of the Invention (18) Regarding the potential difference of sulfuric acid in the etchant, it is used as an etchant—two · = gas acid ’and Fan Yuan is used. Second, the above experimental example, as shown in Figure 1 1 is not. From the point shown in Figure Π, 05wet% and hydrofluoric acid 0.03W; when °, WD, the aluminum electrode and titanium electricity, so the lower limit of the weight ratio of sulfuric acid is known as 0. The effect of the upper and lower inventions] As detailed above Knowing the private ^, the narrator, according to ^ J will the low-resistance # film of titanium film or 鍅 人人 + heart inscription-followed by :: the film to form people < engraved and slightly 4 』 eclipse
，依本發明之電子機 用上述構成《本發明之：:: 將上述積層犋之各構成之： 之蝕刻率實行 D 層與下声之㈤蝕刻故除可 θ配線之線寬外， 又’依本發明之恭 壓之降似β $ 之兒子機 卩牛低及配線延遲將不易 面私之顯示及 示裝置者。 &马車父 修正 t有量與鋁電極及鈦電極間之 疋成份之〇 Q5wt%之過峨酸及 為曼更於〇 w t %至〇 . 5 4 w t %之硫 1相同之方式作測量。其結果 ’於蝕刻劑中含有過碘酸 t碎l酸之含有量為〇. 〇5wt%以 才蛋間之電位差△ E成為0 · 4 V以 成為 〇 . 0 5 w t %。 本發明之蝕刻劑，因具有上述 膜或銘合金膜上積層其他金屬 之積層膜之各構成之各金屬膜 刻率實行蝕刻之優點。 杰用基板之製造方法，藉由使 弹1對上述積層膜作蝕刻，乃可 金屬膜以一次之蝕刻及略相同 各易地控制構成積層配線之上 其生產性良好，可縮短製造工 器，起因於配線阻抗之訊號電 產生，可容易地實現配線較長 細之高密度之顯示之最佳的顯The electronic machine according to the present invention uses the above-mentioned structure of the present invention: "Each of the above-mentioned laminated structures: The etching rate of the D layer and the underlying acoustic etching is performed so that in addition to the line width of theta wiring, According to the present invention, the pressure is lower than that of β $. The son of the machine yak is low and the wiring delay will not be easy to display and display. & Carriage Father's correction t is measured in the same manner as the sulphuric acid component of 0 ~ 5wt% permanganic acid between the aluminum electrode and the titanium electrode and sulphur 1 in the range of 0% to 0.54% by weight. . As a result, the content of periodic acid and pulverized acid in the etchant was 0.05% by weight so that the potential difference ΔE between the eggs was 0.4 V and 0.55% by weight. The etchant of the present invention has the advantage that the etching rate of each metal film of each structure of each of the above-mentioned films or laminated metal films laminated with other metals is etched. The manufacturing method of the used substrate is to make the above-mentioned laminated film etched by using the bullet 1. The metal film can be easily controlled with a single etching and slightly the same. The productivity is good, and the manufacturing tool can be shortened. The signal generated by the wiring impedance can easily realize the best display of the high-density display with long and thin wiring.
第23頁 486512 _案號88120996_年月日_修正 五、發明說明（19) 第24頁 486512 _案號88120996_年月 日 修正_ 圖式簡單說明 第1圖為揭示本發明之電子機器用基板之製造方法之實施 型態例之薄膜電晶體基板之製造方法之工程順序之概略 圖。 第2圖為揭示本發明之電子機器用基板之製造方法之實施 型態例之薄膜電晶體基板之製造方法之工程順序之概略 圖。 第3圖為利用本發明之電子機器用基板之製造方法所得之 薄膜電晶體基板之部份斷面圖。 第4圖為電極電位測量裝置之概略構成之示意圖。 第5圖為構成電極之金屬與電極電位之關係之示意圖。 第6圖為鋁電極與鈦電極間之電位差△ E與鋁及鈦之積層膜 之側钱量△ L之關係之示意圖。 第7圖為使用本實施型態例之薄膜電晶體基板之反射型液 晶顯示裝置之一例之概略圖。 第8圖為蝕刻劑中之過碘酸之含有量與鋁電極及鈦電極間 之電位差之關係之示意圖。 第9圖為蝕刻劑中之氟酸之含有量與鋁電極及鈦電極間之 電位差之關係之示意圖。 第1 0圖為蝕刻劑中之氟酸之含有量與使用此蝕刻劑蝕刻鋁 膜與鈦膜時之側餘量之關係圖。 第1 1圖為蝕刻劑中之硫酸之含有量與鋁電極及鈦電極間之 電位差之關係之示意圖。 第1 2圖為一般的薄膜電晶體型液晶顯示裝置之薄膜電晶體 部份之概略示意圖。 第13圖為形成於基板上之鋁膜及鈦膜之積層膜之斷面圖。Page 23 486512 _ Case No. 88120996 _ year month day _ amendment V. Description of the invention (19) Page 24 486512 _ Case No. 88120996 _ year month day _ revision illustration Brief description of the drawing Figure 1 is used to disclose the electronic device of the present invention A schematic diagram of a process sequence of a method for manufacturing a thin-film transistor substrate according to an embodiment of a method for manufacturing a substrate. Fig. 2 is a schematic diagram showing a process sequence of a method for manufacturing a thin-film transistor substrate, which is an embodiment of a method for manufacturing a substrate for an electronic device according to the present invention. Fig. 3 is a partial cross-sectional view of a thin-film transistor substrate obtained by the method for manufacturing a substrate for an electronic device according to the present invention. FIG. 4 is a schematic diagram of a schematic configuration of an electrode potential measuring device. Fig. 5 is a schematic diagram showing the relationship between the metal constituting the electrode and the electrode potential. Fig. 6 is a schematic diagram showing the relationship between the potential difference ΔE between the aluminum electrode and the titanium electrode and the side amount ΔL of the laminated film of aluminum and titanium. Fig. 7 is a schematic diagram of an example of a reflection type liquid crystal display device using the thin film transistor substrate of this embodiment. Fig. 8 is a schematic diagram showing the relationship between the content of periodic acid in the etchant and the potential difference between the aluminum electrode and the titanium electrode. Fig. 9 is a diagram showing the relationship between the content of hydrofluoric acid in the etchant and the potential difference between the aluminum electrode and the titanium electrode. Fig. 10 is a graph showing the relationship between the content of hydrofluoric acid in the etchant and the side margin when etching the aluminum film and the titanium film using the etchant. Fig. 11 is a schematic diagram showing the relationship between the content of sulfuric acid in the etchant and the potential difference between the aluminum electrode and the titanium electrode. Fig. 12 is a schematic diagram of a thin film transistor portion of a general thin film transistor type liquid crystal display device. Fig. 13 is a sectional view of a laminated film of an aluminum film and a titanium film formed on a substrate.
第25頁 486512 ___案號88120996_年月曰 修正_ 圖式簡單說明 第1 4圖為習知之電子機器用基板之製造方法之工程順序之 概略圖。 第1 5圖為習知之電子機器用基板之其他製造方法之工程順 序之概略圖。 【圖式元件符號】 1 薄膜電晶體基板 1、83 基板 3^ 11 鋁膜或鋁合金膜 4、10 鈦膜或鈦合金膜 5 閘電極 7 閘絕緣膜 8 半導體膜 9 η +型a-Si膜 12^ 88 源電極 15、89 漏電極 16a、16b 下部電極層 17 鈍化膜 18、20> 2 2、9卜9 5 接觸孔 19 ITO層 2 卜 23、 9 6上部電極層 2 7、3 7、3 8、9 7、9 8 光罩、光致抗蝕劑 24 通道 51 上侧玻璃基板 5 2 下側玻璃基板Page 25 486512 ___ Case No. 88120996_ Year Month Amendment _ Brief Description of Drawings Figures 14 and 14 are schematic diagrams of the engineering sequence of a conventional method for manufacturing a substrate for an electronic device. FIG. 15 is a schematic diagram of a process sequence of another conventional method for manufacturing a substrate for an electronic device. [Schematic symbol] 1 Thin film transistor substrate 1, 83 substrate 3 ^ 11 Aluminum film or aluminum alloy film 4, 10 Titanium film or titanium alloy film 5 Gate electrode 7 Gate insulation film 8 Semiconductor film 9 η + type a-Si Film 12 ^ 88 source electrode 15, 89 drain electrode 16a, 16b lower electrode layer 17 passivation film 18, 20 > 2 2, 9b 9 5 contact hole 19 ITO layer 2 b 23, 9 6 upper electrode layer 2 7, 3 7 , 3 8, 9 7, 9 8 Photomask, photoresist 24 channels 51 Upper glass substrate 5 2 Lower glass substrate
486512 案號88120996_年月日 修正 圖式簡單說明 55 上側透明電極 56 下側透明電極 57 上側配向膜 58 下側配向膜 59 液晶層 60 上側偏光板 61 下側偏光板 62 反射板 63 聚酯膜片 64 反射膜 65 凹凸面 75 電解液 76 容器 77> 78 電極 79 可變電阻 80 電源 82 薄膜電晶體 84 閘電極 85 絕緣膜 86 半導體能動膜 87 歐姆接觸層 90 鈍化膜 92 畫素電極 93 端子電極部 a 薄膜電晶體部486512 Case No. 88120996_Year Month and Day Correction Drawing Brief Description 55 Upper transparent electrode 56 Lower transparent electrode 57 Upper alignment film 58 Lower alignment film 59 Liquid crystal layer 60 Upper polarizer 61 Lower polarizer 62 Reflector 63 Polyester film Sheet 64 Reflective film 65 Concavo-convex surface 75 Electrolyte 76 Container 77> 78 Electrode 79 Variable resistor 80 Power source 82 Thin film transistor 84 Gate electrode 85 Insulating film 86 Semiconductor active film 87 Ohmic contact layer 90 Passivation film 92 Pixel electrode 93 Terminal electrode Section a thin film transistor section
第27頁 486512 _案號88120996_年月日_修正 圖式簡单說明 b、c 端子部 ITO 銦氧化錫Page 27 486512 _Case No. 88120996_ Year Month Day_ Amendment Brief description of the drawing b, c Terminal part ITO Indium tin oxide
第28頁Page 28
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW88120996A TW486512B (en) | 1999-12-01 | 1999-12-01 | Method of manufacturing a substrate for electronic device by using etchant and electronic device having the substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW88120996A TW486512B (en) | 1999-12-01 | 1999-12-01 | Method of manufacturing a substrate for electronic device by using etchant and electronic device having the substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW486512B true TW486512B (en) | 2002-05-11 |
Family
ID=21643221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW88120996A TW486512B (en) | 1999-12-01 | 1999-12-01 | Method of manufacturing a substrate for electronic device by using etchant and electronic device having the substrate |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW486512B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI487119B (en) * | 2008-10-10 | 2015-06-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing same |
-
1999
- 1999-12-01 TW TW88120996A patent/TW486512B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI487119B (en) * | 2008-10-10 | 2015-06-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100323733B1 (en) | Method of manufacturing a substrate for electric device by using etchant and electric device having the substrate | |
| JP4169896B2 (en) | Thin film transistor and manufacturing method thereof | |
| JP5244295B2 (en) | TFT substrate and manufacturing method of TFT substrate | |
| KR101199533B1 (en) | Echant and method for fabricating interconnection line and method for fabricating thin film transistor substrate using the same | |
| TWI285784B (en) | Method for manufacturing thin film transistor allay | |
| US20100163876A1 (en) | Reflective tft substrate and method for manufacturing reflective tft substrate | |
| JP4748473B2 (en) | Etching solution for conductor and method for manufacturing thin film transistor array panel using the same | |
| US11257810B2 (en) | Electrostatic discharge unit, array substrate and display panel | |
| CN102244103A (en) | TFT substrate | |
| KR20100130850A (en) | Thin film transistor substrate and manufacturing method thereof | |
| TW201128779A (en) | Thin film transistor and method of forming the same | |
| CN103545221B (en) | Metal oxide thin-film transistor and preparation method thereof | |
| KR20070008258A (en) | Etching solution and manufacturing method of liquid crystal display using same | |
| CN101419916B (en) | Manufacturing method of thin film transistor | |
| TW201420812A (en) | Etchant composition, method for forming metal pattern, and method for fabricating array substrate | |
| TW486512B (en) | Method of manufacturing a substrate for electronic device by using etchant and electronic device having the substrate | |
| TW200426498A (en) | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant | |
| TW200538835A (en) | Display device and method for manufacturing the same | |
| JP2005258115A (en) | Thin film transistor type substrate, thin film transistor type liquid crystal display device, and method of manufacturing thin film transistor type substrate | |
| JP2007189120A (en) | TFT substrate and manufacturing method thereof | |
| JPS61133662A (en) | Active matrix thin film transistor substrate | |
| JPS6329924A (en) | Manufacture of semiconductor device | |
| CN107170806A (en) | Gate electrode and preparation method thereof, array substrate manufacturing method | |
| JP3599174B2 (en) | Thin film transistor panel and method of manufacturing the same | |
| KR20190002381A (en) | Etchant composition for Ag thin layer and method for fabricating metal pattern using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MK4A | Expiration of patent term of an invention patent |