TW487970B - Film deposition method on semiconductor wafer surface - Google Patents
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- TW487970B TW487970B TW90113871A TW90113871A TW487970B TW 487970 B TW487970 B TW 487970B TW 90113871 A TW90113871 A TW 90113871A TW 90113871 A TW90113871 A TW 90113871A TW 487970 B TW487970 B TW 487970B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000000151 deposition Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 59
- 239000002243 precursor Substances 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims abstract description 30
- 230000008021 deposition Effects 0.000 claims abstract description 18
- 239000011261 inert gas Substances 0.000 claims abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 11
- 238000009832 plasma treatment Methods 0.000 claims abstract description 9
- 238000011065 in-situ storage Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 30
- 239000010409 thin film Substances 0.000 claims description 13
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- WZJUBBHODHNQPW-UHFFFAOYSA-N 2,4,6,8-tetramethyl-1,3,5,7,2$l^{3},4$l^{3},6$l^{3},8$l^{3}-tetraoxatetrasilocane Chemical compound C[Si]1O[Si](C)O[Si](C)O[Si](C)O1 WZJUBBHODHNQPW-UHFFFAOYSA-N 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 4
- 230000001965 increasing effect Effects 0.000 claims description 4
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 230000008859 change Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910000077 silane Inorganic materials 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 3
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 claims 2
- 229940094989 trimethylsilane Drugs 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 239000012495 reaction gas Substances 0.000 claims 1
- 230000036632 reaction speed Effects 0.000 claims 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 claims 1
- RSNQKPMXXVDJFG-UHFFFAOYSA-N tetrasiloxane Chemical compound [SiH3]O[SiH2]O[SiH2]O[SiH3] RSNQKPMXXVDJFG-UHFFFAOYSA-N 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 41
- 239000000047 product Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 210000001015 abdomen Anatomy 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000012265 solid product Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- Chemical Vapour Deposition (AREA)
Abstract
Description
487970 五、發明說明（1) 發明之領域 本發明提供一種於一半導體晶片表面上沉積一薄膜的 方法’以於该半導體晶片表面上沈積形成一表面均勻度佳 之薄膜。 背景說明 在半導體製程中，由於二氧化矽具有適當的介電常數 並與矽表面具有良好的結合能力，因此其應用十分廣泛， 一般用來作為閘極氧化膜（g a t e ο X i d e )、區域隔離氧化層 (local oxidation of silicon, LOCOS)或場氧化層 (field oxide)、層間介電層（interlayer dielectric)以 及墊氧化層（pad oxide)等等。而隨著半導體元件的微小 化，對一氧化石夕薄膜品質以及階梯覆蓋（s t e p c 〇 v e r a g e ) 能力要求也更為嚴格。 目前較常用來於半導體晶片表面上形成二氧化矽薄膜 的方法主要有二種：（1 )化學氣相沈積法（chemical vapor d e p o s 111 ο η，C V D)，（ 2 )熱氧化法，以及（3 )旋轉塗佈法。 其中 ’ C V D法又包括有 s i Η 4-低壓 CVD(low-pressure CVD， LPCVD)、TE0S-LPCVD以及電聚增強 CVD(plasma enhanced fVD， PECVD)等等類型。一般而言，利用CVD法所形成的二 氧化石夕薄膜具有較佳的階梯覆蓋能力。CVD法是利用化學487970 V. Description of the invention (1) Field of the invention The present invention provides a method of depositing a thin film on the surface of a semiconductor wafer 'to deposit a thin film with a good surface uniformity on the surface of the semiconductor wafer. BACKGROUND In semiconductor manufacturing processes, silicon dioxide has a wide range of applications because it has a suitable dielectric constant and a good bonding ability with the silicon surface. It is generally used as a gate oxide film and area isolation. A local oxidation of silicon (LOCOS) or field oxide, an interlayer dielectric, a pad oxide, and the like. With the miniaturization of semiconductor devices, the requirements for the quality of the oxide film and the step coverage (ste p c o v e r a g e) have become stricter. At present, there are mainly two methods for forming a silicon dioxide film on the surface of a semiconductor wafer: (1) chemical vapor deposition (CVD), (2) thermal oxidation, and (3) ) Spin coating method. Among them, the C V D method includes s i Η 4-low-pressure CVD (LPCVD), TEOS-LPCVD, and plasma enhanced fVD (PECVD). Generally speaking, the SiO 2 thin film formed by the CVD method has better step coverage ability. CVD method uses chemistry
第4頁 487970 五、發明說明（2) ----—-- 反應的方式，在反應器內& 積在晶片表面的一種薄腹將反應物生成固態生成物，並沉 化學氣相沉積已經成為目：：積技術。經過數十年的發展， 是最重要的技術之一。因=的半導體製程中’是最基本也 的化學反應以生成所需的二化學氣相沉積是藉反應氣體間 配比皆較優於使用濺錢法=暝，故其產物的結晶性與理想 所生成的薄膜。Page 4 487970 V. Description of the invention (2) -------- The reaction mode, a thin belly that accumulates on the surface of the wafer in the reactor, generates reactants into solid products, and deposits chemical vapor deposition Has become the head :: product technology. After decades of development, it is one of the most important technologies. Because in the semiconductor manufacturing process, 'is the most basic and chemical reaction to generate the required two chemical vapor deposition. The ratio of the reaction gases is better than using the sputtering method = 暝, so the crystallinity and ideality of the product The resulting film.
然而當利用PECVD法形成薄膜時，其厚度均句度 (thickness iinif〇rmit；y)極易受到溫度影響而產生誤 差，進而降低後續各項製程的良率，尤其當該薄膜係由具 較大分子之物質所構成時，此一影響更是特別明顯。針對 此一缺失’業界通常係利用調整氣體流量（gas n〇w rate)反應壓力及喷氣頭間距（sh〇werhea(j spacing)等 參數進行補償’以使所生成之薄膜具有較佳之厚度均勻 度。惟使用此種補償方式卻會改變薄膜的性質 (property)’導致產品功能受損，同時亦會縮限製程彈性 (process window)。隨著產品日益精密複雜，對於薄膜之 厚度均勻度的要求亦曰趨嚴格，因此，如何在不改變薄膜 性質的前提下’增進薄膜之厚度均勻度，實為一刻不容緩 的重要議題。However, when a PECVD method is used to form a thin film, its thickness thickness iiniform (y) is extremely susceptible to temperature and causes errors, thereby reducing the yield of subsequent processes, especially when the thin film This effect is particularly pronounced when composed of molecular matter. In response to this deficiency, 'the industry usually compensates by adjusting parameters such as gas flow rate (gas flow rate) reaction pressure and jet head spacing (showera (j spacing)') so that the resulting film has better thickness uniformity .However, the use of this compensation method will change the properties of the film, leading to the damage of the product's function and the shrinkage of the process window. As the products become more and more sophisticated, the thickness uniformity of the film is required. It is also becoming stricter. Therefore, how to 'improve the thickness uniformity of the film without changing the properties of the film is an important issue that cannot be delayed.
發明概述 因此本發明之主要目的在於提供一種利用一前驅物SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method using a precursor
第5頁 487970 五、發明說明（3) (precursor)A，於一半導體晶片表面上沉積一薄膜的方 法，以增進薄膜之厚度均勻度。 在本發明的最佳實施例中，一半導體晶片表面可至少 區分為一涵盖該半導體晶片中心之苐^一區域’以及一涵盖 該半導體晶片邊緣之第二區域，且該第一區域以及該第二 區域之間存在一高度梯度。首先於該半導體晶片表面進行 一同室（in-situ)鈍氣電聚處理（inert gas plasma treat men t)步驟，以於該第一區域以及該第二區域之間形 成一溫度梯度，造成該半導體晶片表面上之該第一區域以 及該第二區域之間產生一前驅物A沈積速度差異。接著於 完成該鈍氣電漿處理製程後，立即於該半導體晶片表面進 行一前驅物（precursor)A-化學氣相沉積(chemical vapor deposition， CVD)製程，以於該半導體晶片表面上沈積形 成一表面平·整之薄膜。 由於本發明之製作方法係於該半導體晶片表面上之該 第一區域以及該第二區域之間形成一溫度梯度，以於該第 一區域以及該第二區域之間產生一前驅物A沈積速度差 異，因此可在不改變薄膜性質的前提下增進薄膜之厚度均 勻度，消除由於該高度梯度所造成的薄膜表面均勾度不佳 問題。相對地在後續各項製程中，亦得以在不縮限製程彈 性（process window)的情況下，消弭由薄膜厚度均勻度不 佳所導致的各種問題，因而改善了產品良率並增加產品穩Page 5 487970 V. Description of the invention (3) (precursor) A: A method for depositing a thin film on the surface of a semiconductor wafer to improve the thickness uniformity of the thin film. In the preferred embodiment of the present invention, the surface of a semiconductor wafer can be divided into at least a region covering the center of the semiconductor wafer and a second region covering the edge of the semiconductor wafer. There is a high gradient between the two regions. First, an in-situ inert gas plasma treat men t step is performed on the surface of the semiconductor wafer to form a temperature gradient between the first region and the second region, causing the semiconductor A difference in deposition speed of the precursor A is generated between the first region and the second region on the wafer surface. Then, after the inert gas plasma processing process is completed, a precursor A-chemical vapor deposition (CVD) process is performed on the surface of the semiconductor wafer immediately to deposit and form a semiconductor wafer on the surface of the semiconductor wafer. Flat and smooth film. Since the manufacturing method of the present invention forms a temperature gradient between the first region and the second region on the surface of the semiconductor wafer, a precursor A deposition rate is generated between the first region and the second region. It can improve the uniformity of the thickness of the film without changing the properties of the film, and eliminate the problem of poor uniformity of the film surface caused by the height gradient. In contrast, in the subsequent processes, the problems caused by the poor uniformity of the film thickness can be eliminated without reducing the process window, thereby improving the product yield and increasing product stability.
第6頁 487970 五、發明說明（4) 定度，進而提昇產品競爭優勢。 發明之詳細說明 δ月參考圖一至圖二’圖一至圖三為本發明於一半導體 晶片表面上沉積一薄膜之方法示意圖。如圖〜所示，一半 導體晶片3 0表面包含有一涵蓋半導體晶片3 〇中心之第一區 域3 2以及一涵蓋半導體晶片30邊緣之第二區域34，且如圖 二所示，第一區域3 2低於第二區域3 4，使第—區域3 2以及 第二區域3 4之間存在一高度梯度，故半導體晶片3 〇表面呈 現一下凹（concave)曲線。 · 首先在低於2托耳（t 〇 r r )之低壓環境下，於半導體晶 片3 0表面進行一同室（in — situ )鈍氣電漿處理（inert gas plasma treatment)製程，利用流量介於2 5 0 0至5 0 0 0標準 立方公分每分鐘（standard cubic centimeters per minute, seem)之氨氣電漿（NH3 plasma)，配合 0.5 至 1.5W/cm乏無線電功率（rf power)，以於第一區域32以及 第二區域3 4之間形成一溫度梯度，使第一區域3 2之表面溫 度低於第一區域3 4之表面溫度。 於完成該鈍氣電漿處理製程後，立即於半導體晶片3 0 表面進行一前驅物（precursor)A-電漿加強化學氣相沉積 (plasma enhanced chemical vapor deposition, PECVD)Page 6 487970 V. Description of the invention (4) Determine the degree, thereby improving the competitive advantage of the product. DETAILED DESCRIPTION OF THE INVENTION δ is referred to FIG. 1 to FIG. 2 'FIG. 1 to FIG. 3 are schematic diagrams of a method for depositing a thin film on a semiconductor wafer surface according to the present invention. As shown in the figure, a surface of a semiconductor wafer 30 includes a first region 32 covering the center of the semiconductor wafer 30 and a second region 34 covering the edge of the semiconductor wafer 30. As shown in FIG. 2, the first region 3 2 is lower than the second region 34, so that there is a height gradient between the first region 32 and the second region 34, so the surface of the semiconductor wafer 30 has a concave curve. · First perform inert gas plasma treatment process on the surface of the semiconductor wafer 30 in a low-pressure environment below 2 Torr (t0rr), using a flow rate of 2 5 0 0 to 5 0 0 0 Standard cubic centimeters per minute (NH3 plasma) with 0.5 to 1.5 W / cm of RF power (rf power) A temperature gradient is formed between a region 32 and the second region 34, so that the surface temperature of the first region 32 is lower than the surface temperature of the first region 34. Immediately after completing the inert gas plasma processing process, a precursor A-plasma enhanced chemical vapor deposition (PECVD) was performed on the surface of the semiconductor wafer 30.
第7頁 487970 五、發明說明（5) 製程，以於半導體晶片3 0表面上沈積形成一由一低介電常 數（1 〇w k )材料所構成’且具有一均勻度低於1 · 3% (± 1 σ )之平整表面之薄膜。其中該同室鈍氣電漿處理製程與 該前驅物A - P E C V D製程係於同一反應室（chamber)中進行， 且前驅物A係具備沉積反應速度隨溫度上升而下降的特點 之物質，諸如四乙氧基矽烷 (tetra-ethyl-ortho-silicate， TE0S)、三甲基矽烷 (tri-methyl si lane, 3MS)、四甲基石夕烧（tetra-methyl silane， 4MS )與四甲基環四石夕氧烧（tetra-methyl cyclo tetra-siloxane， TMCTS)等物質。由於第一區域32之表面 溫度低於第二區域3 4之表面溫度，因此可於半導體晶片3 0 表面上之第一區域3 2以及第二區域3 4之間產生一前驅物A 沈積速度差異，使前驅物A在第一區域3 2之沈積速度高於 在第二區域3 4之沈積速度’藉以消除由於該高度梯度所造 成的薄膜表面均勻度不佳問題。 如圖三所示，在本發明之另一實施例中，當半導體晶 片3 0表面之第一區域3 2高於第二區域34，使半導體晶片30 表面呈現一上凸（convex)曲線時，則在高於8托耳之高壓 環境下，於半導體晶片3 0表面進行一同室鈍氣電漿處理製 程，以使第一區域3 2之表面溫度高於第二區域3 4之表面溫 度。之後採用前述具備沉積反應速度隨溫度上升而下降的 特點之前驅物A，立即於半導體晶片3 0表面進行該前驅物 A - P E C V D製程’以於半導體晶片3 0表面上沈積形成一具有Page 7 487970 V. Description of the invention (5) A process for depositing on the surface of semiconductor wafer 30 to form a low dielectric constant (100wk) material 'and having a uniformity of less than 1.3% (± 1 σ) film with a flat surface. The in-chamber plasma processing process and the precursor A-PECVD process are performed in the same chamber, and the precursor A is a substance having a characteristic that the deposition reaction rate decreases with temperature, such as tetraethyl Tetra-ethyl-ortho-silicate (TE0S), tri-methyl si lane (3MS), tetra-methyl silane (4MS) and tetramethylcyclotetralith Oxygen burning (tetra-methyl cyclo tetra-siloxane, TMCTS) and other substances. Since the surface temperature of the first region 32 is lower than the surface temperature of the second region 34, a precursor A deposition speed difference can be generated between the first region 32 and the second region 34 on the surface of the semiconductor wafer 30. The deposition speed of the precursor A in the first region 32 is higher than that in the second region 34, thereby eliminating the problem of poor surface uniformity of the thin film due to the height gradient. As shown in FIG. 3, in another embodiment of the present invention, when the first region 32 on the surface of the semiconductor wafer 30 is higher than the second region 34, so that the surface of the semiconductor wafer 30 presents a convex curve, Then, in a high-pressure environment higher than 8 Torr, a chamber inert gas plasma processing process is performed on the surface of the semiconductor wafer 30 so that the surface temperature of the first region 32 is higher than the surface temperature of the second region 34. Thereafter, the precursor A, which has the aforementioned characteristic that the deposition reaction rate decreases with temperature, is immediately used to perform the precursor A-P E C V D process' on the surface of the semiconductor wafer 30 to deposit on the surface of the semiconductor wafer 30.
第8頁 487970 五、發明說明（6) 一均勻度低於1 · 3% (± 1 σ )之平整表面之薄膜。由於第一 區域3 2之表面溫度高於第二區域3 4之表面溫度，因此前驅 物Α在第一區域3 2之沈積速度低於在第二區域3 4之沈積速 度，故可藉此消除由於該高度梯度所造成的薄膜表面均勻 度不佳問題。 在本發明之另一實施例中，當半導體晶片3 0表面之第 一區域3 2高於第二區域3 4，使半導體晶片3 0表面如圖三所 示呈現一上凸（c ο n v e X )曲線時，亦可在低於2托耳之低壓 環境下，於半導體晶片3 0表面進行一同室鈍氣電漿處理製 程，以使第一區域3 2之表面溫度低於第二區域3 4之表面溫 度。之後採用一具備沉積反應速度隨溫度上升而增加的特 點之前驅物A，如甲石夕烧（silane，SiH 4)，立即於半導體 晶片30表面進行該前驅物A-PECVD製程，以於半導體晶片 3 0表面上沈積形成一具有一均勻度低於1. 3% (± 1 σ )之平 整表面之薄膜。由於第一區域3 2之表面溫度低於第二區域 3 4之表面溫度，因此前驅物Α在第一區域3 2之沈積速度低 於在第二區域3 4之沈積速度，故可藉此消除由於該高度梯 度所造成的薄膜表面均勻度不佳問題。 在本發明之另一實施例中，當半導體晶片3 0表面之第 一區域3 2低於第二區域3 4，使半導體晶片3 0表面如圖二所 示呈現一下凹（concave)曲線時，亦可在高於8托耳之高壓 環境下，於半導體晶片3 0表面進行一同室鈍氣電漿處理製Page 8 487970 V. Description of the invention (6) A film with a flat surface with a uniformity lower than 1.3% (± 1 σ). Since the surface temperature of the first region 32 is higher than the surface temperature of the second region 34, the deposition rate of the precursor A in the first region 32 is lower than that in the second region 34, so it can be eliminated by this. The problem of poor surface uniformity of the film due to this height gradient. In another embodiment of the present invention, when the first region 32 on the surface of the semiconductor wafer 30 is higher than the second region 34, the surface of the semiconductor wafer 30 is shown as a convex (c ο nve X ) Curve, in a low-pressure environment of less than 2 Torr, the same chamber inert gas plasma processing process can be performed on the surface of the semiconductor wafer 30, so that the surface temperature of the first region 32 is lower than the second region 3 4 The surface temperature. Thereafter, a precursor A, such as silane (SiH 4), which has a characteristic that the deposition reaction rate increases with temperature is used, and the precursor A-PECVD process is immediately performed on the surface of the semiconductor wafer 30 for semiconductor wafers. A thin film having a flat surface with a uniformity of less than 1.3% (± 1 σ) was deposited on the 30 surface. Since the surface temperature of the first region 32 is lower than the surface temperature of the second region 34, the deposition rate of the precursor A in the first region 32 is lower than that in the second region 34, so it can be eliminated by this. The problem of poor surface uniformity of the film due to this height gradient. In another embodiment of the present invention, when the first region 32 on the surface of the semiconductor wafer 30 is lower than the second region 34, so that the surface of the semiconductor wafer 30 has a concave curve as shown in FIG. It can also be processed in a high-pressure environment higher than 8 Torr on the surface of the semiconductor wafer 30 with inert gas plasma treatment.
第9頁 487970 五、發明說明（7) 程，以使第一區域3 2之表面溫度高於第二區域3 4之表面溫 度。之後採用前述具備沉積反應速度隨溫度上升而增加的 特點之前驅物A，立即於半導體晶片3 0表面進行該前驅物 A-PECVD製程，以於半導體晶片30表面上沈積形成一具有 一均勻度低於1. 3% (± 1 σ )之平整表面之薄膜。由於第一 區域3 2之表面溫度高於第二區域3 4之表面溫度，因此前驅 物Α在第一區域3 2之沈積速度高於在第二區域3 4之沈積速 度，故可藉此消除由於該高度梯度所造成的薄膜表面均勻 度不佳問題。 相較於習知利用調整氣體流量（g a s f 1 〇 w r a t e )、反 應壓力及喷氣頭間距（showerhead spacing)等參數進行補 償以改善薄膜之厚度均勻度的方法，本發明係於半導體晶 片3 0表面上之第一區域3 2以及第二區域3 4之間形成一溫度 梯度，以於第一區域3 2以及第二區域3 4之間產生一前驅物 A沈積速度差異。因此可有效增進薄膜之厚度均勻度，消 除由於該高度梯度所造成的薄膜表面均勻度不佳問題，同 時不會縮限製程彈性（process window)，亦不會改變薄膜 性質而導致產品功能受損。故種種由於薄膜厚度均勻度不 佳而在後續各項製程中所導致的問題，亦得以完全消弭。 因此產品良率可獲得大幅改善，產品穩定度亦得以顯著增 加，進而提昇產品競爭優勢。 以上所述僅本發明之較佳實施例，凡依本發明申請專Page 9 487970 V. Description of the invention (7), so that the surface temperature of the first region 32 is higher than the surface temperature of the second region 34. After that, the precursor A, which has the characteristics that the deposition reaction rate increases with temperature, is immediately adopted, and the precursor A-PECVD process is immediately performed on the surface of the semiconductor wafer 30 to form a low uniformity on the surface of the semiconductor wafer 30. Film on a flat surface of 1.3% (± 1 σ). Since the surface temperature of the first region 32 is higher than the surface temperature of the second region 34, the deposition speed of the precursor A in the first region 32 is higher than that in the second region 34, so it can be eliminated by this. The problem of poor surface uniformity of the film due to this height gradient. Compared to the conventional method of adjusting the gas flow (gasf 1 0wrate), the reaction pressure, and the showerhead spacing to improve the thickness uniformity of the film, the present invention is on the surface of the semiconductor wafer 30 A temperature gradient is formed between the first region 32 and the second region 34 to generate a difference in the deposition rate of the precursor A between the first region 32 and the second region 34. Therefore, the thickness uniformity of the film can be effectively improved, and the problem of poor surface uniformity of the film caused by the high gradient can be eliminated. At the same time, the process window will not be reduced, and the properties of the film will not be changed and the product function will be damaged. . Therefore, the problems caused by the subsequent processes due to the poor uniformity of the film thickness can be completely eliminated. Therefore, the product yield can be greatly improved, and the stability of the product can be significantly increased, thereby enhancing the competitive advantage of the product. The above are only the preferred embodiments of the present invention.
第10頁 487970 五、發明說明（8) 利範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋 範圍。 iiii 第11頁 487970 圖式簡單說明 圖示之簡單說明 圖一至圖三為本發明於一半導體晶片表面上沉積一薄 膜之方法示意圖。 圖示之符號說明 30 半導體晶片 32 第一區域 34 第二區域Page 10 487970 V. Description of the invention (8) Equal changes and modifications made within the scope of the invention shall all fall within the scope of the invention patent. iiii Page 11 487970 Brief description of the diagrams Brief description of the diagrams Figures 1 to 3 are schematic diagrams of a method for depositing a thin film on the surface of a semiconductor wafer according to the present invention. Explanation of symbols in the diagram 30 Semiconductor wafer 32 First region 34 Second region
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105485355A (en) * | 2016-01-21 | 2016-04-13 | 江南阀门有限公司 | Hard-sealing and low-temperature butterfly valve and sealing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105485355A (en) * | 2016-01-21 | 2016-04-13 | 江南阀门有限公司 | Hard-sealing and low-temperature butterfly valve and sealing method thereof |
| CN105485355B (en) * | 2016-01-21 | 2018-06-08 | 江南阀门有限公司 | A kind of hard sealing low temperature butterfly valve and its encapsulating method |
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