TW497231B - Stack structure of semiconductor chips and its manufacturing method - Google Patents

Stack structure of semiconductor chips and its manufacturing method Download PDF

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Publication number
TW497231B
TW497231B TW090103758A TW90103758A TW497231B TW 497231 B TW497231 B TW 497231B TW 090103758 A TW090103758 A TW 090103758A TW 90103758 A TW90103758 A TW 90103758A TW 497231 B TW497231 B TW 497231B
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Taiwan
Prior art keywords
semiconductor wafer
substrate
layer
patent application
stacked structure
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TW090103758A
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Chinese (zh)
Inventor
Meng-Ru Tsai
Jen-Bin Peng
Nai-Hua Ye
Jr-Cheng Wu
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Kingpak Tech Inc
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Priority to TW090103758A priority Critical patent/TW497231B/en
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Publication of TW497231B publication Critical patent/TW497231B/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The present invention is related to stack structure of semiconductor chips and its manufacturing method. It includes a substrate, a low-layer semiconductor chip, a gluing layer, plural conducting wires and an upper-layer integrated circuit. The substrate is provided with signal input terminal and signal output terminal for electrically connecting to a printed circuit board. The central part of the lower-layer semiconductor chip is provided with plural bonding pads. The lower-layer semiconductor chip is adhered on the substrate through the gluing layer. In addition, the periphery of the lower-layer integrated circuit is covered by the overflow of the gluing layer so as to prevent plural conducting wires from generating the phenomenon of short circuit with the lower-layer semiconductor chip or bad signal transmission due to the pressing of the upper-layer semiconductor chip.

Description

497231 五、發明說明（1) 本發明為一種半導體晶片之堆疊構造及其封裝方法， 特別係指一用以防止半導體晶片在堆疊時所造成電性傳遞 不良或短路之情形，且其製造上相當便利者。 在科技的領域，各項科技產品皆以輕、薄、短小為其 訴求，因此，對於積體電路的體積係越小越理想，更可符 合產品之需求。而以往積體電路即使體積再小，亦只能並 列式地電連接於電路板上，而在有限的電路板面積上，並 無法將積體電路的容置數量有效地提昇，是以，欲使產品 達到更為輕、薄、短小之訴求，將有其困難之處。 因此，將若干個半導體晶片予以疊合使用，可達到 輕、薄、短小的訴求，然而，將若干個半導體晶片疊合 時，上層半導體晶片將會壓到下層半導體晶片之導線，使 該導線與下層半導體晶片表面形成電性接觸，以致將影響 到下層半導體晶片之訊號傳遞。 是以，習知一種半導體晶片之堆疊構造，請參閱圖 一，其包括有一基板10、一下層半導體晶片12、一上層半 導體晶片1 4、複數個導線1 6及一隔離層1 8。下層半導體晶 片1 2係設於基板1 0上，上層半導體晶片1 4係藉由隔離層1 8 疊合於下層半導體晶片1 2上方，使下層半導體晶片1 2與上 層半導體晶片1 4形成一適當之間距2 0，如是，複數個導線 1 6即可電連接於下層半導體晶片1 2邊緣，上層半導體晶片 1 4疊合於下層半導體晶片1 2上時，不致於壓損複數個導線 1 6 〇 然而，此種結構在製造上必須先製作隔離層1 8，再將497231 V. Description of the invention (1) The present invention is a semiconductor wafer stacking structure and a packaging method thereof, and particularly refers to a situation for preventing poor electrical transmission or short circuit caused by semiconductor wafers during stacking, and the manufacturing thereof is equivalent. Convenience. In the field of technology, all technology products are light, thin and short. Therefore, the smaller the volume of the integrated circuit, the more ideal it is, and the more it can meet the needs of the product. In the past, even if the integrated circuit is small, it can only be electrically connected to the circuit board side by side. On a limited circuit board area, the number of integrated circuits cannot be effectively increased. Therefore, There will be difficulties in making products lighter, thinner and shorter. Therefore, stacking several semiconductor wafers can achieve light, thin, and short requirements. However, when several semiconductor wafers are stacked, the upper semiconductor wafer will be pressed onto the conductors of the lower semiconductor wafer, so that the conductors and Electrical contact is formed on the surface of the lower semiconductor wafer, which will affect the signal transmission of the lower semiconductor wafer. Therefore, a stacked structure of a semiconductor wafer is known. Please refer to FIG. 1, which includes a substrate 10, a lower semiconductor wafer 12, an upper semiconductor wafer 14, a plurality of wires 16, and an isolation layer 18. The lower semiconductor wafer 12 is disposed on the substrate 10, and the upper semiconductor wafer 14 is superimposed on the lower semiconductor wafer 12 by an isolation layer 18 so that the lower semiconductor wafer 12 and the upper semiconductor wafer 14 form an appropriate The distance is 20. If so, the plurality of wires 16 can be electrically connected to the edge of the lower semiconductor wafer 12 and the upper semiconductor wafer 14 is superimposed on the lower semiconductor wafer 12 without compressing the plurality of wires 16. However, this structure must be manufactured with an isolation layer 18 before manufacturing.

90046.ptd 第4頁 497231 五、發明說明（2) 其黏著於下層半導體晶片1 2上，而後再將上層半導體晶片 1 4黏著於隔離層1 8上，是以，其製造程序較為複雜，生產 成本較高。 再者，若下層半導體晶片1 2之焊墊形成於中央部位 時，則並無法以上述之方法實施堆疊。 請參閱圖二，為焊墊2 2形成於下層半導體晶片2 3中央 部位之堆疊情形，此時，上層半導體晶片2 4將會壓到導線 2 5，使導線2 5接觸到下層半導體晶片2 4邊緣，以致造成電 訊之傳遞不佳或短路之現象。 有鑑於此，本發明人乃本於精益求精、創新突破之精 神，而發明出本發明半導體晶片之堆疊構造及其封裝方 法，其可有效解決上述之缺點，且其製造上更為便利，而 可降低生產成本。 本發明之主要目的，在於提供一種積體電路堆疊構造 及其製造方法，其具有便於將積體電路予以堆疊之功效， 以達到提高生產速度之目的。 本創作之另一目的，在於提供一種積體電路堆疊構造 及其製造方法，其可將半導體晶片予以堆疊時，不致產生 電性傳遞不良之現象。 本創作之又一目的，在於提供一種積體電路堆疊構造 及其製方法，其可避免上層積體電路壓到下層積體電路之 導線，且其製程上相當便利。 是以，為達上述之目的，本發明之主要特徵在於包括 有：90046.ptd Page 4 497231 V. Description of the invention (2) It is adhered to the lower semiconductor wafer 12 and then the upper semiconductor wafer 14 is adhered to the isolation layer 18, so the manufacturing process is more complicated and production higher cost. Furthermore, if the bonding pads of the lower semiconductor wafer 12 are formed at the central portion, stacking cannot be performed by the above-mentioned method. Please refer to FIG. 2, for the case where the pads 22 are formed at the central portion of the lower semiconductor wafer 2 3. At this time, the upper semiconductor wafer 2 4 will be pressed to the wire 25 and the wire 25 will contact the lower semiconductor wafer 2 4 Edges, resulting in poor transmission or short circuits of telecommunications. In view of this, the inventor is based on the spirit of excellence, innovation and breakthrough, and invented the stacking structure and packaging method of the semiconductor wafer of the present invention, which can effectively solve the above disadvantages, and its manufacturing is more convenient, and reduce manufacturing cost. The main object of the present invention is to provide a stacked circuit structure and a manufacturing method thereof, which have the effect of facilitating the stacking of integrated circuits to achieve the purpose of improving the production speed. Another object of the present invention is to provide a stacked circuit stack structure and a manufacturing method thereof, which can stack semiconductor wafers without causing a phenomenon of poor electrical transmission. Another purpose of this creation is to provide a stacked circuit stack structure and a manufacturing method thereof, which can prevent the upper stacked circuit from being pressed onto the conductors of the lower stacked circuit, and its manufacturing process is quite convenient. Therefore, in order to achieve the above-mentioned object, the main features of the present invention include:

90046.ptd 第5頁 497231 五、發明說明（3) 一基板，其具有一第一表面及一第二表面，該第一表 面形成有訊號輸入端，該第二表面形成有訊號輸出端，用 以電連接於印刷電路板上； 一下層半導體晶片，其設有一上表面及一下表面，該 上表面中央部位設有複數個焊墊； 一黏膠層，其係用以將該下層半導體晶片之下表面黏 著於該基板之第一表面，且該黏膠層之溢膠將覆蓋於該下 層積體電路之上表面周邊； 複數條導線，其一端係電連接於該下層積體電路之焊 墊上，另一端電連接於該基板之訊號輸入端；及 一上層半導體晶片，其係疊設於該下層半導體晶片之 上表面上，而與該下層半導體晶片形成堆疊，且其係電連 接於該基板之訊號輸入端。 如是，將半導體晶片予以堆疊時，可藉由黏膠層之溢 膠覆蓋住下層半導體晶片，使複數條導線不致與下層半導 晶片形成短路，而導致電訊傳遞不良之現象。 本案得藉由以下圖式及說明，得以更深入之暸解。 圖一為習知半導體晶片堆疊構造之剖示圖。 圖二為習知半導體晶片堆豐構造之不意圖。 圖二為本發明半導體晶片堆豐構造之不意圖。 圖四為本發明半導體晶片之堆豐構造之剖視圖。 圖五為本發明半導體晶片之堆豐構造之不意圖。 請參閱圖三、圖四及圖五，本發明半導體晶片之堆疊 構造，包括有一基板2 6，一下層半導體晶片2 8，一黏著層90046.ptd Page 5 497231 V. Description of the invention (3) A substrate having a first surface and a second surface, the first surface is formed with a signal input terminal, and the second surface is formed with a signal output terminal. It is electrically connected to the printed circuit board. The lower semiconductor wafer is provided with an upper surface and a lower surface, and a plurality of solder pads are provided at the center of the upper surface. An adhesive layer is used to connect the lower semiconductor wafer. The lower surface is adhered to the first surface of the substrate, and the overflow of the adhesive layer will cover the periphery of the upper surface of the lower layer circuit; a plurality of wires, one end of which is electrically connected to the bonding pad of the lower layer circuit The other end is electrically connected to the signal input end of the substrate; and an upper semiconductor wafer is stacked on the upper surface of the lower semiconductor wafer to form a stack with the lower semiconductor wafer, and it is electrically connected to the substrate Signal input. If so, when stacking the semiconductor wafers, the lower semiconductor wafers can be covered by the adhesive of the adhesive layer, so that the plurality of wires will not form a short circuit with the lower semiconductor wafers, resulting in poor telecommunication transmission. This case can be understood more deeply with the following drawings and descriptions. FIG. 1 is a sectional view of a conventional semiconductor wafer stack structure. FIG. 2 is a schematic diagram of a conventional semiconductor wafer stack structure. FIG. 2 is a schematic diagram of a semiconductor wafer stack structure of the present invention. FIG. 4 is a sectional view of a stack structure of a semiconductor wafer according to the present invention. FIG. 5 is a schematic diagram of a stack structure of a semiconductor wafer according to the present invention. Please refer to FIG. 3, FIG. 4 and FIG. 5. The stacked structure of the semiconductor wafer of the present invention includes a substrate 26, a lower semiconductor wafer 28, and an adhesive layer.

90046.ptd 第6頁 497231 五、發明說明（4) 3 0 ’複數條導線3 2及一上層半導體晶片3 4。 , 基板26具有一第一表面3 6及第二表面38，第一表面36 形成有訊號輸入端4 0，該第二表面3 8形成有訊號輸出端 4 2 號輸出端4 2為球柵陣列金屬球（b a 1 1 g r i d a r r a y ) ’用以電連接於電路板上（圖未顯示）。 下層半導體晶片28設有一下表面44及一上表面46，下 表面44係設置於基板26之第一表面36上，而上表面46中央 部位形成有若干個焊墊4 8，用以電連接於基板2 6之訊號輸 入端4 0。 黏著層3 0係設置於下層半導體晶片2 8之下表面4 4與基 板2 6之第一表面3 6間，用以將下層半導體晶片2 8黏著固定 於基板2 6。黏著層3 0加熱液化使下層半導體晶片2 8黏著於 基板2 6上時’位於下層半導體晶片2 8之下表面4 4的黏著層 3 0將溢出下層半導體晶片2 8之下表面4 4，而黏著層3 〇之溢 膠5 0將延著下層半導體晶片2 8周邊延伸至下層半導體晶片 28之上表面46，以致將下層半導體晶片28周邊包覆住。 另’基板26上於下層半導齓1片28周邊形成有阻隔層μ， 用以阻隔溢膠5 0往基板2 6四周擴散，使溢膠5 〇往上堆積覆 盍於下層半莫體晶片2 8之上表面4 6四週邊，本實施例中， 阻隔層5 2係以綠漆覆設於基板2 6上，在製造上更為便利。 —請參閱圖四，將下層半導體晶片28固著於基板2 6後， 將複數條導線3 2—端電連接於位於下層半導體晶片2 8中央 部位之焊墊48，另一端電連接於基板26之訊號輸入端4〇， 使下層半導體晶片2 8之訊號傳遞至基板2 6上。此時，複數90046.ptd Page 6 497231 V. Description of the invention (4) 3 0 ′ A plurality of wires 32 and an upper semiconductor wafer 34. The substrate 26 has a first surface 36 and a second surface 38. The first surface 36 is formed with a signal input terminal 40, and the second surface 38 is formed with a signal output terminal 4 and the second output terminal 42 is a ball grid array. The metal balls (ba 1 1 gridarray) are used to be electrically connected to the circuit board (not shown). The lower semiconductor wafer 28 is provided with a lower surface 44 and an upper surface 46. The lower surface 44 is disposed on the first surface 36 of the substrate 26, and a plurality of pads 48 are formed at the center of the upper surface 46 for electrical connection to Signal input terminal 40 of substrate 26. The adhesive layer 30 is disposed between the lower surface 44 of the lower semiconductor wafer 28 and the first surface 36 of the substrate 26, and is used for adhesively fixing the lower semiconductor wafer 28 to the substrate 26. When the adhesive layer 30 is heated and liquefied to make the lower semiconductor wafer 2 8 adhere to the substrate 26, the adhesive layer 30 located on the lower surface 4 4 of the lower semiconductor wafer 28 will overflow the lower surface 4 4 of the lower semiconductor wafer 28, and The overflow adhesive 50 of the adhesive layer 30 extends along the periphery of the lower semiconductor wafer 28 to the upper surface 46 of the lower semiconductor wafer 28, so that the periphery of the lower semiconductor wafer 28 is covered. In addition, a barrier layer μ is formed on the substrate 26 around the lower layer of a semiconducting wafer 28 to block the overflow of the adhesive 50 from spreading around the substrate 2 6 so that the overflow of the adhesive 50 is piled up and covered on the lower semi-molecular wafer. The upper surface of 2 8 has four perimeters. In this embodiment, the barrier layer 5 2 is coated on the substrate 26 with a green paint, which is more convenient in manufacturing. — Please refer to FIG. 4, after the lower semiconductor wafer 28 is fixed to the substrate 26, a plurality of wires 3 2-are electrically connected to the pads 48 located at the center of the lower semiconductor wafer 28, and the other end is electrically connected to the substrate 26. The signal input terminal 40 allows the signal of the lower semiconductor wafer 28 to be transmitted to the substrate 26. At this time, the plural

五、發明說明（5) 條導線32係位於下 方，而後，將上層 層半導體晶片28^ 複數條導線3 2上， 有溢膠5 0之隔絕， 致有電性之接觸雨 片28藉由複數條導 使上層半導體晶片 體晶片之堆疊。 另外，以一封 28及上層半導體晶 5 6 ’如是，即完成 藉如上之構造 其製造方法具有如 1 ·可使上層半導體 電連於下層半導體 層半導體晶片28隔 &線3 2，亦不致使 電接觸，而產生短 2 ·當下層半導體晶 通膠50包覆住下層 3 2不致因上層半導 形成電接觸，以影 §便利，可降低半 曰+ ¥體曰曰片2 8之上表面4 6之溢 守股曰曰片3 4藉由黏膠5 4黏著堆疊於下 方L此時’上層半導體晶片34雖壓設於 但複數條導線3 2與下層半導體晶片2 8 使複數條導線32與下層半導體晶片28^ 產生短路之現象。而後，上層半導體曰 線56電連接於基板26之訊號輸入端^曰，曰 34之訊號傳遞至基板26上，以完成半導 膠層58覆蓋於基板26、下層半導體晶片 片3 4上方’用以保護複數條導線3 2、 半導體晶片之堆疊封裝。 組合，本發明半導體晶片之堆疊構 下之優點： ，片3 4疊合於下層半導體晶片2 8上時， 晶片2 8之複數條導線3 2藉由溢膠5 〇與下 離，使上層半導體晶片3 4雖壓著複數條 複數條導線3 2與下層半導體晶片2 二 路或壓損之現象。 元成 片2 8黏著於基板2 6時，藉由黏膠層3 〇之 半體晶片2 8之上表面3 6，使複數條導線 體晶片34之壓著而與下層半導體晶片μ 響到訊號之傳遞，其在堆疊之製造上相 導體晶片在堆疊時，欲解決電性傳遞不V. Description of the invention (5) The wires 32 are located below, and then the upper semiconductor wafer 28 ^ is separated from the plurality of wires 32 by the overflow of the glue 50, so that the electrical contact with the rain piece 28 is caused by the plurality The strip guides stack the upper semiconductor wafer body wafers. In addition, with a piece of 28 and the upper semiconductor crystal 5 6 ', if so, the structure is completed. The manufacturing method is as follows: 1. The upper semiconductor can be electrically connected to the lower semiconductor layer semiconductor wafer 28 and the line 32, and Causes electrical contact, resulting in a short 2 · When the lower semiconductor wafer 50 covers the lower layer 3 2 does not cause electrical contact due to the upper semiconductor, which is convenient and can reduce half + + body body 2 2 8 The surface 4 6 of the overflowing strand is said to be laminated 3 4 with adhesive 5 4 stacked on the bottom L. At this time, although the upper semiconductor wafer 34 is pressed on, but a plurality of wires 3 2 and the lower semiconductor wafer 2 8 make a plurality of wires 32 and the lower semiconductor wafer 28 ^ have a short circuit phenomenon. Then, the upper semiconductor line 56 is electrically connected to the signal input terminal of the substrate 26, and the signal of 34 is transmitted to the substrate 26 to complete the semiconductive adhesive layer 58 to cover the substrate 26 and the lower semiconductor wafer 34. In order to protect the plurality of wires 3 2, the stacked package of the semiconductor chip. In combination, the advantages of the stacked structure of the semiconductor wafer of the present invention are: When the wafer 3 4 is stacked on the lower semiconductor wafer 28, the plurality of wires 32 of the wafer 28 are separated from the upper semiconductor by the overflow of the glue 50 and the lower semiconductor is removed. Although the wafer 3 4 is pressed with the plurality of wires 32 and the lower-layer semiconductor wafer 2 is in a two-way or pressure loss phenomenon. When the elementary piece 28 is adhered to the substrate 26, the upper surface 36 of the half body wafer 28 of the adhesive layer 30 is pressed to make the plurality of wire body wafers 34 pressed to the signal of the lower semiconductor wafer μ. In the manufacture of the stack, the phase conductor chip is stacked to solve the electrical transfer failure.

497231 五、發明說明（6) 良所產生製造成本提高之課題。 在較佳實施例之詳細說明中所提出之具體實施例僅為 為了易於說明本發明之技術内容，並非將本發明狹義地限 制於實施例，凡依本發明之精神及以下申請專利範圍之情 況所作種種變化實施均屬本發明之範圍。497231 V. Description of the invention (6) The problem of increasing manufacturing cost caused by good. The specific embodiments proposed in the detailed description of the preferred embodiments are only for easy explanation of the technical content of the present invention, and are not intended to limit the present invention to the embodiments in a narrow sense. In the spirit of the present invention and the scope of patent application below The various changes made are within the scope of the present invention.

90046.ptd 第9頁 497231 圖式簡單說明 圖"一為習知半導體晶片堆豐構造之剖不圖。 圖二為習知半導體晶片堆疊構造之示意圖。 圖三為本發明半導體晶片堆疊構造之示意圖。 圖四為本發明半導體晶片之堆豐構造之剖視圖。 圖五為本發明半導體晶片之堆豐構造之不意圖。 標號說明 基板26 下層半導體晶片2 8 黏著層3 0 複數條導線3 2 上層半導體晶片3 4 第一表面3 6 第二表面3 8 訊號輸入端4 0 訊號輸出端4 2 下表面4 4 上表面4 6 焊塾48 溢膠50 阻隔層5 2 黏膠54 複數條導線5 6 封膠層5 890046.ptd Page 9 497231 Brief description of the drawings Figure "A section of the conventional semiconductor wafer stack structure." FIG. 2 is a schematic diagram of a conventional semiconductor wafer stack structure. FIG. 3 is a schematic diagram of a semiconductor wafer stack structure according to the present invention. FIG. 4 is a sectional view of a stack structure of a semiconductor wafer according to the present invention. FIG. 5 is a schematic diagram of a stack structure of a semiconductor wafer according to the present invention. Description of reference numerals Substrate 26 Lower semiconductor wafer 2 8 Adhesive layer 3 0 Plural wires 3 2 Upper semiconductor wafer 3 4 First surface 3 6 Second surface 3 8 Signal input terminal 4 0 Signal output terminal 4 2 Lower surface 4 4 Upper surface 4 6 Solder pad 48 Overfill 50 Barrier layer 5 2 Adhesive 54 Multiple wires 5 6 Sealant 5 8

90046.ptd 第10頁90046.ptd Page 10

Claims (1)

497231497231 1 · 一種半導體晶片之堆疊構造，其係用以電連接於印 路板上，包括有： 一基板，該基板具有一第一表面及一第二表面，該第 一表面形成有訊號輸入端，該第二表面形成有訊號輸出 端，用以電連接於該印刷電路板上； 一下層半導體晶片’其設有一上表面及一下表面，該 上表面中央部位設有複數個焊墊；1. A stacked structure of a semiconductor wafer, which is used to be electrically connected to a printed circuit board, and includes: a substrate having a first surface and a second surface, the first surface forming a signal input terminal, A signal output terminal is formed on the second surface for electrically connecting to the printed circuit board; the lower semiconductor wafer is provided with an upper surface and a lower surface, and a plurality of solder pads are provided at the central portion of the upper surface; 一黏膠層，其係用以將該下層半導體晶片之下表面黏 著於該基板之第一表面，且該黏膠層之溢膠將覆蓋於該下 層半導體晶片之上表面； 複數條導線，其一端係電連接於該下層半導體晶片之 焊墊上，另一端電連接於該基板之訊號輸入端；及 一上層半導體晶片’其係疊設於該下層半導體晶片之 上表面上’而與該下層半導體晶片形成堆疊，且其係電連 接於該基板之訊號輸入端。 2 ·如申凊專利範圍第1項所之半導體晶片之堆疊構造，其 中該基板之訊號輸出端為球栅陣列式（B g a )之金屬球。An adhesive layer is used to adhere the lower surface of the lower semiconductor wafer to the first surface of the substrate, and the overflow of the adhesive layer will cover the upper surface of the lower semiconductor wafer; a plurality of wires, which One end is electrically connected to the bonding pad of the lower semiconductor wafer, and the other end is electrically connected to the signal input end of the substrate; and an upper semiconductor wafer 'which is stacked on the upper surface of the lower semiconductor wafer' and is connected to the lower semiconductor The chips form a stack and are electrically connected to the signal input terminal of the substrate. 2 · The stacked structure of the semiconductor wafer as described in item 1 of the patent application, wherein the signal output end of the substrate is a ball grid array (B g a) metal ball. 3 ·如申请專利範圍第1項所述之半導體晶片之堆疊構造， 其中該基板之第一表面上位於下層半導體晶片側邊形成有 阻隔層’用以阻撐黏膠層之溢膠’使溢膠往下層半導體晶 導體晶片之堆疊構造， 成於該基板之第一表 4 ·如申請專利範圍第3項所述之半 其中該阻隔層係以覆設綠漆方式形 面03 · The stacked structure of a semiconductor wafer as described in item 1 of the scope of the patent application, wherein a barrier layer 'for resisting the overflow of the adhesive layer' is formed on the first surface of the substrate on the side of the lower semiconductor wafer The stacked structure of the semiconductor crystal conductor wafer on the lower layer is formed on the first table of the substrate. As described in the third half of the scope of the patent application, the barrier layer is shaped in the form of green paint. 第11頁 2002.01.16.011 497231 六、申請專利範圍 5.如申請專利範圍第1項所述之半導體晶片之堆疊構造， 其中該上層半導體晶片係藉由複數條導線電連於該基板之 訊號輸入端。 6 .如申請專利範圍第1項所述之半導體晶片之堆疊構造， 其更包括有一封膠層，用以封住該下層半導體晶片及該上 層半導體晶片，以保護該等複數條導線。 7. —種半導體晶片之堆疊構造之封裝方法，其包括下列步 驟： 提供一基板，該基板具有一第一表面及一第二表面， 該第一表面形成有訊號輸入端，該第二表面形成有訊號輸 出端； 提供一下層半導體晶片，其設有一上表面及一下表 面，該上表面中央部位設有複數個焊墊； 提供一黏膠層，該黏膠層係位於該下層半導體晶片與 該基板間，用以將該下層半導體晶片之下表面黏者於該基 板之第一表面，而該黏膠層之溢膠將覆蓋於該下層積體電 路之上表面； 提供複數條導線，其一端係電連接於該下層積體電路 之焊墊上，另一端電連接於該基板之訊號輸入端；及 提供一上層半導體晶片，其係疊設於該下層半導體晶 片之上表面上，而與該下層半導體晶片形成堆疊，且其係 電連接於該基板之訊號輸入端。 8 .如申請專利範圍第7項所述之半導體晶片之堆疊構造之 封裝方法，其中該基板之訊號輸出端為球柵陣列式（B G A)Page 11 2002.01.16.011 497231 VI. Patent application scope 5. The stacked structure of the semiconductor wafer as described in item 1 of the patent application scope, wherein the upper semiconductor wafer is electrically connected to the signal input terminal of the substrate through a plurality of wires. . 6. The stacked structure of the semiconductor wafer as described in item 1 of the scope of the patent application, further comprising an adhesive layer for sealing the lower semiconductor wafer and the upper semiconductor wafer to protect the plurality of wires. 7. A packaging method for a stacked structure of semiconductor wafers, comprising the following steps: providing a substrate having a first surface and a second surface, the first surface is formed with a signal input terminal, and the second surface is formed There is a signal output terminal; a lower semiconductor wafer is provided, which is provided with an upper surface and a lower surface, and a plurality of pads are provided at the center of the upper surface; an adhesive layer is provided, and the adhesive layer is located between the lower semiconductor wafer and the Between the substrates, the lower surface of the lower semiconductor wafer is adhered to the first surface of the substrate, and the overflow of the adhesive layer will cover the upper surface of the lower layer integrated circuit; a plurality of wires is provided, and one end thereof is provided Is electrically connected to the bonding pad of the lower layer integrated circuit, and the other end is electrically connected to the signal input end of the substrate; and an upper semiconductor wafer is provided, which is stacked on the upper surface of the lower semiconductor wafer and is connected to the lower layer The semiconductor wafers are stacked and electrically connected to the signal input terminal of the substrate. 8. The packaging method of a stacked structure of a semiconductor wafer as described in item 7 of the scope of patent application, wherein the signal output end of the substrate is a ball grid array (B G A) 90046.ptd 第12頁 497231 六、申請專利範圍 之金屬球。 9 .如申請專利範圍第7項所述之半導體晶片之堆疊構造之 封裝方法，其中該基板之第一表面上位於下層半導體晶片 側邊形成有阻隔層，用以阻擋溢膠層之溢膠，使溢膠往下 層半導體晶片之上表面攀伸。 1 0 .如申請專利範圍第9項所述之半導體晶片之堆疊構造之 封装方法，其中該阻隔層係以點綠漆方式形成於該基板之 第一表面上。 1 1.如申請專利範圍第7項所述之半導體晶片之堆疊構造之 封裝方法，提供一封膠層，用以封住該下層半導體晶片及 該上層半導體晶片，以保護該等複數條導線。90046.ptd Page 12 497231 6. Metallic Balls within the scope of Patent Application. 9. The packaging method for a stacked structure of a semiconductor wafer as described in item 7 of the scope of the patent application, wherein a barrier layer is formed on the first surface of the substrate on the side of the lower semiconductor wafer to block the overflow of the overflow layer, Make the overflow glue extend to the upper surface of the lower semiconductor wafer. 10. The method for packaging a stacked structure of a semiconductor wafer according to item 9 of the scope of the patent application, wherein the barrier layer is formed on the first surface of the substrate in a dot green paint manner. 1 1. The packaging method for a stacked structure of a semiconductor wafer as described in item 7 of the scope of the patent application, providing an adhesive layer to seal the lower semiconductor wafer and the upper semiconductor wafer to protect the plurality of wires. 90046.ptd 第13頁90046.ptd Page 13
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