503676 A： B7 3〇6twf. doc/006 五、發明說明（I ) 本發明是有關於一種基板外接墊的製作方法5且特 別是有關於一種可改善習知無法有效利用防銲層之開口孔 徑之問題點的基板外接墊的製作方法。 近年來，爲因應電子產品日益輕、薄、短、小之趨勢’ 印刷電路板（Printed Circuit Board，PCB)上之佈線設計及 製作亦須加以改良。爲增加線路佈線密度（Lay〇ut Density)，除了使線路細微化之外，對於印刷電路板表層 的防銲層開口的孔徑也跟著愈來愈小（由之前的1〇〇微米縮 小到現今的70或80微米），以使印刷電路板之面積使用更 有效率。 然而，在習知的印刷電路板技術中，對於外接墊及防 銲層開口的做法仍存在有許多的問題點，詳如下述。 請參考第1~第2圖，其繪示習知基板上外接墊之製作 流程剖視圖。 i 在習知的印刷電路板技術中，如第1圖所示，係先在 基板100之上形成多個外接墊圖案102a。接著，如第2圖 所示，在外接墊圖案102a及基板100之表面上，利用、 曝光等步驟形成一圖案化的防銲層112。此圖案化@卩方銲 層112具有多個開口 112a，以暴露出外接墊圖案1〇2a。 在此處，防銲層112係爲一種高介電質的材料，其作· 用除了保護外接墊圖案102a及其他表層之線路 示）以外，更可利用其高介電質的特性，避免外接塾@案 102a之間及線路圖案彼此之間不必要的電性導通。 然而，防銲層112因受到濕製程(顯影製程）的卩艮制， 3 本紙張尺度適用中國國家標準（CNS)/\4規格（2丨0 X 297公釐） ii ——— I·裝 i! I訂i (請先閱讀背面之注意事項再填寫本頁) 線 經濟部智慧財產局員工消費合作社印製 S306twf.doc/006 S306twf.doc/006 經齊部智慧財產局員Η消費合作社印製 五、發明說明（1) 其開口 112a會呈傾斜式地縮小，尤其是對於高介電暂的 材料，此-傾斜將更爲明顯。是以，造成習知無法有 用防銲層m之開口 112a的孔徑，而造成基板1〇〇之 使用效率低的問題點。而且，此傾斜式縮小的孔徑更會使 得製程變異性大增，尤其是針對日益縮小的孔徑需求，此 類的變異性，將使得製程難以控制⑽對防婷層112之開口 112a暴露出之外接墊i02a之面積大小難以控制）。 此外，當於防銲層的顯影製程中發生顯影不潔的情況 時，由外接墊圖案102a和防銲層112係位於不同的平面， 故無法有效地去除顯影不潔，使得外接墊1〇2a和內層線 路（圖未繪示）之接觸不良或電性不佳，而使得製程良率下 降。 綜上所述’習知的基板外接墊的製作方法存在的問題 點有：無法有效利用防銲層開口孔徑（即暴露出之外接墊 102a之面積），造成基板之面積使用效率下降;形成防銲開 口的製程變異性大(即暴露出之外接墊l〇2a之面積變異性 大），而使得製程難以控制;無法有效去除顯影不潔，而使 得製程良率下降。 本發明的目的係，提出一種基板外接墊的製作方法， 可改善習知無法有效利用防銲層之開口孔徑的缺點，而可 提高基板之面積使用效率。 本發明的目的係，提出一種基板外接墊的製作方法， 其對暴露出外接墊l〇2a的製程變異性較習知爲小，其製 程控制較習知爲容易。 — —— —— —— —裝-----ί訂i (請先閱讀背面之注咅？事項再填寫本頁) 線 0 本紙張尺度適用中國國家標準_视公料〉 503676 8 3 0 6twf. doc/0 0 6 Λ7 Γ>7 經濟部智慧財產局員工消費合作社印製 五、發明說明（>) 本發明的目的係，提出一種基板外接墊的製作方法， 可避免習知防銲層顯影不潔的問題，而使得製程良率提 昇。 爲解決習知的問題點，及達成本發明上述及其他目 的，本發明提出一種基板外接墊的製作方法，包括：提供 一基板及一外接墊層，全面性地形成一銅鍍層於基板與外 接墊層之表面。形成一圖案化光阻層於銅鍍層上，以暴露 出部份之銅鍍層，使導柱層、（受導柱層覆蓋之)銅鍍層及(受 銅層覆蓋之）外接墊圖案形成一外接墊。形成一導柱層於 暴露出之部份銅鍍層上。移除圖案化光阻層並移除未受導 柱層覆蓋而暴露出之部份銅鍍層。形成一防銲層於基板與 導柱層之表面。去除部份的防銲層，並暴露出導柱層，使 得防銲層與導柱層同高。其中，外接墊層係配置於基板之 上，且外接墊層具有多個外接墊圖案。圖案化光阻層並具 有多個開口，分別對應每一外接墊圖案。 依照本發明之特徵，因外接墊和防銲層位於同平面， 後續製程之處理較容易（例如將晶片與基板連接時的打線 步驟，或是將覆晶晶片的凸塊與基板連接時的接合步驟）。 依照本發明之特徵，因先形成外接墊，再藉由全面形 成一防銲層，並去部份之防銲層，以暴露出導柱層，故可 充分利用暴露出之外接墊面積，而提高基板之面積使用效 率。 依照本發明之特徵，因利用光阻層其介電係數小於防 銲層介電係數的特性，光阻層之開口呈傾斜式縮小的現象 5 • ΙΙΙΙΙΙΙ1ΙΙΙ - I I I I I 1· I ^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A、丨規格（210 X 297公釐） 503676 Λ7 B7 8 3 0 6twf. doc/00 6 五、發明說明（f) 會比防銲層之開口輕微，故可減少暴露出外接墊製程的變 異性，而使得暴露出之外接墊面積容易控制。 (讀先閱讀背面之注意事項再填寫本頁) 依照本發明之特徵，可避免習知防銲層顯影不潔的問 題點5而提筒製程良率。 爲讓本發明之上述目的、特徵和優點能夠明顯易懂， 下文特舉一較佳實施例，並配合所附圖示，作詳細說明如 下： 匮式之簡單說明 第1〜2圖繪示習知基板上外接墊之製作流程剖視圖； 以及 第3〜14圖繪示依照本發明之較佳實施例之一種基板 外接墊之製作流程剖視圖。 圖式標號之簡蚩說明 100、200 :基板 102a、202a:外接墊圖案 206:光阻層 經濟部智慧財產局員工消費合作社印製 201、206a:圖案化光阻層 202 :外接墊層 112、212、212a :防銲層 112a、207、212a:開口 204、204a:銅鍍層 208:導柱層 214:外接墊 較佳實施例 6 本紙張尺度適用中國國家標準（CNS)Al規格（210x297公釐〉 503676 8306twf. doc/006 Λ7 B7 經齊部智慧財產局員工消費合作社印製 五、發明說明（r) 請參考第3〜14圖，其爲依照本發明之較佳實施例之 一種基板外接墊之製作流程剖視圖。 請先參考第6圖，提供一基板200，例如爲一印刷電 路板，基板200之材質可爲樹脂片（Prepreg)，例如是玻 璃環氧基樹脂之FR-4基板、雙順丁烯二酸醯亞胺 (Bismaleimide-Triazine，BT)樹脂之 BT 基板等，或爲環 氧樹脂或其他絕緣材料。並如第6圖所示，於基板200上 形成有多個外接墊圖案202a，其材質例如爲銅（Copper， Cu)。其中，形成外接墊層圖案202a的方法例如爲微影、 蝕刻，詳如第3〜5圖所示。 如第3圖所示，於基板200上壓合一外接墊層202， 例如爲銅箔。如第4圖所示，於外接墊層202上形成一圖 案化光阻層201，暴露出部份之外接墊層202，其形成圖 案化光阻層201的方法舉例而言包括鐳射去膜或曝光、顯 影。接著，如第5圖所示，去除暴露出之外接墊層202， 以得多個外接墊圖案202a，其去除暴露出外接墊層202的 方法例如爲蝕刻。最後，移除圖案化光阻層201，以得如 第6圖之結構。 如第7圖所示，全面性地形成一銅鍍層204於基板200 與外接墊層圖案202a之表面上。其中，銅鍍層204之材質 例如爲以氧化還原反應所沈積之化學銅。接著，如第9圖 所示’形成一圖案化光阻層206a於銅鍍層204上。其中， 形成圖案化光阻層206a之方法如第8〜第9圖所示。 如第8圖所示，先形成一光阻層206於銅鍍層204之 7 !·裝·！ (請先閱讀背面之注意事項再填寫本頁) 訂· — n n n n I 丨 m 本紙張尺度適用中國國家標準（CNS〉A1規格（2Η)χ297公釐） 經濟部智慧財產局員工消費合作社印製 503676 五、發明說明) 上。接著，如第9圖所示，圖案化此光阻層206，以形成 多個開口 207’使得外接墊圖案202a上的部份銅鍍層204， 可透過圖案化光阻層206a的開口 207而暴露於外。其中， 每一開口 207係分別對應每一外接墊圖案202a。圖案化光 阻層206的方法例如爲鐳射去膜或是曝光（photography)、 顯影（development)。 此處，在圖案化光阻層206的過程中，其形成的開口 207雖亦會有略微傾斜式內縮的情況發生，但相較於習知 (如第2圖)在圖案化防銲層112以形成開口 112a的步驟， 画案化光阻層206a的開口 207之內縮情形明顯要輕微得多 (如第9圖），甚至可忽略此一傾斜的影響，而形成孔壁與 基板200之表面幾乎呈垂直的開口 207。 如第10圖所示，塡滿開口 207而形成導柱層2〇g。其 形成導柱層208的方法，例如可藉由銅鍍層2〇4作爲種子 層(seed layer)，以電鍍銅或濺鍍的方式塡滿開口 2〇7，亦 可以印刷塡入或浸式（例如先以高溫乾膜覆蓋住不需塡入 的部份，再將之浸入於鎔融的金屬材料中）的方法$成導 柱層208。接著’如第11圖所示’移除_案化光阻層2〇以* 暴露出導柱層208及部份的銅鍍層204。 如第π圖所示’移除未受導柱層2〇8覆蓋而暴露出 之部份的銅鍍層204a，以避免不必要的電性導通。並由$ 份的銅鑛層204、導柱層208及外接塾_案^2a，=同^ 成類似柱狀結構的外接墊214。其中’移除銅鍍層2〇4的 方法例如S快速倉虫刻（Flash Etching)，由於銅鑛層2〇4 8 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公釐） illl·!— — — — — — Aw * I I 1 I I l I ^ * I I (請先閱讀背面之注咅？事項再填寫本頁} 線,. 五 ___ 經濟部智慧財產局員工消費合作社印製 503676 8306twf.doc/ 006 A 7 發明說明（rp 之厚度遠小於外接墊層圖案202a及導柱層208的厚度，因 此藉由快速餓刻的方式來移除銅鍍層204，將不會破壞外 接墊層圖案202a及導柱層2〇8。 如第13圖所示’全面性地形成一防銲層212於基板 200、外接墊圖案202a與導柱層208之表面上，其中，防 銲層212之材質例如爲防銲綠漆(s〇ider mask)或是其他與防 銲綠漆相似的介電材料。如第14圖所示，去除部份之防 銲層212使得去除後之防銲層212a與外接墊214同高，並 暴露出外接墊214。其中，去除部份之防銲層212的方法 包括硏磨或是以化學溶解方式去除部份之防銲層。 依照本發明之特徵，因於圖案化光阻層206a上可形 成孔壁與基板200之表面幾乎呈垂直的開口 207,並在形 成外接墊214之後，全面形成一防銲層212於外接墊214 及基板200之表面，再去除部份之防銲層212以暴露出外 接墊214。是故，本發明可有效利用暴露出之外接墊214 的面積，進而提高基板200之面積使用效率。而且，本發 明可避免習知防銲層顯影不潔的問題點，進而提高製程之 良率。 依照本發明之特徵，同理如上，故可大幅減低習知(如 第2圖）防銲層112受限於顯影製程，而使得防銲層Π2之 開口 112a呈傾斜式內縮的影響。是故，本發明之暴露出 外接墊214的製程變異性小，旦可容易控制暴露出外接墊 214之面積。 依照本發明特徵，因外接墊214和防銲層212a位於同 9 n n n n n n ϋ ϋ ϋ n i * β,β e . ▲ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)AI規格（210x 297公釐） 503676503676 A: B7 3〇6twf. Doc / 006 V. Description of the invention (I) The present invention relates to a method for manufacturing an external pad of a substrate 5 and, in particular, to an opening aperture that can improve the conventional method and cannot effectively use a solder resist. The manufacturing method of the substrate external pad of the problem point. In recent years, in response to the trend of electronic products becoming lighter, thinner, shorter, and smaller, the printed circuit board (PCB) wiring design and manufacturing must also be improved. In order to increase the wiring density (Layout Density), in addition to making the circuit finer, the aperture of the solder mask opening on the surface of the printed circuit board has also become smaller and smaller (from the previous 100 microns to the current 70 or 80 microns) to make printed circuit board area more efficient. However, in the conventional printed circuit board technology, there are still many problems with the method of opening the external pad and the solder resist layer, as described below. Please refer to Figures 1 to 2 for a cross-sectional view of the manufacturing process of the external pad on the conventional substrate. i In the conventional printed circuit board technology, as shown in FIG. 1, a plurality of external pad patterns 102a are formed on the substrate 100 first. Next, as shown in FIG. 2, a patterned solder resist layer 112 is formed on the surface of the external pad pattern 102a and the substrate 100 by steps such as exposure. The patterned @ 卩 方 焊 层 112 has a plurality of openings 112a to expose the external pad pattern 102a. Here, the solder mask layer 112 is a high-dielectric material. In addition to protecting the external pad pattern 102a and other surface layers, it can also take advantage of its high-dielectric properties to avoid external contact.案 @ 案 102a and unnecessary electrical conduction between circuit patterns. However, since the solder resist 112 is made by a wet process (development process), 3 paper sizes are applicable to the Chinese National Standard (CNS) / \ 4 specifications (2 丨 0 X 297 mm) ii ——— I · installation i! I order i (Please read the notes on the back before filling out this page) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Online Economics S306twf.doc / 006 S306twf.doc / 006 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of Qibu V. Description of the invention (1) The opening 112a will be narrowed obliquely, especially for high-dielectric materials, this tilt will be more obvious. Therefore, the hole diameter of the opening 112a of the solder mask m cannot be used conventionally, and the problem that the use efficiency of the substrate 100 is low is caused. In addition, the obliquely reduced aperture diameter will greatly increase the process variability, especially for the ever-decreasing aperture requirements. Such variability will make it difficult to control the process. The size of the pad i02a is difficult to control). In addition, when the developing process is unclean during the development process of the solder resist layer, the external pad pattern 102a and the solder resist layer 112 are located on different planes, so the developing uncleanness cannot be effectively removed, so that the external pad 102a and the inner pad The layer circuit (not shown) has poor contact or poor electrical properties, which reduces the process yield. In summary, the conventional manufacturing method of the substrate external pad has the following problems: the opening aperture of the solder resist layer cannot be effectively used (that is, the area of the external pad 102a is exposed), resulting in a decrease in the use efficiency of the substrate area; The process variability of the welding opening is large (that is, the area variability of the exposed pad 102a is large), which makes the process difficult to control; the development uncleanness can not be effectively removed, and the process yield is reduced. The object of the present invention is to provide a method for manufacturing an external pad of a substrate, which can improve the disadvantage that the opening aperture of the solder resist cannot be used effectively, and can improve the area efficiency of the substrate. An object of the present invention is to provide a method for manufacturing a substrate external pad, which has less variability in the process of exposing the external pad 102a, and its process control is easier than conventional. — —— —— —— —Install ----- I order (please read the note on the back? Matters before filling out this page) Line 0 This paper size applies to Chinese national standard _ See public material> 503676 8 3 0 6twf. Doc / 0 0 6 Λ7 Γ &7; 7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (>) The purpose of the present invention is to provide a method for manufacturing an external pad of a substrate, which can avoid the conventional soldering protection. The problem of unclean layer development makes the process yield increase. In order to solve the conventional problems and achieve the above and other objectives of the present invention, the present invention proposes a method for manufacturing a substrate external pad, including: providing a substrate and an external pad layer, and comprehensively forming a copper plating layer on the substrate and the external pad. The surface of the cushion. Forming a patterned photoresist layer on the copper plating layer to expose a part of the copper plating layer, so that the guide pillar layer, the copper plating layer (covered by the guide pillar layer), and the (covered by the copper layer) external pad pattern form an external pad. A pillar layer is formed on the exposed copper plating layer. The patterned photoresist layer is removed and a portion of the copper plating layer that is not covered by the pillar layer is exposed. A solder resist is formed on the surface of the substrate and the pillar layer. Remove part of the solder mask layer and expose the pillar layer so that the solder mask layer is the same height as the pillar layer. The external pad layer is disposed on the substrate, and the external pad layer has a plurality of external pad patterns. The patterned photoresist layer has a plurality of openings corresponding to each external pad pattern. According to the features of the present invention, since the external pad and the solder resist layer are on the same plane, subsequent processing is easier (such as the wire bonding step when connecting the wafer to the substrate, or the bonding when connecting the bumps of the flip-chip wafer to the substrate step). According to the features of the present invention, since an external pad is formed first, and then a solder resist layer is formed in its entirety, and a part of the solder resist layer is removed to expose the pillar layer, so the area of the exposed pad can be fully utilized, and Improve the area use efficiency of the substrate. According to the features of the present invention, due to the use of the photoresist layer with a dielectric constant smaller than that of the solder resist layer, the opening of the photoresist layer is obliquely reduced. 5 • ΙΙΙΙΙΙΙ1ΙΙΙΙ-IIIII 1 · I ^ (Please read the back first Please note this page before filling in this page) This paper size applies Chinese National Standard (CNS) A, 丨 specifications (210 X 297 mm) 503676 Λ7 B7 8 3 0 6twf. Doc / 00 6 V. Description of the invention (f) The opening of the solder mask is slight, so the variability of the process of exposing the external pad can be reduced, and the area of the external pad exposed can be easily controlled. (Read the precautions on the back before you fill in this page.) According to the features of the present invention, it is possible to avoid the problem 5 of the unclean solder mask development and to improve the yield of the cylinder process. In order to make the above-mentioned objects, features, and advantages of the present invention comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings, and described in detail as follows. A cross-sectional view of a manufacturing process of an external pad on a substrate is shown; and FIGS. 3 to 14 show cross-sectional views of a manufacturing process of a substrate external pad according to a preferred embodiment of the present invention. 100, 200: Substrate 102a, 202a: External pad pattern 206: Photoresist layer Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 201, 206a: Patterned photoresist layer 202: External pad layer 112, 212, 212a: solder mask layer 112a, 207, 212a: opening 204, 204a: copper plating 208: guide pillar layer 214: external pad preferred embodiment 6 This paper size applies Chinese National Standard (CNS) Al specification (210x297 mm) 〉 503676 8306twf. Doc / 006 Λ7 B7 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of Qibu V. Invention Description (r) Please refer to Figures 3 ~ 14, which is a substrate external pad according to a preferred embodiment of the present invention A cross-sectional view of the manufacturing process. Please refer to FIG. 6 first to provide a substrate 200, such as a printed circuit board. The material of the substrate 200 may be a resin sheet (Prepreg), such as a glass epoxy resin FR-4 substrate, double BT substrates such as bismaleimide-triazine (BT) resin, or epoxy or other insulating materials. As shown in FIG. 6, a plurality of external pad patterns are formed on the substrate 200 202a, whose material is, for example, copper (Copp er, Cu). Among them, the method for forming the external pad pattern 202a is, for example, lithography and etching, as shown in FIGS. 3 to 5. As shown in FIG. 3, an external pad 202 is laminated on the substrate 200. For example, it is copper foil. As shown in FIG. 4, a patterned photoresist layer 201 is formed on the outer pad layer 202, and a part of the outer pad layer 202 is exposed. The method for forming the patterned photoresist layer 201 is as an example. The language includes laser film removal, exposure, and development. Then, as shown in FIG. 5, the exposed pad layer 202 is removed to obtain a plurality of pad patterns 202a. The method of removing the pad pattern 202 is, for example, etching. Finally, the patterned photoresist layer 201 is removed to obtain the structure shown in FIG. 6. As shown in FIG. 7, a copper plating layer 204 is comprehensively formed on the surface of the substrate 200 and the external pad pattern 202a. Among them, The material of the copper plating layer 204 is, for example, chemical copper deposited by a redox reaction. Then, as shown in FIG. 9, a patterned photoresist layer 206a is formed on the copper plating layer 204. Among them, the patterned photoresist layer 206a is formed. The method is shown in Figures 8 to 9. As shown in Figure 8, first form Photoresist layer 206 is mounted on 7 of copper plating layer 204! (Please read the precautions on the back before filling this page) Order · — nnnn I 丨 m This paper size applies to Chinese national standards (CNS> A1 specification (2Η) χ297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 503676 V. Description of Invention). Next, as shown in FIG. 9, the photoresist layer 206 is patterned to form a plurality of openings 207 ′ so that a portion of the copper plating layer 204 on the external pad pattern 202 a can be exposed through the openings 207 of the patterned photoresist layer 206 a. Out. Each opening 207 corresponds to each external pad pattern 202a. The method of patterning the photoresist layer 206 is, for example, laser film removal, or photography and development. Here, in the process of patterning the photoresist layer 206, although the openings 207 formed there may also be slightly inclined inward contraction, compared to the conventional pattern masking layer (as shown in Figure 2). Step 112 is to form the opening 112a. The shrinkage of the opening 207 of the patterned photoresist layer 206a is obviously much smaller (as shown in FIG. 9), and the effect of this tilt can be ignored to form the hole wall and the substrate 200. The surface is almost vertical opening 207. As shown in FIG. 10, the opening 207 is filled to form a guide pillar layer 20g. The method for forming the guide pillar layer 208 can, for example, use copper plating layer 204 as a seed layer, fill the opening 207 with electroplated copper or sputtering, or print in or dip ( For example, a high-temperature dry film is used to cover the part that does not need to be penetrated, and then it is immersed in the molten metal material) to form the guide pillar layer 208. Then, as shown in FIG. 11, the photoresist layer 20 is removed and the pillar layer 208 and a part of the copper plating layer 204 are exposed. As shown in Fig. Π ', the portion of the copper plating layer 204a which is not covered by the pillar layer 208 and is exposed is removed to avoid unnecessary electrical conduction. The copper ore layer 204, the guide pillar layer 208, and the circumscribing layer ^ 2a are used to form the circumscribing pad 214 having a similar columnar structure. Among them, the method of removing the copper plating layer 204 is, for example, Flash Etching. Since the copper ore layer 204, this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) illl · ! — — — — — — Aw * II 1 II l I ^ * II (Please read the note on the back? Matters before filling out this page} Line ,. 5 ___ Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 503676 8306twf .doc / 006 A 7 Description of the invention (The thickness of rp is much smaller than the thickness of the external pad pattern 202a and the guide pillar layer 208. Therefore, removing the copper plating layer 204 by means of rapid engraving will not damage the external pad pattern 202a and the pillar layer 208. As shown in FIG. 13, a solder mask layer 212 is comprehensively formed on the surface of the substrate 200, the external pad pattern 202a, and the pillar layer 208, and the material of the solder mask layer 212 For example, it is a solder mask or other dielectric material similar to the solder mask. As shown in FIG. 14, a part of the solder mask 212 is removed so that the solder mask 212 a and The external pad 214 is the same height, and the external pad 214 is exposed. Among them, a method of removing a part of the solder resist layer 212 Including honing or removing a part of the solder resist layer by chemical dissolution. According to the features of the present invention, the patterned photoresist layer 206a can form an opening 207 with a hole wall almost perpendicular to the surface of the substrate 200. After the external pad 214 is formed, a solder resist layer 212 is formed on the surface of the external pad 214 and the substrate 200, and a part of the solder resist layer 212 is removed to expose the external pad 214. Therefore, the present invention can effectively utilize the exposed pad 214. The area of the external pad 214 further improves the area use efficiency of the substrate 200. In addition, the present invention can avoid the problem of unclean development of the solder resist layer, thereby improving the yield rate of the process. According to the features of the present invention, the same reason as above, so It can greatly reduce the effect of the conventional (such as FIG. 2) solder mask 112 being limited by the development process, so that the opening 112a of the solder mask Π2 is inclined and retracted. Therefore, the external pad 214 of the present invention is exposed. The process variability is small, and the area where the external pad 214 is exposed can be easily controlled. According to the features of the present invention, because the external pad 214 and the solder resist layer 212a are located in the same 9 nnnnnn ϋ ϋ ϋ ni * β, β e. ▲ (Please read first Back of Note: Please fill in this page again.) This paper size applies to China National Standard (CNS) AI specification (210x 297 mm) 503676
五、發明說明（g) 經濟部智慧財產局員工消費合作社印製 Τ'® ’對於後續的製程例如將晶片與基板連接時的打線步 Μ ’或是將覆晶晶片的凸塊與基板連接時的接合步驟，其 處理皆較爲容易。 綜上所述，本發明之基板外接墊的製作方法具有下 列優點： (1) 本發明之基板外接墊的製作方法，因外接墊和防銲層同 ’後續製程之處理較容易（例如將晶片與基板連接 _的打線步驟，或是將覆晶晶片的凸塊與基板連接時的 接合步驟）。 (2) 本發明之基板外接墊的製作方法，可充分利用暴露出之 #接墊面積，進而可提高基板之面積使用效率。 (3) 本發明之基板外接墊的製作方法，因可充份減少習知受 1¾銲層開口呈傾斜式縮小的影響，故可減少暴露出外接 m製程的變異性，而使得暴露出外接墊之面積容易控 制。 (4) 本發明之基板外接墊的製作方法，可避免習知防銲層顯 影不潔的問題點，可提高製程良率。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 1 0 ^— I—,—.—丨 裝 i I 丨 (請先閲讀背面之注意事項再填寫本頁) ft— ϋ· n mm— 訂丨！-線 本紙張尺度適用中國國家標準（CNS)/Vi規格（2]0 x 297公釐）V. Description of the invention (g) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs “T'®” For subsequent processes such as the wire bonding step M when connecting the wafer to the substrate or the bump of the flip-chip wafer to the substrate The joining steps are easy to handle. In summary, the method for manufacturing an external pad of a substrate of the present invention has the following advantages: (1) The method for manufacturing an external pad of a substrate of the present invention, because the external pad and the solder resist layer are easier to process in subsequent processes (such as the wafer A step of connecting the substrate to the substrate, or a bonding step of connecting the bump of the flip-chip wafer to the substrate). (2) The method for manufacturing an external pad of a substrate according to the present invention can make full use of the exposed #pad area, thereby improving the area efficiency of the substrate. (3) The manufacturing method of the substrate external pad of the present invention can sufficiently reduce the influence of the conventional 1¾ solder layer opening in an oblique manner, so that the variability of the external m process can be reduced, and the external pad can be exposed. The area is easy to control. (4) The method for manufacturing an external pad of a substrate according to the present invention can avoid the problem of uncleanness of the solder mask, and can improve the process yield. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 1 0 ^ — I —, —.— 丨 Install i I 丨 (Please read the precautions on the back before filling this page) ft— ϋ · n mm— Order 丨! -Line This paper size applies to Chinese National Standard (CNS) / Vi specifications (2) 0 x 297 mm