^12482 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（1) 本發明之簌圊 一般而言，本發明係關於積體電路，及特別是關於積體 電路中之淺溝隔離。 本發明之背景 、淺溝隔離（STI)與化學機械磨光（CMP)結合成爲用於〇·2微 米裝置及更小者之重要隔離計劃。此種技藝提供縮小能力 (scalability)及平面構形作爲其優點。典型之STI方法包括 在基體上形成一襯墊氧化物層，接者形成一氮化物層。於 一圖型I光阻蝕刻在該氮化物層上形成之後，對該氮化物 層，襯塾氧化物層及基體施行蝕刻。此圖型之光阻蝕刻包 括相當於各隔離區域之窗，然後作氧化物層之覆蓋沉積， 俾於已移除該光阻蝕刻之後填塞各隔離區域。 孩覆蓋沉積形成在各溝中及非挖溝區域内之氧化物。因 此必須使用某種平面化程序以完成名義上之平坦頂部表 面。但此項技術患於局部之磨光率變動以及凹狀扭曲與氧 化物殘渣有關之問題。此等變更通常可由局部圖型密度中 <改變及在CMP期間以不同之速率對不同之材料蚀刻所造 成。 圖型密度係指積體電路構形中之變更，局部之CMp速率 殊視附近各溝之圖形密度而定。此種圖型變更所導致之問 滅爲在低圖型密度區域中之，，凹狀扭曲”（dishing)。 減y此等問遞之方法馬提供相反狀態（reverse tone)氧 化物蚀刻以增進CMP之均勻一致。在此狀況中，一圖型之 光阻蚀刻被开> 成於氧化物層上，其中該圖型相當於圖型之 -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ·裝--------訂-1 (請先閱讀背面之注意事項再填寫本頁) n n n 512482 A7 B7 五、發明說明（2 ) 相反狀恐以形成各溝。將該衰仆 ，專將泛虱化物層蝕刻以減少形成於神 二溝：域二氣化物數量。因爲需有一另加之石印術步 ^ 〈成本增加。又由於補償及重合爭點，此方法 乃不易概略估計。 万^ 另一万式可將”假裝填”（dummy fin)圖型加於用以界定光 阻钱刻中各溝之光罩。此假裝填圖形將橫過_基體之圖型 被度〈變更減至最少。不過，對不同積體電路之甚多種類 〈假裝填圖型之設計，可大爲增加該光罩之複雜性與成 本。因此所希望在爲具有—種能產生平面化特色而無C⑽ 缺點之方法〇 本發明之概要 本發明係關於製造一種包含淺溝隔離（STI)區域之積體電 路 < 方法。孩方法包括提供一種含有一材料層及各淺溝之 基體。一絕緣層係形成於該材料層上及各淺溝中，該絕緣 層之一部份被移除以暴露設有溝之隔離層。其後，使用提 起法除去在該材料層上形成之絕緣層以完成各淺溝隔離區 域。結果，可形成平面化之各淺溝隔離區域而不必使用化 學機械磨光（CMP)。因此能避免與CMP有關之各問題。 經濟部智慧財產局員工消費合作社印製 應瞭解者上列之一般性説明與下文之詳細説明均係作爲 本發明之範例而非用以限制者。 曼式之簡單説明 當與所附各圖連同閲讀時，可從下列之詳細説明對本發 明有最佳之瞭解，應強調在根據半導體工業之共通作業， 附圖之各項不同特點並不按比例尺縮小，與此相反，各特 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 第089113098號專利申請案 中文說明書修正^ 五、發明説明（3 鉍《尺寸乃係任意擴大或減縮以資清晰附圖 為下列各圖： 圖1 a為用以根據本發明之第一說明實例形成淺溝隔離區 域之流程圖： 圖1 b為用以根據本發明之第二說明實例形成淺溝隔離區 域之流程圖； 圖2-8為例示根據圖lb中所示之方法製造一積體電路之 各略圖； 、圖9為根據本發明之第三說明實例形成淺溝隔離區域之 流程圖；及 圖1 0 - 1 2為說明根據圖9中所示之方法製造一積體電路 之各略圖。 明之詳細說明 簡言4，本發明係關於製造一種包含淺溝隔離（sti)區域 之積體電路之方法，如圖丨a中所示者，該方法包括步騾 1，k供含有一材料層及淺溝之一基體。步驟2，形成一絕 、’彖層杰S材料層上及各淺溝中。該絕緣層之一部份在步驟 3中被移除以曝露設有淺溝之隔離層其後在步騾4中使用提 起法除去在該材料層上形成之絕緣層以完成各淺溝隔離區 域。結果能形成變為平面之各淺溝隔離區域而不必使用化 學機械磨光（CMP)，因此可避免與CMp有關之各問題。 圖lb為舉例說明根據本發明製造淺溝隔離（STI)—區域之 另一方法之流程圖。茲參照顯示在製造連續步驟中之一積 體電路之圖2 - 8敘述圖1 b中所示方法如下列。 ~ 6 - 本紙張尺度適财S S家鮮(CNS) A4規格(2igx挪公复) 經濟部智慧財產局員工消費合作社印製 512482 Α7 __Β7 五、發明說明（4) 在步驟1 0，將一材料層110形成於基體100上，舉例而言 該基體乃係例如娃，鎵神，娃鍺或其他已知半導體材料之 一半導體，一種襯塾氧化物105可形成於該材料層Π0與基 體100之間。該襯墊氧化物105可予以熱成長並係例如 Si〇2，該襯墊氧化物之厚度X 1為例如丨⑽又至2〇〇又或約為 15〇a。 當曝露於至少一種共用之蝕刻劑時，可選擇該材料層 11 0以較其後形成之絕緣層13 0為快之速度姓刻之。例如絕 緣層110乃抵抗第一種姓刻劑之姓刻而材料層丨1 〇，則對第 一種蝕刻劑較少抗拒。換言之，當曝露於第一種蝕刻劑 時，材料層110係以較絕緣層13〇為快之速度蝕刻。又，亦 可選擇材料層Π0使其作用如同使用於淺溝115形成之堅固 掩蔽。舉例而言，該蝕刻方法係一種溼化學蝕刻，該材料 層110之厚度X2為例如15〇〇又至2〇〇〇又或約為丨7^又。 在一舉例說明之實例中，材料層110包含SiN，絕緣層 130包含高密度電漿（HDP)氧化物及蝕刻劑包含熱磷酸，該 SiN及HDP氧化物係用熟知之技術形成。可替用者，材料層 110可為聚娃及蝕刻劑可為氨氫氧化物（ΝΗ4〇η)。 在步驟20中，將設有圖型之掩蔽層120形成於該材料層 110上。例如設有圖形之掩蔽層12〇係以光致抗蝕劑形成及 使用傳統之石印技術加上圖型。在步驟3 0中，使用傳統之 姓刻技術姓刻材料層η 〇及基體1 〇〇以形成各溝丨丨5。如有 襯墊氧化物105存在亦可施以蝕刻，在步騾4〇中，使用熟 知之方法除去設有圖型之掩蔽層1 20及清洗基體。然後 -----r---^--------- (請先閱讀背面之注意事項再填寫本頁) 巧張尺度適財_家標準（CNS)A4規格⑽χ 297^爱） 512482 A7^ 12482 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) The invention is generally related to integrated circuits, and in particular shallow trench isolation in integrated circuits . BACKGROUND OF THE INVENTION The combination of shallow trench isolation (STI) and chemical mechanical polishing (CMP) has become an important isolation plan for 0.2 micron devices and smaller. This technique provides scalability and planar configuration as its advantages. A typical STI method includes forming a pad oxide layer on a substrate, and then forming a nitride layer. After a pattern I photoresist is formed on the nitride layer, the nitride layer, the lining oxide layer, and the substrate are etched. The photoresist etch of this pattern includes a window corresponding to each of the isolation regions, and then is covered with an oxide layer to deposit and fill the isolation regions after the photoresist etch has been removed. The oxides formed in the trenches and in the non-trenched areas are covered by the deposits. Therefore, some flattening procedure must be used to complete the nominally flat top surface. However, this technique suffers from problems with local polishing changes and concave distortions related to oxide residues. Such changes are usually caused by < changes in local pattern density and etching of different materials at different rates during CMP. The pattern density refers to the change in the configuration of the integrated circuit. The local CMP rate depends on the pattern density of the nearby trenches. The problem caused by this pattern change is in the low-pattern density area, concave distortion "(dishing). Subtract these methods to provide reverse tone oxide etching to improve The uniformity of CMP. In this situation, a pattern of photoresist etching is opened on the oxide layer, where the pattern is equivalent to -4 of the pattern-This paper size applies to the Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) · Install -------- Order-1 (Please read the precautions on the back before filling this page) nnn 512482 A7 B7 V. Description of the invention Formation of various trenches. The fading layer was specifically etched to reduce the amount of gaseous compounds formed in Shen Ergou: Domain II. Because of the need for an additional lithography step ^ <cost increase. Also due to compensation and overlap This method is not easy to estimate roughly. 10,000 ^ Another 10,000 type can add a "dummy fin" pattern to the mask used to define the grooves in the photoresist engraving. This fake filling pattern will cross _The pattern of the substrate is reduced to a minimum. However, there are many types of circuits for different integrated circuits. <The design of the fake filling pattern can greatly increase the complexity and cost of the photomask. Therefore, it is desirable to have a method that can generate planarization characteristics without C⑽ disadvantages. SUMMARY OF THE INVENTION The present invention is about manufacturing An integrated circuit < method including a shallow trench isolation (STI) region. The method includes providing a substrate including a material layer and each shallow trench. An insulating layer is formed on the material layer and in each shallow trench. A part of the insulating layer is removed to expose the trench-isolated layer. Thereafter, the insulating layer formed on the material layer is removed using a lift method to complete each shallow trench isolation area. As a result, planarized sections can be formed. Shallow trenches isolate the area without the use of chemical mechanical polishing (CMP). Therefore, problems related to CMP can be avoided. The general descriptions listed above and the detailed descriptions below should be printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is intended as an example of the present invention and is not intended to limit it. The simple description of Mann, when read in conjunction with the accompanying drawings, can best understand the present invention from the following detailed description, It should be emphasized that according to the common operation of the semiconductor industry, the different characteristics of the drawings are not scaled down. On the contrary, each special paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Article 089113098 Amendment to the Chinese Specification for Patent Application No. ^ V. Description of the invention (3 Bismuth "Dimensions are arbitrarily enlarged or reduced for clarity. The drawings are as follows: Figure 1a is used to form a shallow trench according to the first illustrative example of the present invention Flowchart of the isolation area: Figure 1b is a flow chart for forming a shallow trench isolation area according to the second illustrative example of the present invention; Figures 2-8 are examples illustrating the fabrication of an integrated circuit according to the method shown in Figure lb 9; FIG. 9 is a flowchart of forming a shallow trench isolation region according to a third illustrative example of the present invention; and FIGS. 10 to 12 are schematic diagrams illustrating fabrication of an integrated circuit according to the method shown in FIG. The detailed description of the brief is brief 4. The present invention relates to a method for manufacturing an integrated circuit including a shallow trench isolation (sti) area, as shown in FIG. And one of the shallow grooves. In step 2, a layer of a material is formed on each of the shallow trenches. A part of the insulating layer is removed in step 3 to expose the isolation layer provided with shallow trenches, and then the insulating layer formed on the material layer is removed in step 4 using a lift method to complete each shallow trench isolation area. . As a result, the shallow trench isolation regions that become planar can be formed without using chemical mechanical polishing (CMP), and thus various problems related to CMP can be avoided. FIG. 1b is a flowchart illustrating another method of manufacturing a shallow trench isolation (STI) -area according to the present invention. The method shown in Fig. 1b is described below with reference to Figs. 2-8 showing an integrated circuit in one of the successive steps of manufacturing. ~ 6-This paper is suitable for SS Home Fresh (CNS) A4 size (2igx). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 512482 Α7 __Β7 V. Description of the invention (4) In step 10, a material The layer 110 is formed on the substrate 100. For example, the substrate is a semiconductor such as silicon, gallium, silicon germanium, or other known semiconductor materials. A hafnium oxide 105 may be formed on the material layer Π0 and the substrate 100. between. The pad oxide 105 can be thermally grown and is, for example, SiO 2, and the thickness X 1 of the pad oxide is, for example, ⑽ to 200 or about 150 a. When exposed to at least one common etchant, the material layer 110 can be selected to be engraved at a faster rate than the insulating layer 130 formed thereafter. For example, the insulating layer 110 is resistant to the first type of engraving agent and the material layer is less resistant to the first type of etchant. In other words, when exposed to the first etchant, the material layer 110 is etched at a faster rate than the insulating layer 130. Alternatively, the material layer Π0 can be selected to function as a strong mask for the shallow trench 115 formation. For example, the etching method is a wet chemical etching, and the thickness X2 of the material layer 110 is, for example, 15,000 to 2000, or about 7 mm. In an illustrative example, the material layer 110 includes SiN, the insulating layer 130 includes high-density plasma (HDP) oxide, and the etchant includes thermal phosphoric acid. The SiN and HDP oxide are formed using well-known techniques. Alternatively, the material layer 110 may be polysilicon and the etchant may be ammonia hydroxide (N （4η). In step 20, a patterned masking layer 120 is formed on the material layer 110. For example, a patterned masking layer 120 is formed using a photoresist and patterned using conventional lithographic techniques. In step 30, the material layer η 〇 and the substrate 100 are engraved using a conventional surname engraving technique to form each groove 5. If the pad oxide 105 is present, etching can be applied. In step 40, the masking layer 120 and the substrate provided with the pattern are removed by a known method. Then ----- r --- ^ --------- (Please read the notes on the back before filling out this page) Kojima scales are suitable for wealth_CNS A4 specifications ⑽χ 297 ^ 爱) 512482 A7
(請先閲讀背面之注意事項再填寫本頁) ί =中’將絕緣層13G形成於材料層U0上及各溝115 135。/二用於絕緣層130之材料及沉積方法使變薄之區域 二=成D此外’亦可選擇沉積法，俾使溝115被充塞 以〉儿積义物料。 A =例不足万法為高密度電漿（HD^氧化物以空隙填塞 杈^儿積。1999年2月16日頒佈之美國專利案第5,872,〇58 號發，名稱為使用HDP之高縱橫空隙填塞法者敛述使用空 隙，、▲步4iA a積氧化物之此種方法。該專利案係併列於此 以供參考。絕緣層π〇之厚度χ3為例如4〇〇〇又至5〇〇〇又或約 為 4 5 0 0 a。 在步驟60中，將絕緣層13〇蝕刻以曝露材料層ιι〇之一部 份。步驟6 0可為單一蝕刻或複式蝕刻過程。例如絕緣層 130可用各向異性蝕刻施以覆蓋蝕刻，該各向異性蝕刻乃 以選擇方式蝕刻非平面之區域者，其後，使用稀釋（丨〇〇 :工) 之HF姓刻法餘刻絕緣層丨3 〇。此兩步驟之過程移除變薄之 區域135及曝露材料層110之各區域125。另一方式，可單 獨使用覆蓋各向異性蚀刻或H F I虫刻以曝露區域12 5。絕緣 層13〇之約200又至3〇〇又，在步驟6〇中被移除。 經濟部智慧財產局員工消費合作社印製 在步驟7 0中，使用對材料層11 〇具有高選擇性之一種蝕 刻劑作蝕刻之用。材料層110可包括SiN並可使用熱磷酸蝕 刻之。圖8例示使用上述方法形成之隔離區域丨4〇。在襯墊 氧化物上之隔離區域14〇之階高可為200又至1〇〇〇又及隔離 區域之總厚度X5可為35〇0又至4〇〇〇又該襯墊氧化物1〇5在步 驟7 0實施之蝕刻過程中對基體中之作用區1 〇5提供保護。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 512482 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 在步驟8 0中，使用熟知之各方法完成積體電路。例如將 各裝置形成於基體中，及形成其後之導電及電介質層以產 ^ 一芫整之積體電路。所述裝置及此等裝置之互連乃視所 製造之特定積體電路而定。 圖9為本發明之一替用具體實例之流程圖。此實例與圖 1 b中所不之實例相同，唯已加入步驟55，57及59及修正步 4 6 0知參照圖1 0 - 1 1敘述圖9中所示方法如下列。圖 10-11乃顯示在製造之連續步驟中之一積體電路者。 在步風55中，一掩蔽層15〇係形成於絕緣層13〇上。掩蔽 層150<形成乃用以在於爾後蝕刻中保護各溝ιΐ5中形成之 、巴、彖層13 0之各邵份。此掩蔽層1 5 0係例如設有圖型之光阻 蚀刻層’在步驟57中，將絕緣層130蝕刻以曝露材料層 U〇 ’及在步驟59中將掩蔽層從該基體移除。在步驟 中，將絕緣層13〇蝕刻以曝露區域16〇及從區域17〇除去剩 下义物料，以此方法可使材料層11〇之較大區域曝露及其 後在步驟7 〇中被蝕刻。該積體電路遂如上文所述者予以完 成及顯示於圖9中。 一在另一選替實例中，可使用假填塞圖型於圖，比及9所 不 < 万法中。於此狀況中，假填塞圖型可包括在不需要隔 離區或之範圍中各溝之形成。結果，各隔離區域可能橫過晶 片形成而使橫過晶片之隔離區域之圖型密度更為一致。 雖；、、：本發明已參照各示範實例予以敛述，但並不受限於 此等實例，而且所附之申請專利範圍應解釋為包括本發= <其=變體與實例及此等變體與實例乃可由熟諳本技藝者 在不背離本發明之真正精神與範圍下完成者。 本紙張尺度適财規格⑽X 297公餐） — Lli.---.----·裝-------訂--------- (請先閲讀背面之注意事項再填寫本頁) 512482 第089113098號專利申請案 A 中文說明書修正頁(91年6月V 6. 2J —g 五、發明説明（6a ) 圖式元件符號說明 100 基體 105 襯墊氧化物 110 材料層 115 淺溝 120 設有圖形之掩蔽層 125 曝露區域 130 絕緣層 135 變薄之區域 - 140 隔離區域 150 掩蔽層 160 曝露區域 170 區域 -93 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐）(Please read the precautions on the back before filling this page) ί = 中 ’The insulating layer 13G is formed on the material layer U0 and each groove 115 135. / Second, the material used for the insulating layer 130 and the deposition method to make the area thinner. Second = into D. In addition, the deposition method can also be selected, so that the trench 115 is stuffed with the material. A = case is less than 10 million methods for high-density plasma (HD ^ oxide fills the branch with voids ^ product. Issued in the United States Patent No. 5,872, 058 issued on February 16, 1999, the use of high-definition HDP The gap-filling method converges on the method of using voids and ▲ step 4iA a to accumulate oxides. The patent case is listed here for reference. The thickness χ3 of the insulating layer π is, for example, 4,000 to 5 〇〇 or about 4 500 a. In step 60, the insulating layer 130 is etched to expose a part of the material layer ιι. Step 60 can be a single etching or multiple etching process. For example, the insulating layer 130 Anisotropic etching can be used to cover the etching. The anisotropic etching is used to etch non-planar areas in a selective manner. Thereafter, the insulating layer is etched using the diluted HF surname etch method (3). The two-step process removes the thinned areas 135 and the exposed areas 125 of each area 125. Alternatively, anisotropic etching or HFI etch can be used alone to expose the area 12 5. The insulating layer 13 About 200 to 300 again, was removed in step 60. Ministry of Economy Wisdom Printed by the production bureau employee consumer cooperative in step 70, an etchant having a high selectivity to the material layer 110 is used for etching. The material layer 110 may include SiN and may be etched using hot phosphoric acid. Figure 8 illustrates the use of The isolation region formed by the above method is 40. The step height of the isolation region 14 on the pad oxide may be 200 to 1,000, and the total thickness of the isolation region X5 may be 350,000 to 4. 〇〇The pad oxide 105 protects the active area 105 in the substrate during the etching process carried out in step 70. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 512482 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (In step 80, complete the integrated circuit using well-known methods. For example, forming each device in the substrate and forming the subsequent conductivity And dielectric layer to produce integrated integrated circuits. The devices and interconnections of these devices depend on the specific integrated circuits that are manufactured. Figure 9 is a flow chart of an alternative embodiment of the present invention. This example is similar to what is shown in Figure 1b The example is the same, except that steps 55, 57 and 59 and the correction step 4 6 0 have been added. Referring to Figures 1 0-1 1 the method shown in Figure 9 is as follows. Figures 10-11 are shown in the continuous steps of manufacturing An integrated circuit. In the step 55, a masking layer 150 is formed on the insulating layer 13. The masking layer 150 is formed to protect the layers formed in the trenches 5 in subsequent etching. Each part of 13 0. This masking layer 150 is provided with a patterned photoresist etching layer 'in step 57, the insulating layer 130 is etched to expose the material layer U', and the masking layer is formed in step 59. Remove from the substrate. In the step, the insulating layer 130 is etched to expose the region 160 and the remaining material is removed from the region 170. In this way, a larger area of the material layer 11 can be exposed and subsequently etched in step 70. . The integrated circuit is then completed and shown in Figure 9 as described above. In another alternative example, a pseudo-stuffing pattern may be used in the graph, compared to 9 < Wanfa. In this case, the dummy packing pattern may include the formation of trenches in areas where isolation or areas are not required. As a result, each isolation region may be formed across the wafer to make the pattern density more uniform across the isolation region of the wafer. Although; ,,: The present invention has been described with reference to various exemplary examples, but it is not limited to these examples, and the scope of the attached patent application should be interpreted to include the present invention < 其 = variations and examples and this Variations and examples may be accomplished by those skilled in the art without departing from the true spirit and scope of the invention. This paper is suitable for financial specifications (X 297 meals) — Lli .---.---- · install ------- order --------- (Please read the precautions on the back before Fill out this page) 512482 Patent Application No. 089113098 A Chinese Specification Correction Page (June 91 V 6. 2J —g V. Description of Invention (6a) Symbol Description of Schematic Elements 100 Base 105 Pad Oxide 110 Material Layer 115 Shallow groove 120 Masking layer with pattern 125 Exposed area 130 Insulation layer 135 Thinned area-140 Isolation area 150 Masking layer 160 Exposed area 170 Area-93-This paper size applies to China National Standard (CNS) A4 specifications (210 x 297 mm)