559987 A7 _^B7 五、發明説明（ 發明領域： (請先閲讀背面之注意事項再填寫本頁) 本發明係有關於一種半導體元件之電容器（Capacit〇r) 及其製造方法，特別是有關於一種高介電值（High_k Dielectric)電容器及其製造方法。 發明背景： 隨著電子元件之線寬尺寸的持續縮減，導致其内之電 容器的尺寸也受到限制。為了提供電子元件足夠的電容， 而發展出數種提高電容器之電容的方法。其中的一種方法 係製作出具有三維結構之電容器，藉由提高電容器的高 度，來增加電容器之面積，並藉以提升電容器之電容。另 一種方法則係利用提高介電層之介電常數來達到增加電容 器之電容的目的。 經濟部智慧財產局員工消費合作社印製 請參照第1圖與第2圖，其係繪示習知電容器之製程 剖面圖。首先，提供半導體之基材1〇〇，並於基材1〇〇上 先行製作出元件之閘極1 04、源極丨〇6、汲極丨〇8、以及隔 離層1 02。接著，沉積一層絕緣層i丨〇覆蓋在閘極工〇4、源 極106、汲極108、以及隔離層1〇2上。再利用微影以及蝕 ，_敗技術在源極1 06上方之絕緣層i丨〇中形成接觸窗n 2， 並暴露出源極1 0 6的一部分。接觸窗1 12形成後，沉積一 層導電材料填滿接觸窗1 12並覆蓋在絕緣層丨1()上。再去 除絕緣層110上之導電材料，而在接觸窗112中形成接觸 插塞1 1 4，其中接觸插塞1 1 4係用以提供源極丨06與外界 之電性連接。 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 559987 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（) 接觸插塞 114形成後，沉積一層較厚之複晶矽 (P〇lysilicon)層116覆蓋在絕緣層110以及接觸插塞114 上，用以作為電容器之下電極。其中，當複晶矽層1 1 6具 有較大之厚度時，複晶矽層1 1 6的表面積也會隨之變大， 因此可增加電容器之電容。再沉積一層厚度較薄之阻障層 1 1 8覆蓋在複晶矽層1 1 6上，其中阻障層1 1 8係用以在後 續的製程中阻止氧的擴散。由於，阻障層Π 8具有較薄之 厚度，因此有利於後續阻障層11 8之電漿蝕刻的進行。接 著，沉積一層薄薄的過渡金屬（Transition Metal)層120覆 蓋在阻障層118上。其中，過渡金屬層120之厚度愈薄， 愈有利於電漿|虫刻的進行。再利用微影與蚀刻製程圖案化 過渡金屬層1 2 0、阻障層1 1 8、以及複晶矽層1 1 6 ,而暴露 出部分之絕緣層1 1 〇，並在另一部分之絕緣層1 1 〇以及接 觸插塞1 1 4上形成由依序堆疊之複晶石夕層1 1 6、阻障層 1 1 8、以及過渡金屬層1 2 0所構成之儲存節點1 2 2。 儲存節點1 22形成後，沉積一層阻障金屬材料覆蓋在 儲存節點1 2 2以及絕緣層1 1 0上。再對此層阻障金屬材料 進行回蝕刻（EtchingBack)步驟，藉以去除部分之阻障金屬 材料’並暴露出部分之過渡金屬層1 2 0以及絕緣層1 1 〇， 而在儲存節點1 22之側壁上形成阻障金屬間隙壁1 24。接 著’沉積過渡金屬材料覆蓋在儲存節點1 2 2、阻障金屬間 隙壁124、以及絕緣層1 10上。再回蝕刻所沉積之過渡金 屬材料’藉以去除此過渡金屬材料的一部分，並暴露出部 1紙張尺度適用中國國家標準(CNS)A4規格(210X 297公楚）------- (請先閲讀背面之注意事項再填寫本頁} #· 、一一-口 線一 五、發明説明（） 分之過渡金屬層】 i2〇以及絕緣層1 10，而在儲存節點i 側壁之阻障金屬間隙壁124上形成過渡金屬間隙壁126, 成-構如第丨圖所示。纟中，阻障金屬 以及阻障層！ 18係田、 、土 ’、以作為防止複晶矽層1 1 6之複晶石夕好 料氧化的阻障結構。 ⑬阳石夕材559987 A7 _ ^ B7 V. Description of the invention (Field of the invention: (Please read the precautions on the back before filling out this page) The present invention relates to a capacitor of a semiconductor element (Capacit〇r) and its manufacturing method, especially related to A high-k Dielectric capacitor and a method for manufacturing the same. BACKGROUND OF THE INVENTION: As the line width of electronic components continues to shrink, the size of capacitors within them is also limited. In order to provide sufficient capacitance for electronic components, Several methods have been developed to increase the capacitance of capacitors. One of them is to make a capacitor with a three-dimensional structure. By increasing the height of the capacitor, the area of the capacitor is increased and the capacitance of the capacitor is increased. The other method is to use Increase the dielectric constant of the dielectric layer to achieve the purpose of increasing the capacitance of the capacitor. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 1 and Figure 2, which are cross-sectional views showing the process of a conventional capacitor. First , Provide semiconductor substrate 100, and first make the device gate 10 on the substrate 100 4. Source 丨 〇6, Drain 丨 08, and Isolation Layer 102. Then, an insulating layer i 丨 is deposited to cover gate electrode 04, source 106, drain 108, and isolation layer 10. 2. The photolithography and etching are used again to form a contact window n 2 in the insulating layer i 丨 above the source electrode 106, and a part of the source electrode 106 is exposed. After the contact window 112 is formed, A layer of conductive material is deposited to fill the contact window 112 and cover the insulating layer 1 (). Then the conductive material on the insulating layer 110 is removed, and a contact plug 1 1 4 is formed in the contact window 112, where the contact plug 1 1 4 is used to provide source 丨 06 electrical connection with the outside world. This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 559987 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the invention () After the contact plug 114 is formed, a thicker polysilicon layer 116 is deposited on the insulating layer 110 and the contact plug 114 to serve as the lower electrode of the capacitor. When the crystalline silicon layer 1 1 6 has a large thickness, the surface area of the polycrystalline silicon layer 1 1 6 also varies with It becomes larger, so the capacitance of the capacitor can be increased. A thinner barrier layer 1 1 8 is deposited on the polycrystalline silicon layer 1 1 6, wherein the barrier layer 1 1 8 is used to prevent it in subsequent processes. Diffusion of oxygen. Because the barrier layer Π 8 has a thinner thickness, it is beneficial to the subsequent plasma etching of the barrier layer 118. Then, a thin transition metal layer 120 is deposited to cover On the barrier layer 118. Among them, the thinner the thickness of the transition metal layer 120 is, the more favorable it is to carry out the plasma | worming. The photolithography and etching processes are then used to pattern the transition metal layer 120, the barrier layer 1 18, and the polycrystalline silicon layer 1 16 to expose a part of the insulating layer 1 10, and the other part of the insulating layer A storage node 1 2 2 composed of a polycrystalline spar layer 1 16, a barrier layer 1 1 8, and a transition metal layer 1 2 0 is sequentially formed on the contact plug 1 1 4 and the contact plug 1 1 4. After the storage node 12 is formed, a barrier metal material is deposited to cover the storage node 12 and the insulating layer 110. This layer of barrier metal material is then etched back (EtchingBack) step, so as to remove part of the barrier metal material 'and expose part of the transition metal layer 1 2 0 and the insulating layer 1 1 0, and in the storage node 1 22 Barrier metal spacers 124 are formed on the side walls. Next, the depositing transition metal material covers the storage node 1 2 2, the barrier metal gap wall 124, and the insulating layer 1 10. Then etch back the deposited transition metal material 'to remove a part of this transition metal material and expose the paper size of the Ministry of Standards 1 to China National Standards (CNS) A4 (210X 297 Gongchu) ------- (Please Read the precautions on the back before filling in this page} # · ， 一一-口 线 15 ， Description of the invention () Transition metal layer] i2〇 and insulating layer 1 10, and the barrier metal on the side of the storage node i A transition metal spacer 126 is formed on the barrier wall 124, and the structure is as shown in the figure. In the figure, the barrier metal and the barrier layer! 18 series of fields, and soil, to prevent the polycrystalline silicon layer 1 1 6 The barrier structure of polycrystalline stone Xixi good oxidation.
完成儲存節點】9。 H 層128芦蓋，針 &阻P早結構後’沉積高介電值材料 曰 復在儲存節點122、過渡金屬間隙壁126、 緣層11。上。再沉積上電極13。覆蓋在高介 ; 1。然後·去除部分之高介電值材…8以及上電極 並暴路出部分之絕緣層110 ’而完成電容器的製作， 所形成之電容器結構如第2圖所示。 由於，高介電值材料之氧原子極易擴散至複晶石夕中， 並與複晶石夕反應’而在高介電值材料與複晶石夕的介面間產 生介電常數較低的氧化薄膜’進而影響電容器之電容。因 此’需在高介電值材料们28與複晶矽層116之間 提供由阻障金屬間隙壁124以及阻障& ! 18所組成之 曰曰 結構’來阻止高介電值材料層128中之氧原子擴散至複 矽層1 1 6中。 發明目的及概述： ’所產生 層阻障結 下降以及 雲於習知利用複晶矽來當作電容器之電極時 之電容不敷使用。又，習知高介電值電容器需多 構，而造成製程過於繁雜，進而導致製程可靠产 成本上升。 4 559987 A7 '發明說明（) 值電，本發明的主要目的之-就是在提供-種高介電 屑。“，本發明之高介電值電容器不需額外的阻障金屬 因此’製程簡單’除了可提高製程可靠度與良率外， 灵可有效減低製造成本。 本發明之再一目的就是在提供一種高介電值電容器之 &方法，其係利用過渡金屬將電容器之堆疊式料節點 包覆。如此-來’高介電值材料層可直接形成於儲存 即^上，並不會產生高介電值材料層之氧擴散問題。因此， 電容器的電性品質可獲得提升。 根據以上所述之主要目的，本發明更提供了一種古八 :值電容器’至少包括：一介電層位於一基材上，其：:: μ電層至少包括一接觸插塞位於上述之基材的一部分上； 一儲存節點位於該接觸插塞以及部分之該介電層上，其中 此儲存節點至少包括依序堆疊之一第一金屬層、一模型層 (Dummy Layer)、以及一第二金屬層；複數個間隙壁覆蓋在 上述之儲存節點之側壁上；一高介電值材料層覆蓋在上述 之儲存節點、間隙壁、以及介電層之另一部分上；以及二 第三金屬層位於上述之高介電值材料層上。 根據本發明之再一目的，本發明更提供了一種高介電 值電容器之製造方法，至少包括：形成一介電層覆蓋在一 基材上，其中此介電層至少包括·一接觸插塞位於上述之基 材的一部分上；形成一儲存節點覆蓋在上述之接觸插塞以 及介電層之一部分上，其中此儲存節點至少包括依序堆疊 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐） (請先閲讀背面之注意事項再填、寫本頁} #· 線一 經濟部智慧財產局員工消費合作社印製 559987 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 之一第一金屬層、Complete the storage node] 9. The H layer is covered with 128 reeds, and a high dielectric material is deposited after the pin & P resistive structure is deposited on the storage node 122, the transition metal spacer 126, and the edge layer 11. on. Furthermore, the upper electrode 13 is deposited. Covered in Takasuke; 1. Then, remove some of the high dielectric material ... 8 and the upper electrode and blow out the insulating layer 110 'of the part to complete the production of the capacitor. The structure of the capacitor is shown in Figure 2. Because the oxygen atoms of the high dielectric material easily diffuse into the polycrystalline stone and react with the polycrystalline stone, a low dielectric constant is generated between the interface of the high dielectric material and the polycrystalline stone. The oxide film 'further affects the capacitance of the capacitor. Therefore, it is necessary to provide a high-k material layer 128 between the high-k material 28 and the polycrystalline silicon layer 116 by a barrier metal spacer 124 and a barrier &! 18 structure. The oxygen atoms in it diffuse into the complex silicon layer 1 16. The purpose and summary of the invention: The layer barrier junction generated by ’decreases and the capacitance is insufficient when Yun Yu is familiar with using polycrystalline silicon as an electrode of a capacitor. In addition, it is known that high-dielectric capacitors need to be multi-structured, which results in too complicated a process, which leads to an increase in reliable production cost. 4 559987 A7 'Explanation of the invention () Value of electricity, the main purpose of the present invention-is to provide-a high dielectric chip. "The high-dielectric value capacitor of the present invention does not require additional barrier metals, so the 'simple process' can improve the reliability and yield of the process, and can effectively reduce the manufacturing cost. Another object of the present invention is to provide a The & method for high-dielectric value capacitors is to use a transition metal to cover the stacked material nodes of the capacitor. In this way, a high-dielectric material layer can be directly formed on storage, and no high-dielectric The problem of oxygen diffusion of the electrical value material layer. Therefore, the electrical quality of the capacitor can be improved. According to the main purpose described above, the present invention further provides an ancient eight: value capacitor 'at least includes: a dielectric layer on a base On the material, the :: electrical layer includes at least a contact plug on a part of the above-mentioned substrate; a storage node on the contact plug and a portion of the dielectric layer, wherein the storage node includes at least a sequence One of the first metal layer, a dummy layer, and a second metal layer; a plurality of spacers cover the side walls of the storage node; a high dielectric material Covering the storage node, the spacer, and another portion of the dielectric layer; and the second and third metal layers are located on the high-dielectric material layer. According to another object of the present invention, the present invention further provides a A method for manufacturing a high-dielectric capacitor includes at least: forming a dielectric layer overlying a substrate, wherein the dielectric layer includes at least a contact plug on a part of the above-mentioned substrate; forming a storage node cover On the above-mentioned contact plugs and a part of the dielectric layer, the storage node includes at least a stack of this paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) (Please read the precautions on the back before filling ， Writing this page} # · Printed by Line 1 Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economy
柄型層、jv τα 一 锋一 數個間隙壁覆# ^ μ 一弟二金屬層；形成複 復皿在该儲存節點之 一入十士 材料層覆蓋在上述 < W 土上，形成一南介電值 -部分上；形成一第储存節‘點、間隙壁、以及介電層之另 上；以及進行1美二金屬層位於上述之高介電值材料層 部分以及第三金屬； 稭以去除-介電值材料層之一 另一部分。 ㈢之一部分，並暴露出上述之介電層的 其中，上述之第_ 讓高介電值材料屬層以及間隙壁之材料較佳為可 # > -k 'ft ^ 7成於其上而不會產生副作用之材 枓，例如過渡金屬， 埴 j於回；丨電值材料形成於其上。此 外’板型層之材料 如為非金屬之介電材料，因此模型 層之厗度可以很厚而 个级〜I杈型層之電漿蝕刻的進行。 圖式簡單說明I 本發明的較伟音· & y ^々 貫施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1圖至第2圖為繪示習知電容器之製程剖面圖；以 及 第3圖至第6圖為繪示本發明之一較佳實施例之高介 電常數電容器的製程剖面圖。 圖號對照說明I 100 基材 102 隔離層 104 閘極 106 源極 108 汲極 110 絕緣層 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 559987 A7 B7 五、發明説明（ 112 接觸窗 116 複晶秒層 120 過渡金屬層 12 4 阻障金屬間隙壁 128 高介電值材料層 2 0 0 基材 204 介層窗 208 金屬層 212 金屬層 216 金屬層 220 高介電值材料層 114 118 122 126 130 202 206 210 214 218 222 接觸插塞 阻障層 儲存節點 過渡金屬間隙壁 上電極 介電層 接觸插塞 模型層 儲存節點 間隙壁 上電極 (請先閱讀背面之注意事項再填寫本頁j 經濟部智慧財產局員工消費合作社印製 發明詳細說明： 本發明揭露一種高介電值電容器及其製造方法，不需 沉積額外的阻障金屬，而藉由非金屬之模型層的使用來避 免習知直接以電漿蝕刻蝕刻下層金屬材料，進而獲得較佳 之蚀刻形狀以及微距（C r i t i c a 1 D i m e n s i ο η ; C D)控制能力〇 因此’具有製程簡單、製作成本低、以及良率佳等優點 為了使本發明之敘述更加詳盡與完備，可夂昭 、下列描述並 配合第3圖至第6圖之圖示。 請參照第3圖至第6圖，其係繪示本發明+ Θ之一較佳實 施例之高介電常數電容器的製程剖面圖。首生 先，提供半導 體之基材200，其中基材200上已形成例如記憶 隨（未纟會示） 之閘極、源極、汲極、以及隔離結構等。再带 7战）丨電層202 本紙張尺度適用中國國家標準(CNS)A4規格(210Χ 297公釐） -訂· 線一 559987 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 復1在基材2 0 0上’並利用例如微影（p h 〇 t 〇 1丨t h 〇 g r a p h y)以 及蝕刻製程對此介電層202進行定義，藉以去除部分之介 電層202 ’並暴露出部分之基材2〇〇，而在介電層2〇2中以 及基材200上形成介層窗204。其中，介層窗204所暴露 出之區域’可例如為基材200上之源極或是汲極。接著， 沉積導電材料覆蓋在介電層2〇2、所暴露之基材2〇〇、以及 介層窗204上，並填滿介層窗2〇4後，利用例如化學機械 研磨（Chemical Mechanical Polishing; CMP)的方式去除介 電層202上之導電材料，而在介層窗2〇4中形成接觸插塞 206。其中，接觸插塞2〇6之材料可例如為複晶矽、鎢 (Tungsten ; W)、或複晶矽與鎢之組合等導電材料。 然後，利用例如沉積的方式形成厚度很薄之金屬層2〇ί 覆蓋在介電層202以及接觸插塞206上，藉以在後續之製 程中防止高介電值材料之氧擴散。其中，金屬層2〇8'之厚 度相當薄’較佳是介於約100Α至約800Α之間，a u ^ J 如此一來 可使得金屬層208之電漿蝕刻更方便進行。金屬層形 成後，沉積較厚之模型層210覆蓋在金屬層2〇8上，其^ 模型層210之厚度較佳是介於約2〇〇〇a至約12〇〇〇人之八 另外，模型層2 1 0之材料可例如為非金屬之介 "电材料。由 經濟部智慧財產局員工消費合作社印製 於，模型層2 1 0係由介電材料所構成，相當容 约从電漿蝕 刻，因此模型層210可以很厚，而不會影響雷 / 〇 电水蝕刻的進 行。接著，沉積一層薄薄的金屬層2丨2覆蓋在捃 %煨型層2 1 0 上，其中金屬層212之厚度較佳是介於約1〇〇 aShank layer, jv τα one front and several gaps covering # ^ μ a second metal layer; forming a duplicate dish at one of the storage nodes, a layer of ten material covering the above < W soil, forming a south A dielectric value-partly; forming a first storage node 'point, a spacer, and a dielectric layer; and performing a metal layer on the high-dielectric material layer part and the third metal; Removal-one of the other layers of the dielectric material layer. And a part of the above-mentioned dielectric layer is exposed, among which the above-mentioned _ let the high-dielectric material material layer and the material of the spacer be preferably # > -k 'ft ^ 7 on it Materials that do not cause side effects, such as transition metals, are used in the back; 丨 Electric value materials are formed on them. In addition, if the material of the 'plate type layer' is a non-metallic dielectric material, the thickness of the model layer can be very thick, and plasma etching can be carried out at a level of ~ 1? Schematic illustration I The more powerful sound of the present invention & y 々 々 The embodiment will be described in more detail in the following explanatory text with the following figures, of which: Figures 1 to 2 are for illustration A cross-sectional view of a conventional capacitor manufacturing process; and FIGS. 3 to 6 are cross-sectional views illustrating a manufacturing process of a high dielectric constant capacitor according to a preferred embodiment of the present invention. Drawing number comparison description I 100 Base material 102 Isolation layer 104 Gate electrode 106 Source electrode 108 Drain electrode 110 Insulation layer This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling This page) 559987 A7 B7 V. Description of the invention (112 Contact window 116 Polycrystalline second layer 120 Transition metal layer 12 4 Barrier metal spacer 128 High dielectric material layer 2 0 0 Substrate 204 Interlayer window 208 Metal layer 212 Metal layer 216 Metal layer 220 High-k material layer 114 118 122 126 130 202 206 210 214 218 222 Contact plug barrier storage node transition Metal dielectric layer on the metal barrier wall Contact plug model layer Storage node gap wall Electrode (please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Detailed description of the invention: The present invention discloses a high-dielectric value capacitor and its manufacturing method, without the need to deposit additional barrier metals , And the use of non-metallic model layers to avoid the conventional direct etching of the underlying metal material by plasma etching, so as to obtain a better etching shape and macro C ritica 1 D imensi ο η; CD) control ability. Therefore, 'it has the advantages of simple process, low production cost, and good yield. In order to make the description of the present invention more detailed and complete, the following description and the third Figures 6 to 6. Please refer to Figures 3 to 6, which are cross-sectional views showing the manufacturing process of a high-dielectric-constant capacitor according to a preferred embodiment of the present invention + Θ. Substrate 200, in which the gate, source, drain, and isolation structure of memory (not shown) have been formed on the substrate 200. Then with 7 wars 丨 Electric layer 202 This paper is applicable to China National Standard (CNS) A4 Specification (210 × 297 mm)-Order · Line One 559987 A7 B7 V. Invention Description () (Please read the precautions on the back before filling this page) Copy 1 on the substrate 2 0 0 ' The dielectric layer 202 is defined by using, for example, lithography (ph 〇t 〇1 丨 th graphy) and an etching process, so as to remove a part of the dielectric layer 202 'and expose a part of the substrate 200, and Dielectric is formed in the dielectric layer 202 and on the substrate 200 Window 204. The area 'exposed' by the interlayer window 204 may be, for example, a source or a drain on the substrate 200. Next, a conductive material is deposited to cover the dielectric layer 202 and the exposed substrate 2 〇〇, and the interlayer window 204, and after filling the interlayer window 204, using a method such as chemical mechanical polishing (CMP) to remove the conductive material on the dielectric layer 202, and the interlayer window A contact plug 206 is formed in 204. The material of the contact plug 206 can be, for example, a conductive material such as polycrystalline silicon, tungsten (Tungsten; W), or a combination of polycrystalline silicon and tungsten. Then, a thin metal layer 20 is formed on the dielectric layer 202 and the contact plug 206 by, for example, a deposition method, so as to prevent oxygen diffusion of the high-dielectric value material in a subsequent process. Among them, the thickness of the metal layer 208 'is relatively thin', preferably between about 100A and about 800A, and a u ^ J can make plasma etching of the metal layer 208 more convenient. After the metal layer is formed, a thicker model layer 210 is deposited to cover the metal layer 208. The thickness of the model layer 210 is preferably between about 2000a to about 12,000 people. In addition, The material of the model layer 2 10 may be, for example, a non-metal dielectric " electrical material. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the model layer 2 10 is composed of a dielectric material, which is quite capable of being etched from the plasma. Therefore, the model layer 210 can be very thick without affecting the lightning / 〇 电The progress of water etching. Next, a thin metal layer 2 丨 2 is deposited and covered on the 捃% 煨 -type layer 2 1 0, wherein the thickness of the metal layer 212 is preferably between about 100 a
至約600A 五、發明説明（） 屬：層212將有利於電漿的钱刻。而且，金 上而不產生副作用:用電值材料順利地沉積於其 屬，例如鉑（Pt) 1(R / ^ 212之材料較佳是過渡金 電值材料的2 Γ 1及_)等，以利後續之高介 過渡：屬’亦可為其他金屬材料。 輸+並不限於 =屬層212之沉積後，利用例如微影 ==刻技術進行定義，而去除部分之金屬… ，以金屬層2°8’並暴露出部分之介電層加。 曰一 ㉝分之介電I 202以及接觸插塞206上形成由 =一部分之金屬層212、模型層21〇、以及金屬層所堆 且而=之储存節點214，所形成之結構如第3圖所示。 ”請參照第4圖，儲存節點2 1 4形成後，共形（C〇nformally) 况積金屬層216覆蓋在儲存節點214以及介電層2〇2上。 其中，金屬層216之厚度較佳是介於約2〇〇人至約8〇〇人之 間’且金屬層216之材料較佳是能讓高介電值材料順利地 沉積於其上而不產生副作用者，例如過渡金屬中的鉑、釕、 以及銀等，以供後續之高介電值材料得以順利地沉積於其 Ji 〇 ' 經濟部智慧財產局員工消費合作社印製 接著，利用例如電漿蝕刻的方式，進行金屬層2丨6的 回蝕刻（Etching Back)，而去除部分之金屬層216，並暴露 出部分之金屬層2 1 2以及部分之介電層2〇2。藉以在儲存 節點2 1 4之側壁上形成間隙壁2丨8，所形成之結構如第5 本紙張尺度適用中國國家標準(CNS)A4規格(2l〇x 297公爱) 559987 、發明說明（ 圖所示。此時， 山 產生副作用之全：材料順利地沉積於其上而不 隙壁218金人屬’例如過渡金屬，即金屬層212以及間 ^ 凡王將儲存節點2 1 4包覆住。 214, fL, 220 '、土 、以及介電層202上，盆中高介 層22〇之鉍# π "電值材料 (Ba.Sr "、口例如為；太酸銷（SrTi03)、鈦酸銷鋇 層咖的由於’高介電值材料 222覆 T大幅提高電容器之電容。再沉積上電極 料較佳材料層22…其中上電極222之材 α金屬’例如翻、訂、以及銥等。然後，利用 心以及姓刻的方式，定義高介電值材料層2 上電極？？9，工丄 ^ 而去除部分之高介電值材料層220以及部分 22並暴露出部分之介電層202，藉以完成本發 明之電容器結構，如第6圖所示。 ；儲存節點2 1 4完全受到金屬層2 1 2以及間隙壁 8的覆蓋，因此高介電值材料層220可順利地形成在儲 、子節點2 1 4與間隙壁2 1 8上。此外，由於模型層2 1 0之材 料非金屬之介電材料，因此不需在高介電值材料層22〇與 儲存即點2 1 4之間再形成額外的阻障結構，即可避免因高 介電值材料層220之氧的擴散而形成低介電值材料薄膜， 進而可避免電容器之電性品質受到影響。 由於’本發明之高介電值電容器不需任何阻障金屬 層。因此’製程簡單易施行，而可有效提高製程可靠度與 10 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) _、=& 線一 經濟部智慧財產局員工消費合作社印製 559987 A7 _B7_ 五、發明説明（） 良率，並可大幅地降低製造成本。 本發明之高介電值電容器之製造方法係利用過渡金屬 包覆住電容器之儲存節點。因此，高介電值材料層可直接 形成於儲存節點上，而不需再額外形成多層阻障結構。如 此一來，不僅可降低製程負擔，電容器的電性品質亦可獲 得提升。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 (請先閲讀背面之注意事項再填寫本頁) # -訂· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)To about 600A V. Description of the invention (): The layer 212 will be beneficial for the plasma cutting of plasma. Moreover, gold does not cause side effects: the value material is smoothly deposited on its genus, for example, platinum (Pt) 1 (the material of R / ^ 212 is preferably 2 Γ 1 and _) of a transition gold value material, etc., In order to facilitate the subsequent high-media transition: the genus can also be other metal materials. After the deposition of the metal layer 212, it is defined by, for example, the lithography technique, and a part of the metal is removed. The metal layer is 2 ° 8 ′ and a part of the dielectric layer is exposed. A part of the dielectric layer I 202 and the contact plug 206 are formed with a part of the metal layer 212, the model layer 21, and the storage node 214 stacked with the metal layer. The structure formed is as shown in FIG. 3 As shown. Please refer to FIG. 4, after the storage node 2 14 is formed, a conformally formed metal layer 216 covers the storage node 214 and the dielectric layer 202. Among them, the thickness of the metal layer 216 is better It is between about 200 people and about 800 people ', and the material of the metal layer 216 is preferably one that allows high-dielectric material to be smoothly deposited thereon without causing side effects, such as in Platinum, ruthenium, and silver, etc., for subsequent high-dielectric materials to be successfully deposited on its Ji 〇 'Intellectual Property Bureau, Employees' Cooperatives, and printed by a consumer co-operative society. Then, for example, plasma etching, the metal layer 2丨 6 Etching Back, and remove part of the metal layer 216, and expose part of the metal layer 2 1 2 and part of the dielectric layer 2 0. A gap is formed on the side wall of the storage node 2 1 4 Wall 2 丨 8, the structure formed is the same as the fifth paper standard applicable to Chinese National Standards (CNS) A4 specifications (2l0x 297 public love) 559987, invention description (shown in the picture. At this time, the mountain has all the side effects: Material deposited smoothly on it without gaps For example, the transition metal, ie, the metal layer 212 and the intermediate layer Wang Fan, cover the storage node 2 1 4. 214, fL, 220 ′, soil, and the dielectric layer 202, the high dielectric layer 22〇 之 bis in the basin # π " Electric value materials (Ba.Sr ", for example; too acid pin (SrTi03), barium titanate pin, because of the high dielectric value material 222 coating T greatly increases the capacitor's capacitance. Then deposit the electrode material The preferred material layer 22 ... Among them, the alpha metal of the upper electrode 222 is, for example, turned, stapled, and iridium, etc. Then, the upper electrode of the high-dielectric value material layer 2 is defined by using the method of heart and last name. ^ The portion of the high-dielectric material layer 220 and the portion 22 are removed and a portion of the dielectric layer 202 is exposed to complete the capacitor structure of the present invention, as shown in FIG. 6; The storage node 2 1 4 is completely subjected to the metal layer 2 1 2 and the gap 8 cover, so the high dielectric material layer 220 can be smoothly formed on the storage and sub-nodes 2 1 4 and the gap 2 2 8. In addition, because the material of the model layer 2 1 0 is non-metal Dielectric material, so there is no need to An additional barrier structure is formed in between, which can avoid the formation of a thin film of a low dielectric material due to the diffusion of oxygen in the high dielectric material layer 220, thereby preventing the electrical quality of the capacitor from being affected. Dielectric value capacitors do not require any barrier metal layer. Therefore, the process is simple and easy to implement, which can effectively improve the process reliability and 10 paper sizes are applicable to China National Standard (CNS) A4 specifications (210X 297 mm) (Please read first Note on the back, please fill out this page again) _ 、 = & Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 559987 A7 _B7_ V. Description of the invention () Yield rate, and can significantly reduce manufacturing costs. The manufacturing method of the high-dielectric value capacitor of the present invention is to cover the storage node of the capacitor with a transition metal. Therefore, the high-dielectric material layer can be directly formed on the storage node, without further forming a multilayer barrier structure. In this way, not only can the process load be reduced, but the electrical quality of the capacitor can also be improved. As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention Effective changes or modifications should be included in the scope of patent application described below. (Please read the precautions on the back before filling out this page) # -Order · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X 297 mm)