TW563189B - Method for forming self-aligned metal oxide semiconductor transistor - Google Patents

Abstract

The present invention provides a method for forming a metal oxide semiconductor (MOS) transistor having a self-aligned and silicide-covered gate. The gate has a larger surface area and a lower resistance such that the invented method is applicable in a process with an ever decreasing IC size. The invented method mainly comprises: depositing a selective dielectric layer, e.g. a poly-Si-Ge, on the gate to increase the surface area thereof; and forming a silicide layer on the surface thereof to reduce the resistance thereof. As a result, the formed gate has a larger contact area than one produced by a conventional process, and is easier to be connected to a wire, thereby increasing the efficiency of the MOS transistor.

Description

563189 V. Description of the invention (1) 5-1 Field of invention:

There is a medium. You can't do it right. We have a body-on-crystal electrode. The half-gate method of oxygen and square gold formation and decent shape of the 1 crystal surface of the electrode has a half-gate is oxygen plus bright gold issuance of an original material ΠΓ5Ξ! ^ ¾ IV, ^ H 5-2 Background of the invention: Traditional The method for forming a MOS transistor usually includes the following steps: first, as shown in the first A diagram, a substrate 10 is provided, and then a gate oxide layer 15 is formed on the substrate 10. Next, a gate 20 is formed on the gate oxide layer 15 again. After that, the gate electrode 20 is used as a mask, and an ion implantation is performed to form a lightly doped electrode 25 and a lightly doped source electrode 30. Then, a side wall 40 of the gate electrode 20 is formed, as shown in the first B diagram. The gate electrode 20 and the side wall 40 are used as a curtain, and another ion implantation is performed to form a drain electrode 45 and a source electrode 50. This completes the fabrication of a MOS transistor. However, as the size of integrated circuits becomes smaller, the gates also need to be smaller. In this way, the contact area between the gate electrode and the wire will be reduced, and the resistance will increase, so that the efficiency of the MOS transistor will be reduced. One solution is to increase the conductivity of the gate. The current technology is to form a layer of petrified metal on the surface of the gate electrode, such as titanium titanite, petrified silicon or nickel silicide, to reduce the resistance of the gate. This method first deposits a metal layer 55, such as titanium, silicon, or silicon, to cover the surface of the MOS transistor, as shown in the first D diagram. Then, a heating step is performed, so that the gates 20, 50 and 5,

Page 4 563189 V. Description of the invention (2) Both the polycrystalline silicon on the surface of the source 30 and the metal interact with the metal to form a silicide metal layer (60, 65, 70), as shown in the first E diagram. Finally, the metal layer 55 is removed, as shown in the first F diagram. However, although the above-mentioned method can reduce the gate resistance value, it still encounters difficulties when the size of the gate is reduced when the wire connection is made. Therefore, another solution is how to effectively increase the surface area of the gate. 5-3 Objects and Summary of the Invention An object of the present invention is to provide a method for gold-oxygen semitransistor. Another object of the present invention is to provide a method to increase the surface area of the gate electrode. Another object of the present invention is to provide a method to reduce the resistance value of the gate electrode. The following steps: First, a structure is provided, which includes at least a substrate, a gate oxide layer on the substrate; and a gate on the gate oxide layer. Then, ion implantation is performed to form a lightly doped drain and a lightly doped source. Second, a first dielectric layer is deposited, such as an oxide stone layer or a nitride stone layer, to cover

563189 V. Description of the invention (3) This gate, gate oxide layer, lightly doped electrode and lightly doped source electrode. Then, an etching step is performed to remove a part of the first dielectric layer to expose a part of the upper end of the gate. After that, a second dielectric layer, such as polycrystalline silicon germanium, is selectively deposited on the surface of a part of the upper end of the exposed gate. The surface area and width of the second dielectric layer are larger than those of the exposed gate region. It is worth noting that this second dielectric layer will only be deposited on the gate made of polycrystalline silicon and will not be deposited on the first dielectric layer. Therefore, this step is self-aligning. This deposition step can be performed by chemical vapor deposition at about 50 ° C. to 700 ° C. Then, a portion of the first dielectric layer is removed by using the second dielectric layer as a mask to expose the lightly doped drain. Electrode and lightly doped source electrode, and partially shielded by this second dielectric layer and the remaining first dielectric layer is used as the sidewall of the gate. Then, an ion implantation step is performed to form the anode and source. A metal layer such as titanium, starting, and recording can be deposited to cover the second dielectric layer, the drain, and the source. Then, a heating step is performed to make the second dielectric layer, the drain, and the source The polycrystalline silicon on the electrode surface reacts with the metal to form a silicided metal layer. This silicided metal layer can reduce the resistance values of the gate, the drain, and the source. The step of depositing the metal layer may be an ionized metal plasma I MP) method. The metal-oxide semiconductor transistor thus formed has a gate having a larger surface area and a lower resistance value. 5-4 Detailed description of the invention: The preferred embodiments of the present invention will be discussed in detail later. Implementation Example is to use

Page 6 563189 V. Description of the Invention (4) To describe a specific example of using the present invention, it is not intended to limit the scope of the present invention. The present invention proposes a method that can effectively increase the gate surface area. The detailed steps are as follows: First, as shown in Figure A, a substrate 10 is provided, and then a gate oxide layer 1 is formed on a substrate 10. 5. Next, a polycrystalline silicon layer is deposited on the gate oxide layer 15 and the polycrystalline silicon layer is etched to form a gate electrode 20. After that, the gate electrode 20 is used as a mask, and an ion implantation is performed to form a lightly doped drain electrode 25 and a lightly doped source electrode 30. Each MOS transistor is separated by a field oxide layer 35, as shown in the second A diagram. Then deposit a first dielectric φ layer 75, such as a silicon oxide layer or a silicon nitride layer, to cover the gate 20, the gate oxide layer 15, the lightly doped drain 25, and the lightly doped source 3 0, as shown in the second B figure. Then, an etching step is performed to remove a part of the first dielectric layer 75 to expose a part of the upper end of the gate electrode, as shown in the second C diagram. Afterwards, a second dielectric layer 80 is deposited by chemical vapor deposition between about 500 ° C and 700 ° C to cover a part of the upper end of the exposed gate, such as the second D As shown. The material of the second dielectric layer 80 is mainly a substance having selective deposition, such as polycrystalline silicon germanium, which can only be deposited on the surface of the gate 20 made of polycrystalline silicon, and will not be deposited. Above the first dielectric layer 75, it is therefore a self-aligned deposition method. As shown in the second D diagram, we can find that the surface area and width of the second dielectric layer 80 are larger than the area of the partial area of the gate 20 originally. Therefore, it is beneficial to the connection between the gate and the conductor and to increase the contact area. Then, using this second dielectric layer 80 as a mask, an anisotropic etching is performed to remove a portion of the first dielectric layer 75 to expose it.

Page 7 563189 V. Description of the invention (5) Most of lightly doped drain 25 and lightly doped source 30. The portion of the first dielectric layer that has not been removed below the second dielectric layer 80 is used as the sidewall 85 of the gate electrode 20, as shown in the second E diagram. Then, an ion implantation is performed with the second dielectric layer 80 as a curtain to generate a drain electrode 90 and a source electrode 95, as shown in the second F diagram. Then, a metal layer 100, such as titanium, cobalt, or nickel, is deposited by an ionized metal plasma method (I MP) to cover the surface of the MOS transistor, the drain electrodes 90 and 95, as shown in the second G diagram. Show. Then, a heating step is performed so that the surfaces of the second dielectric layer 80, the drain electrode 90, and the source electrode 95 all interact with the metal to form a silicided metal layer (1 0 5, 1 1 0, 1 1 5), as shown in the second figure. The petrified metal layer (1 0 5, 1 1 0, 1 1 5) can reduce the resistance values of the gate electrode 20, the drain electrode 90, and the source electrode 95, so that problems caused by the reduction in size can be avoided. . Finally, the metal layer is removed, and the MOS transistor of the present invention is completed as shown in FIG. 2I. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 563189 Brief description of the drawings, as shown in the drawings of this description: Figures A to F: Traditional sectional views of various stages of forming a gold-oxygen semi-transistor with a silicided metal layer; Figures A to II. The present invention forms a cross-sectional schematic diagram of an embodiment of a self-aligned metal-oxide semiconductor transistor at each stage. Representative symbols of the main part: 10 substrate φ 15 gate oxide layer 2 gate Electrode 2 5 lightly doped electrode 3 0 lightly doped source electrode 3 5 field oxide layer 40 sidewall 4 5 drain electrode 5 0 source electrode 55 metal layer 6 0 gate silicided metal layer 6 5 drain electrode Metal layer 7 0 Source silicided metal layer 75 First dielectric layer 80 Second dielectric layer

563189 Brief description of the diagram 85 Side wall 90 Drain 9 5 Source 1 0 0 Metal layer 1 0 5 Silicide metal layer at the gate 1 1 0 Silicide metal layer at the drain 1 1 5 Petrified metal layer at the source

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Claims (1)

563189 6. Application scope 1. A method for increasing the gate surface area, the method includes at least the following steps to provide a structure, the structure includes at least a substrate, and the substrate includes at least a gate oxide layer 'a gate On the gate oxide layer 'the substrate contains at least a light doping; and a pole and a lightly doped source; forming a first dielectric layer to cover the substrate, the gate oxide layer, the gate Electrode, the lightly doped drain electrode, and the lightly doped source electrode; etching the first dielectric layer to expose a part of the gate electrode; selectively depositing a second dielectric layer to cover the gate electrode The second dielectric layer covers the partial area of the gate electrode; and the second dielectric layer is used as a screen cover, and the first dielectric layer is engraved with # The lightly doped drain electrode and the lightly doped source electrode are exposed, and the first dielectric layer partially remaining on the surface of the gate serves as a side wall of the gate. 2. As in the method of claim 1, the method further includes an ion implantation step to form a drain and a source. 3. The method of claim 1 in which the first dielectric layer is a silicon oxide layer. 4. The method of claim 1, wherein the first dielectric layer is a nitrided layer. Page 11 563189 6. Scope of patent application 5. The method according to item 1 of the patent scope, wherein the second dielectric layer is a polycrystalline silicon germanium layer. 6. The method according to item 5 of the patent application, wherein the polycrystalline silicon germanium layer is formed by a chemical vapor deposition method. 7. The method of claim 6 in which the chemical vapor deposition method is performed at about 500 ° C to 700 ° C. 8. If the method of claim 1 is applied, the method further includes the following steps: performing an ion implantation step to form a drain and a source: forming a metal layer covering the drain, the source, the sidewall, and the A second dielectric layer; performing a heating step to form a silicided metal layer on the surface of the second dielectric layer; and removing the metal layer. 9. The method according to item 8 of the patent application, wherein the material of the metal layer is one selected from the group consisting of titanium, diamond, and nickel. 10. The method according to item 8 of the scope of patent application, wherein the metal layer is deposited by an ionized metal electropolymerization method (MP). Page 12 563189 6. Application patent scope 11. A method for forming a metal oxide semi-electric crystal, the method includes at least the following steps: providing a substrate; forming a gate oxide layer on the substrate; forming a gate electrode On the gate oxide layer; forming a lightly doped drain electrode and a lightly doped source electrode on the substrate; forming a first dielectric layer to cover the substrate, the gate electrode, and the lightly doped drain electrode And the lightly doped source; I etch the first dielectric layer to expose a portion of the gate; and selectively deposit a second dielectric layer to cover the portion of the gate Wherein the second dielectric layer covers the partial area of the gate electrode with the second dielectric layer as a curtain cover, and the first dielectric layer is engraved to expose the lightly doped drain electrode. And the lightly doped source, a portion of the first dielectric layer remaining on the gate surface serves as a sidewall of the gate; an ion implantation is performed to form a drain and a source; and a metal layer is formed to Covering the drain, the source, the sidewall, and the second dielectric layer; and performing a heating step to form a A silicided metal layer is on the surface of the second dielectric layer; and etching to remove the metal layer. 12. The method according to item 11 of the scope of patent application, wherein the first dielectric layer is a silicon oxide layer. Page 13 563189 6. Scope of patent application 1 3. The method according to item 11 of the scope of patent application, wherein the first dielectric layer is a silicon nitride layer. 14. The method according to item 11 of the scope of patent application, wherein said second dielectric layer is a compound crystal; e-layered. 15. The method according to item 14 of the scope of patent application, wherein the polycrystalline silicon germanium layer is formed by a chemical vapor deposition method. 16. The method according to item 15 of the scope of patent application, wherein the chemical vapor deposition® method is performed at about 500 ° C to 700 ° C. 1 7. The method according to item 11 of the scope of patent application, wherein the material of the metal layer is one selected from the group consisting of titanium, cobalt, and nickel. 18. The method according to item 11 of the scope of patent application, wherein the metal layer is deposited by an ionized metal plasma method (IMP). Page 14