566065 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說们 【發明所屬^技術領域】 本發明係有關於使用於電器及電子機器之電路系統之 電子零件搭載基板之製造方法、及藉由該方法所製造之電 5子零件搭載基板。 C先前技術3 近年’伴隨對電子機器之高性能化及小型化等要求， 組裝於電子機器之電子零件之高密度封裝化急速地進展。 為了因應這種高密度封裝化，就IC晶片來說，以裸晶封裝 10之狀態面實裝於配線基板，亦即倒裝晶片封裝之情況很多 。就用以搭載1C晶片之配線基板來說，伴隨IC晶片之多 插腳化，而有採用在達成配線之高密度化上適宜之多層配 線基板之傾向。 增層法係一種用以形成在多層配線基板之多層配線構 15造之方法。在增層法中，於核心基板上依序重複形成絕緣 層及形成該絕緣層上之配線圖案，使配線多層化。具體來 說’首先，在作為核心基板之玻纖環氧基板或BT基板上 積層形成由環氧系樹脂形成之增層絕緣層。接著，於該絕 緣層上形成穿孔穴。形成穿孔穴之方法可採用：使用感光 20性樹脂作為絕緣層材料並藉微影成像法在絕緣層形成孔穴 之方法、或藉照射雷射在絕緣層形成孔穴之方法等。在絕 緣層形成穿孔後，藉無電解電鍍或電鍍，在絕緣層上使導 體材料成膜。這時，藉導體材料使穿孔在穿孔穴上形成。 接著，藉由將業已於絕緣層上成膜之導體材料蝕刻而形成 6 566065 玖、發明說明 配線圖案。如此在絕緣層上形成配線圖案後，藉由以預定 次數反覆進行從絕緣層之積層形成到配線形成為止一連串 之步驟，即可達到配線之多層化’結果可提高電路之集積 度0 5 然而，藉增層法形成多層配線構造之多層配線基板上 ，高頻率通帶之傳送特性將成為問題。尤其是1C晶片與電 容器間之距離一旦變長，則配線電阻（亦即電感）增大， 訊號干擾就變得更容易發生。 於是，縮短1C晶片與電容器間之距離以抑制配線電阻 10 之已知技術係以1C晶片之電極部露出核心基板之表面側之 狀態將1C晶片内藏於核心基板，之後於核心基板表面形成 多層配線構造之技術（例如參照下述文獻1及2)。又，用 以縮短1C晶片與電容器間之距離以抑制配線電阻之其他已 知技術係於金屬形成之支持基板之表面藉增層法形成多層 15 配線構造，相對於該多層配線構造之最外層之表面搭載1C 晶片，同時施以補強板加工後，除去前述支持基板之全體 ，藉此於業已露出之絕緣層之裡面形成銲錫凸塊之多層膜 (MLTF)封裝技術（例如參照下述文獻3)。 文獻1 :特開2001-352174號公報 20 文獻 2 : R. Emery，S· Towle，H. Braunisch，C. Hu，G.566065 发明 Description of the invention (The description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments and the drawings. [Technical field of the invention] The present invention relates to the use of electrical and electronic equipment. Manufacturing method of electronic component mounting substrate of circuit system, and electric sub-component mounting substrate manufactured by the method. C Prior art 3 In recent years, it has been assembled in electronic equipment in accordance with requirements for high performance and miniaturization of electronic equipment. In order to cope with such high-density packaging, in terms of IC chips, the bare chip package 10 is mounted on the wiring substrate in the state of the bare chip package 10, that is, flip-chip packaging is often the case. As for the wiring board used for mounting 1C chips, with the increase in the number of pins of the IC chip, there is a tendency to use a multilayer wiring board suitable for achieving high density of wiring. The build-up method is used to form a multilayer board. A method for manufacturing a multilayer wiring structure of a wiring substrate. In the build-up method, an insulating layer is sequentially and repeatedly formed on the core substrate and the insulating layer is formed. The wiring pattern is used to multilayer the wiring. Specifically, 'first, a glass-fiber epoxy substrate or a BT substrate as a core substrate is laminated to form a layered insulating layer made of an epoxy resin. Next, on the insulating layer Forming a perforated hole. The method of forming a perforated hole can be: a method of using a photosensitive 20 resin as an insulating layer material and forming a hole in the insulating layer by lithography, or a method of forming a hole in the insulating layer by irradiating a laser. After the perforation of the insulating layer is formed, the conductive material is formed on the insulating layer by electroless plating or electroplating. At this time, the perforation is formed on the perforated hole by the conductive material. Then, the conductor that has been formed on the insulating layer is formed by the conductive material. The material is etched to form 6 566065 玖, the wiring pattern of the invention description. After the wiring pattern is formed on the insulating layer, a series of steps from the formation of the insulating layer to the formation of the wiring is repeated a predetermined number of times to achieve multiple layers of wiring. The result can improve the integration degree of the circuit. 0 5 However, high frequency The transmission characteristics of the passband will become a problem. In particular, once the distance between the 1C chip and the capacitor becomes longer, the wiring resistance (that is, the inductance) will increase, and signal interference will become more likely to occur. Therefore, the 1C chip and the capacitor will be shortened. A known technique for suppressing the wiring resistance 10 is a technique in which the 1C wafer is embedded in the core substrate with the electrode portion of the 1C wafer exposed on the surface side of the core substrate, and then a multilayer wiring structure is formed on the surface of the core substrate (for example, see below) References 1 and 2). Another known technique for shortening the distance between a 1C chip and a capacitor to suppress wiring resistance is to form a multilayer 15 wiring structure on the surface of a support substrate formed of metal by an additive layer method. The outermost layer of the multilayer wiring structure is equipped with a 1C chip, and after the reinforcement board is processed, the entire support substrate is removed to form a multilayer film (MLTF) packaging technology (solder bump) inside the exposed insulation layer ( For example, refer to the following reference 3). Document 1: JP 2001-352174 20 Document 2: R. Emery, S. Towle, H. Braunisch, C. Hu, G.
Raiser, and G. J. Vandentop、“Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric Constant Materials”、[online]、平成 13 年 10 月 12 日、intel Co. Η·Ρ· 、 URL : 7 566065 玖、發明說明 http://www.intel.com/research/silicon/BBULconferencefoils.p 文獻 3 : T. Shimoto, K. Kikuchi，H. Honda，K. Kata, Κ· Baba，and Κ· Matsui “High-Performance Flip-Chip BGA 5 based on Multi-Layer Thin-Film Packaging Technology”, Proceedings of the 2002 IMAPS, p.10-15. 上述文獻1及文獻2所揭示之技術，由於係在預先將 1C晶片固定於支持基板後，藉增層法形成多層配線構造， 因此1C晶片及多層配線構造之位置組合很困難。又，由於 10 預先將1C晶片固定於支持基板後始形成多層配線構造，因 此當多層配線構造發生不良時，1C晶片之再利用變得很困 難。亦即，當多層配線構造之成品率不是100%時，浪費高 價之1C晶片的可能性很高。 又，文獻3中揭示之技術，為了拉近ic晶片與電容器 15 之距離，最後必須全面除去支持基板。一旦如此除去支持 基板，則作為晶片零件搭載基板缺乏剛性，進行封裝或其 他裝卸將變得很困難。再加上，當以對除去支持基板之晶 片零件搭載基板賦予剛性為目的而在多層配線構造之最上 層之表面設置加強材時，由於過程步驟增加，因此作業效 20 率不佳。又，由於1C晶片搭載後必須加工晶片零件搭載基 板，因此在該加工時可能會破壞1C晶片。 【明内容3 發明概要 因此，本發明之目的，即在提供可圖電子零件搭載基 8 566065 玫、發明說明 板之低電感化’同時在位置組合及實用性上優異且作業效 率優異之電子零件搭載基板之製造方法。 本發明之另-目的，在提供藉該方法所製造之晶片零 件搭載基板。 5 #本發明之第1方面所提供之電子料搭載基板之製 造方法，&含有··於金屬製之支持基板表面使增層絕緣層 及增層配線圖案交互形成之增層積層步驟；於載置前述支 持基板之電子零件之位置形成貫通孔，使最内層之增層絕 緣層露出之孔形成步驟；及經由前述支持基板之前述貫通 10孔於前述最内層之增層絕緣層封褒電子零件之封裝步驟。 藉該製造方法，可在支持基板之表面形成增層積層體 後進行電子零件之搭載。因此，對增層積層體搭載電子零 件時之位置組合變得比較容易進行。又，由於可在形成增 層積層體後進行電子零件之搭載，故可在確認增層積層體 15適曰地形成後再搭載電子零件，如此不會浪費電子零件， 且實用性優異。更，由於只需除去電子零件搭載範圍之支 持基板部分，故支持基板之剩餘部分具有與加強材同樣的 功能。所以在進行封裝或其他處理時具有足夠剛性。因而 不需另外設置賦予剛性之步驟，作業效率也很優異。 2〇 該製造方法以更包含在前述封裝步驟後，於前述貫通 孔中以絕緣性樹脂密封在前述電子零件周圍產生之間隙之 岔封步驟為佳。藉此，不僅可使各配線間之絕緣性提升， 且增加電子零件之搭載狀態下之安定度。因此，電子零件 與增層積層體間之電性連接可達到更高的可靠性。 9 566065 玖、發明說明 吞亥製造方法，以其中A益、+、以 、在引述增層積層步驟之前更包含 將2片支持基板之裡面暫時接合之暫時接合步驟，且在前 述增層積層步驟後、前述孔形成步驟之前，更包含分離兩 支持基板之分離㈣，而前述增層積層步_對各支持矣 板之表面進行為佳。藉這種製造方法，在增層積層步射 ，對支持基板或增層絕緣層加熱時，可緩和因兩者之熱膨 脹率之差所導致n亦即，藉由冑2片支持基板之裡 面暫時接合’則即使因—側之支持基板與形成於該支持基 板表面之增層絕緣層之熱膨脹率之差而產生了彎曲，但與 10 該幫曲正㈣地，•另-狀域基板與形成於該支持 基板表面之增層絕緣層之熱膨脹率之差也產生了彎曲，因 此互相抵銷。藉此可使封裝可靠性提升。 15 該製造方法，以其中前述暫時接合步驟係藉由將前述 兩支持基板夾持於具有露出各支持基板之外周部之大小之 2片樹脂薄片fa1，在加熱下使兩樹脂薄片真空積層來進行 為佳。藉這種製造方法，不彳堇2 #支持基板不必使用接著 劑等即可維持接合狀態，同時，例如只需切斷前述露出外 周部之樹脂薄片，即可輕易分離2片支持基板。又，樹脂 20 薄片之一部分可作為增層絕緣層之最内層來使用，在作業 效率上也很優異。 該製造方法’以其中前述暫時接合步驟之後更包含至 少前述兩樹脂薄片在露出部上形成金屬鍍膜之鍍膜步驟為 佳。藉該製造方法，則在增層積層步驟中，即使遇到在增 層絕緣層上形成增層配線圖案之際進行表面粗化處理之情 10 566065 玖、發明說明 况月述路出部之樹脂薄片藉前述金屬錢膜而不會受到表 面粗化處理之影響。因此，在增層積層步驟中，即使形成 多層’前述露出部之樹脂薄片也不會破損，可使兩2片支 持基板之暫時接合狀態更安定並維持。 5 該製造方法，以其中前述金屬鍍膜係與形成於對前述 最内層之增層絕緣層之配線圖案同時形成為佳。藉由這種 製k方法’可在作業效率更佳之狀態下進行金屬鍵膜之形 成。 该製造方法，以其中前述鍍膜步驟後更包含於前述金 10屬制上形成與該金屬鍍膜不同材料之保護膜《膜形成步 驟為佳。藉該製造方法，可防止金屬鍍膜在例如使用消去 (subtractive )法幵> 成配線圖案時進行之姓刻等而被除去。 藉此，可防止露出部之樹脂薄片之破損，並使2片支持基 板之暫時接合以更安定之狀態維持。 15 本發明之適宜之實施形態，係更具有：將電子零件中 ，在最内層之增層絕緣層之未形成增層配線圖案之裡面及/ 或支持基板之裡面研磨之研磨步驟。藉該製造方法，可圖 電子零件搭載基板全體之輕薄小型化。 藉本發明之第2方面所提供之電子零件搭載基板，係 2〇包含有··金屬製支持基板、於該支持基板之表面交互形成 增層絕緣層及增層配線圖案之增層積層體、及搭載於該增 層積層體之電子零件者，又，前述支持基板在載置前述電 子零件之位置具有貫通孔，而前述電子零件係經由前述支 持基板之刖述貫通孔而搭載於位於最内層之增層絕緣層之 11 566065 玖、發明說明 未形成增層配線圖案之裡面。 該電子零件搭載基板，以係於前述貫通孔以絕緣性樹 脂密封在前述電子零件周圍產生之間隙為佳。 該電子零件搭載基板，係以前述電子零件為1C晶片， 5而最外層之增層絕緣層中形成有增層配線圖案之表面搭載 有電容器為佳。藉此，可縮短1C晶片與電容器之配線距離 。因此，可減低電感，抑制雜訊干擾之發生。 本發明之適宜之實施形態中，構成支持基板之金屬， 以在-65 c〜280 c之溫度範圍之熱膨脹係數為lppm/K 10〜20PPm/K者為佳。藉由使用由具有該熱膨脹係數之金屬所 形成之支持基板，可進一步減低比較上熱膨脹係數較大之 增層積層體與比較上熱膨脹係數較小之電子零件之差。因 此，就增層積層體與電子零件之間之電性連接，可達成更 高的可靠性。又，該金屬以從由42合金、鉬、柯華合金、 15因鋼、42因鋼、鈦、銅/因鋼/包銅材、不錄鋼、銅、鐵、 鎳、紹當中選出者作為該金屬為佳。 圖式簡單說明 第1圖是有關本發明之晶片搭載基板之截面圖。 第2a〜2η圖是顯示同一晶片搭載基板之製造方法之一 20 連串步驟之截面圖。 第圖疋”、、頁示上述製造方法之一步驟之變形例之截面 圖。 第4圖疋顯不上述製造方法之一步驟之另一變形例之 截面圖。 12 566065 玖、發明說明 C實施方式】 第1圖是有關本發明之實施形態之晶片搭載基板X1 之截面圖。晶片搭載基板XI包含：具有表面la及裡面lb 之支持基板1、形成於表面la之增層積層體2、IC晶片3 5 及電容器4。 支持基板1具有用以收納1C晶片3之貫通孔U。貫 通孔11係因應搭載之1C晶片3之形狀，從支持基板j之 裡面lb到表面la而形成。又，支持基板丨之全體形狀為 例如板狀，該厚度以與IC晶片3之厚度相同程度為佳，不 10 過該形狀或厚度並不受限於此。 又，支持基板1係由金屬形成。該金屬以在-65〇c〜28〇 c之溫度範圍之熱膨脹係數為lppm/K〜2〇ppm/K者為佳。 構成該金屬之材料可舉例如：42合金、鉬、柯華合金、因 鋼、42因鋼、鈦、銅/因鋼/包銅材、不銹鋼、銅、鐵、鎳 、鋁等。 增層積層體2包含：絕緣層21 a〜21 f、配線圖案 22a〜22f、穿孔23、罩面（over-c〇at)層24。絕緣層21a 以在其裡面211a與支持基板丨之表面la接合之狀態形成 積層，絕緣層21a之表面212a上形成有配線圖案22a。又 2〇 ，絕緣層21b以在其裡面211b與絕緣層21a之表面212a 接合之狀態形成積層，絕緣層2ib之表面212b上形成有配 線圖案22b。更，如第i圖所示，絕緣層21c〜21f係與絕 緣層21b同樣地依序形成積層。唯，增層積層體2之積層 數並不受限於上述，而是可依需要任意決定。 13 566065 玖、發明說明 絕緣層21 a〜21 f之構成材料以使用一般的熱硬化性樹 脂為佳。該熱硬化性樹脂可舉例如··聚醯亞胺樹脂、環氧 树月曰、雙順丁稀二醯亞胺樹脂、順丁烯二醯亞胺樹脂、氰 酸酯樹脂、熱硬化性聚伸苯基醚樹脂、聚二苯醚樹脂、含 5氟樹脂、及全芳香型聚酯系液晶聚合物樹脂等。又，絕緣 層21a〜21 f之構成材料，並不限於上述所舉者。 配線圖案22a〜22f係在各個絕緣層21a〜21f上形成圖 案而成者。層間之各配線圖案間（例如配線圖案22及配線 圖案22b等）係藉穿孔23電性連接。又，穿孔23係藉下 10 述方法與配線圖案22a〜22f同時形成。 罩面層24是為了保護最外層之絕緣層2丨f上所形成圖 案之配線圖案22f而設，並具有開口部24a使配線圖案22f 之一部分面臨該罩面層24。構成罩面層24之材料可使用 上述作為絕緣層21a〜21f之構成材料之樹脂、或用在一般 15的焊料保護層之環氧丙烯酸酯樹脂。 1C晶片3係如第1圖所示，具有多數之球電極31，且 係從支持基板1之裡面lb側經由貫通孔π搭載於最内層 之絕緣層21a之裡面211a。1C晶片3係主要部分由矽等一 般的半導體元件材料構成，顯示熱膨脹率3〇〜3.5ppm/K。 20夕數球電極31在1C晶片3之表面3a上排列成格栅陣列狀 ，構成球格柵陣列。球電極31係由金或預定組成之焊料形 成。又，在貫通孔11上，IC晶片3之周圍所產生之間隙 藉由絕緣性樹脂樹脂密封，形成樹脂密封部32。用於該樹 脂密封之絕緣性樹脂可舉例如：環氧樹脂、聚醯亞胺樹脂 14 566065 玖、發明說明 、異氰酸酯樹脂等。 電容器4係如第1圖所示，具有多數電極部4卜從罩 面層24之表® 242侧藉由開口部叫搭載於最外層之絕緣 層加之表面而。電容器4之搭載數或容量依需要來任 5 意決定即可。 以下，參照第2a〜2n圖來說明藉增層法製造有關本實 施形態之晶片搭載基板X1時所適宜之方法。 製造晶片搭載基板XI時，首先，如第2a圖所示，對 2片支持基板1，1、之各個表面la，la'施以脫脂、氧處理及/ ίο或表面粗化處理（例如使用由銅形成之支持基板時為cz 處理等），再將2片支持基板1，Γ以裡面lb，lb、相向之狀態 重疊而構成支持基板10。 接著，如第2b圖所示，將支持基板10夾持於由絕緣 性樹脂形成且具有從各支持基板1，1'之外周部1 C 1 C'露出 15之大小之2片絕緣薄片2〇,2〇、間，以預定溫度及預定時間 施以真空積層。藉此，2片支持基板i，i'即可維持積層狀 態。構成絕緣薄片20,20'之絕緣性樹脂可舉例如與上述所 揭不之絕緣層21 a〜21 f之構成材料相同者。因此，絕緣薄 片20,20'中之覆蓋各支持基板1，1'之部分，作為最内層之 20 絕緣層21a，21 a'而發揮功能。另，基於圖示之精簡化，第 2b圖中係顯示業已對相當於一個晶片搭載基板XI之支持 基板1，Γ施以真空積層後之狀態，不過亦可例如歸納對應 多數個晶片搭載基板之大小之支持基板施以真空積層，再 進行過後述步驟之後再分割為多數個晶片搭載基板。 15 566065 玖、發明說明 接著，形成有絕緣層21a，21a'之基層支持基板1〇之要 部擴大圖顯示於第2c圖。如該圖所示，在絕緣層21a之預 定所在，形成穿孔穴23a，之後，進行消拖尾（desmear) 處理，以進行穿孔穴23a内部之樹脂殘渣之除去、及穿孔 5 穴23a之内壁面與絕緣層21a之表面211b之粗化。穿孔穴 23a之形成方法可採用二氧化碳雷射、激生分子雷射、UV-YAG雷射等。又，第2C〜2h圖中所示之步驟，兩個支持基 板之支持基板1，1、兩者是相同的，因此僅就一側之支持基 板1來圖示。 10 接著，如第2d圖所示，藉無電解電鍍法在穿孔穴23a 之底部形成厚0.5〜2/zm之無電解鎳鍍層221a。之後，藉 無電解銅鍍法在絕緣層21a之表面211b、穿孔穴23a之内 壁面及無電解鎳鍍層221a上形成厚〇.1〜〇.5/zm之無電解 鋼艘層222a。該無電解銅鍍層222a係在後續步驟之電鍍 15 處理中作為通電層發揮功能之種子層。又，各個無電解電 錢法中之一連串之處理可採用習知之方法。 接著’如第2e圖所示，在無電解銅鍍層222a上形成 抗餘圖案25。具體來說，於無電解銅鍍層222a上積層乾 薄膜抗I虫劑（dry film resist )，藉由以對應所希望之配線圖 2〇 案之曝光處理及顯影處理將該乾薄膜抗蝕劑圖案化，藉此 形成抗蝕圖案25。 接著，如第2f圖所示，以無電解銅鍍層222a作為通 電層’施以電銅鍍處理。藉此，於抗蝕圖案25之非遮罩領 域’使厚10〜3〇# m之電銅鍍層223a堆積成長。電銅鍍法 16 566065 玖、發明說明 可採用習知之利用酸式硫酸銅鍍液之方法。 接著’如第2g圖所示，使抗蝕圖案25剝離。作為剝 離/夜者可使用例如氫氧化鈉水溶液或有機胺系水溶液。 接著’如第2h圖所示，除去不覆蓋於電銅鍍層223a 5之無電解銅鍍層222a。具體來說，無電解銅鍍層222a係 矛J用例如過氧化氫及硫酸之混合水溶液或二氣化銅 (CuCl2 )水溶液等餘刻除去。這時，蝕刻液係與無電解銅鍍層 222a之露出部分及電銅艘層223a相同作用，不過如上所 述’無電解鋼鍍層222a之厚度較電銅鍍層223a之厚度薄 1〇很多’因此只有無電解銅鍍層222a之露出部分會先消失。 結果’具有無電解銅鍍層222a與電銅鍍層223&之配線圖 案22a在絕緣層21a之表面211b上形成圖案。 接著’以預定次數（例如6次）反覆第2c〜2h圖所示 之一連串步驟。結果，如第2i圖所示，支持基板1經由穿 15 孔23形成相互電性連接之6層配線圖案22a〜22f及6層絕 緣層21a〜21f。又，如前所述，由於也就另一側之支持基 板1'進行第2c〜2h之步驟，因此同樣在其表面經由穿孔23 形成有相互電性連接之6層配線圖案22a'及6層絕緣層 21a'。又，無電解鎳鍍層之形成亦可僅在最内層之絕緣層 20 21a，21a' 〇 之後，同樣如第2i圖所示，藉由在最外層之絕緣層 21f，21f'上印刷焊料抗蝕劑、施以曝光處理、顯影處理及加 熱硬化處理，形成具有開口部24a，24a'之罩面層24,24'。 更，在配線圖案22f，22f'上之因開口部24a，24a'而露出之部 17 566065 玖、發明說明 分，藉無電解細法在配線圖案22f，22f'上形成厚〇.5〜以 m之無電解鎳鍍層（未圖示）。 著士第2j圖所示，將在絕緣薄片'上之不作 為絕緣層21a，21a'使用之從支持基板露出之部分（亦及緣 P 20a’20a )切斷除去1此解除了積層支持基板之基 層狀態’而得到作為2個中間製品之多層配線基板 Υ1，ΥΓ 又緣4 20a，20a'之切斷除去，亦可伴隨支持基板n 之一部分之切斷。 在此僅就多層配線基板γι進行接下來之各步 驟之說 10明’當然多層配線基板ΥΓ情況亦相同。 ’係如第2k圖所示，於支持基板！之 裡面b上形成餘刻圖126。具體來說，在裡面lb上將乾 4膜抗姓y積層’藉由施以對應於所希望之钱刻圖案之曝 光处里及顯衫處理，將該乾薄膜抗姓劑圖案化，藉此而形 15 成I虫刻圖案26。 接者，如第21圖所示，藉餘刻在支持基板1上形成貫 通孔11。具體來說，支持基板i使用例如二氣化銅（ CuCl2)水‘夜、或過氧化氫與硫酸之混合水溶液等不溶解 環氧樹脂之餘刻液除去。結果，支持基板1上形成貫通孔 11又。又於穿孔23、穿孔穴23a之底之無電解鎳鍍層 221a (參照第2h圖）成為障壁金屬，未被蝕刻。 接著，如第2m圖所示，將蝕刻圖案26剝離。剝離液 可使用氫氧化納水溶液或有機胺系水溶液。 接著’藉無電解金鍍法，經由貫通孔11在露出之無電 18 玖、發明說明 解錄錢層22la上形成未圖示 屑。v 之厚度1〜5#m之無電解金鍍 ’無電解金It法之-連串處理可採用f知之方法。 接著，如第2n圖赫，從支持基板丨之裡㈣侧經 貝通孔11將1C晶片3封 曰乃^釘凌於最内層之絕緣層21a之裡 211 a，使JC晶片3之球電極31盘空π , 电往31與穿孔23經由無電解 金鍍層（未圖示）導通。 .、接者’同樣如第2η圖所示，將絕緣性樹脂注入產生於 貝通孔11與1C晶片3間之間隙，形成樹脂密封部32，藉 此密封該間隙。 曰 10 最後 同樣如第2η圖所示，在罩面層 24上搭載電容 器4。這時，電容器4之電極部41經由罩面層μ之開口 部24a而與最外層之配線圖案饥電性接合。藉此，即製 作出第1圖所示之晶片搭載基板XI。 上述多層喊基板Y1，Y1'之形成方法，可在對積層支 15持基板10利用絕緣薄片2〇,2〇'施以真空積層後，進行從第 3圖所示之在絕緣薄片20,2〇、之緣部2〇a，2〇a'上形成金屬鍍 膜50，一直到第2c〜2h圖之各步驟。藉由該金屬鍍膜5〇 , 則即使遇到增層積層體2之積層數很多、多次反覆穿孔23 形成時進行之/肖拖尾處理之情況時，由於緣部2〇a，2〇a、受 20到金屬鍍膜50保護，因此可更有效果地防止緣部2〇a，2〇a' 之破損或穿孔等之發生。又，金屬鍍膜5〇之構成材料可舉 銅或鎳等。 金屬鍍膜50亦可在進行第2d〜2f圖所示之無電解銅鍍 及電鍍銅鍍時，也對緣部20a，20a'進行同樣處理而形成於 19 566065 玖、發明說明 50而設置 緣部2〇a，2Ga、。如此，+需要為了形成金屬鑛膜 其他步驟，故可使作業效率提升。 卜 匈上述金屬鍍膜5〇之構成材料時，則可如 10 第^圖所示，於該金屬賴5G上更形成保護膜51後，進 行第2c〜2h之各步驟1由設置該保護膜5卜則即使在增 層積層體2之積層數很多、必須多次重複形成穿孔μ時^ 進行之種子層（無電解銅制）之㈣除去之情況，仍可 防止金屬制5G被_料，進而更有效果地防止緣部 20a’20a之破損或穿孔等之發生。又，作為保護膜η之構 成材料可舉聚四氟乙烯或聚丙烯等。 上述晶片搭憾板XI侧料2片支持基板U、積 層之積層支持基板10製作，不過亦可藉由在丨片支持基板 1上形成增層積層體2,搭載IC晶片3及電容器4來製作 。又，亦可替換1C晶片3與電容器4之搭載位置。更，可 15在經由貫通孔u將IC晶片3或電容器*搭載於增層積層 體2後，更設置研磨支持基板i之裡面化與^晶片3或 電容器4之步驟。 上述曰曰片格載基板XI之製造中，參照第2c〜2h圖說 明了藉半添加（semi-additive)法形成配線圖案22a，22a'之 20方法，不過本發明在形成配線圖案22a，22a'上亦可採用習 知之消去法或全添加（fulLadditive)法。 藉以上說明之製造方法所形成之晶片搭載基板χι，可 縮短1C晶片3與電容器4之距離。藉此，可減低電感，抑 制干擾之發生。 20 566065 玖、發明說明 藉由上述製造方法’可在支持基板1之表面lb形成增 層積層體2後進行1C晶片3之搭載，因此，用以圖增層積 層體2與ic晶片3之電性導通之位置組合就變得比較容易 進行。又，由於可在形成增層積層體2後進行ic晶片3之 5搭载，故可在確認增層積層體2適當地形成後再搭載Ic晶 片3 ’如此不會浪費ic晶片3，且實用性優異。更，支持 土板1 /、萵藉由除去1C晶片3之搭載範圍即可形成貫通孔 11 ’故支持基板1之剩餘部分具有與加強材同樣的功能。 因此’不需另外設置賦予剛性之步驟，作業效率很優異。 1〇 藉由將2片支持基板1，1、積層並進行增層積層體2,2、 之形成來作為積層支持基板10，可在加熱增層積層體2,2' 或支持基板1，1、時，緩和因兩者之熱膨脹率之差所導致之 彎曲。亦即，藉由將2片支持基板u'之裡面暫時接合， 則即使因一側之支持基板丨與形成於該支持基板表面之增 15層絕緣層2之熱膨脹率之差而產生了彎曲，但與該彎曲正 相反地，由於另一側之支持基板丨'與形成於該支持基板表 面之增層絕緣層2'之熱膨脹率之差也產生了彎曲，因此互 相抵銷。藉此可使封裝可靠性提升。 藉由將以貫通孔11搭載之IC晶片3與貫通孔U及增 20層積層體2間所產生之間隙以絕緣性樹脂密封，不僅可使 各配線間之絕緣性提升，且增加IC晶片3之搭載狀態下之 安定度。因此，1C晶片3與增層積層體2間之電性連接可 達到更高的可靠性。又，在將IC晶片3或電容器4經由貫 通孔11搭載於增層積層體2後，更進而研磨支持基板1之 21 566065 玖、發明說明 裡面lb、1C晶片3或電容器4,藉此可圖晶片搭載基板 XI全體之輕薄化。 接著，依據實施例更具體地說明本發明。 〔實施例1〕 5 (晶片搭載基板之製作） 準備2片厚〇.5mm、尺寸15〇χ 15〇mm之銅板作為支 持基板，並對各自形成增層積層體之表面施以脫脂、酸處 理及CZ處理。之後，將2片銅板以裡面相向之狀態重疊 ，再將之以2片厚50# m、尺寸200x 200mm之環氧樹脂 10薄片（SH-9味之素（味c〇素）製）夾持，使用真空積層在 130°C壓著2分鐘。更以170t：3分鐘藉由積層而在各銅板 表面形成絕緣層。 接著，使用二氧化碳雷射在各絕緣層上之預定位置形 成穿孔（直徑50 μ m)，並進行消拖尾處理。接著，在各穿 15 孔穴底形成厚1//m之無電解鎳鍍層。接著，在各絕緣層 及各無電解鎳鑛層上形成厚〇·3 # m之無電解銅鑛層。接下 來’在各無電解銅鍍層上將乾薄膜抗姓劑（商品名：RY_ 3040，曰立化成製）以預定圖案形成，一面將之遮罩，並 以之前業已形成之無電解銅鍍層作為通電層，形成電鍍銅 2〇 鍍層。將乾薄膜抗餘劑剝離後，以钱刻除去之前為乾薄膜 抗蝕劑所披覆之無電解銅鍍膜。之後，以170°C加熱60分 鐘，藉此形成配線圖案及穿孔。之後，將上述從形成絕緣 層之步驟到形成配線圖案及穿孔之步驟為止之一連_步驟 重複4次進行，藉此形成5層之配線構造。 22 566065 玖、發明說明 接著，藉網版印刷及微影成像法，在由5層形成之配 線構造上積層形成罩面層層。在罩面層之預定位置上設置 開口，以使最後形成之配線圖案之一部分面臨該罩面層。 接下來，經由該開口部在面臨之配線圖案上形成厚丨# m 5之無電解鎳鍍層，接著形成厚之金鍍層，藉此而形 成用以與外部端子連接之接地電極。在此形成之接地電極 係配置成對應於之後搭載之電容器之導電聯絡部配置。 接著，將未構成絕緣層且從形成於銅板表面之增層積 層體露出之環氧樹脂薄片切斷除去，藉此解除2片銅板之 1〇 積層狀態。 接著’在銅板裡面以預定圖案形成乾薄膜抗蝕劑（商 品名：NIT-50曰合莫同（日合七一卜製），一面將之 遮罩，一面使用二氣化銅（CuCl2)水溶液（關東化學製） 作為蝕刻液將銅板蝕刻，形成貫通孔。這時，由於穿孔六 15底形成之無電解鎳鍍層成為障壁金屬，因此穿孔未被蝕刻 。將乾溥膜抗蝕劑剝離後，經由該貫通孔在面臨之穿孔之 無電解鎳鍍層上形成厚3//m之金鍍層，藉此形成用以與 外部端子連接之接地（land)電極。在此形成之接地電極 係配置成對應於之後搭載之IC晶片之電極配置。 20 接著’厚〇.5mm之1C晶片在切斷成殼體尺寸後，以 收納於刖述貫通孔之形態，經由接地電極藉焊接接合搭載 於增層積層體。接著，以環氧樹脂密封IC晶片與貫通孔間 產生之間隙（商品名：U8434-6，納米克斯（于s ^夕只） 製）。又，電容器經由接地電極藉焊接接合搭載於增層積層 23 566065 玖、發明說明 體。 〔實施例2〕 (晶片搭載基板之製作） 準備2片厚〇.3mm、尺寸150x 150mm之不鏽鋼板作 5為支持基板，對形成增層積層體之表面各自施以脫脂、酸 處理及表面粗化處理。之後，將2片不鏽鋼板以各個裡面 相向之狀態重疊，並以2片厚50#m、尺寸200X 200mm 之環氧樹脂（商品名：SH-9味之素（味〇素））將之挾持 ’再使用真空積層以130°C壓著2分鐘。更，以i70°C積層 10 30分鐘，藉此於各不鏽鋼板之表面形成絕緣層。 接者，使用一氧化故雷射在各絕緣層上之預定位置形 成穿孔（直徑50/zm)，並進行消拖尾處理。接著，在各穿 孔八底形成厚l//m之無電解鎳錢層。接著，在各絕緣層 及各無電解鎳鍵層上形成厚〇.3#m之無電解銅鍍層。又， 15同時，在各環氧樹脂薄片之緣部（絕緣層以外之部分）上 進行無電解銅鍍，形成膜厚〇·3 μπχ之金屬鍍膜。接下來， 在各無電解銅鍍層上將乾薄膜抗蝕劑（商品名：RY-3〇4〇 ’曰立化成製）以預定圖案形成，一面將之遮罩，並以之 刖業已形成之無電解銅錢層作為通電層，形成電艘銅鍍層 20 。將乾薄膜抗蝕劑剝離後，以蝕刻除去之前為乾薄膜抗餘 劑所彼覆之無電解銅鍍膜。之後，以17(TC加熱6〇分鐘， 藉此形成配線圖案及穿孔。之後，將上述從形成絕緣層之 步驟到形成配線圖案及穿孔之步驟為止之一連串步驟重複 4次進行，藉此形成5層之配線構造。 24 566065 玖、發明說明 接著，藉網版印刷及微影成像法，在由5層形成之配 線構造上積層形成罩面層。在罩面層之預定位置上設置開 口，以使最後形成之配線圖案之一部分面臨該罩面層。接 下來，經由該開口部在面臨之配線圖案上形成厚丨# m之 5無電解鎳鍍層，接著形成厚之金鍍層，藉此而形成 用以與外部端子連接之接地電極。在此形成之接地電極係 配置成對應於之後搭載之電容器之導電聯絡部配置。 接著，將未構成絕緣層且從形成於不鏽鋼板表面之增 層積層體露出之環氧樹脂薄片切斷除去，藉此解除2片不 10 鏽鋼板之積層狀態。 接著，在不鏽鋼板裡面以預定圖案形成乾薄膜抗蝕劑 (商品名：NIT-40、曰合莫同（日合千一卜製），一面 將之遮罩，一面使用蝕刻液將不鏽鋼板蝕刻，形成貫通孔 。又，該蝕刻液為將50wt%之三氣化鐵（FeCl3)、63wt% 15之硝酸與36wt%之鹽酸以3 : 1 : 3 (=三氣化鐵：硝酸：鹽 酸）之比例混合之混合液。這時，由於穿孔穴底形成之無 電解鎳鍍層成為障壁金屬，因此穿孔未被蝕刻。將乾薄膜 抗蝕劑剝離後，經由該貫通孔在面臨之穿孔之無電解鎳鍍 層上’形成厚3#m之金鍍層，藉此形成用以與外部端子 2〇連接之接地電極。在此形成之接地電極係配置成對應於之 後搭載之1C晶片之電極配置。 接著，厚0.3mm之1C晶片在切斷成殼體尺寸後，以 收納於前述貫通孔之形態，經由接地電極藉焊接接合搭載 於增層積層體。接著，以環氧樹脂密封IC晶片與貫通孔間 25 566065 玖、發明說明 產生之間隙（商品名：U8434-6，納米克斯（于S y夕只） 製）。又，電容器經由接地電極藉焊接接合搭載於增層積層 體。 如以上之說明，藉由本發明，1C晶片與增層積層體之 5 位置組合變得較為容易，不僅可抑制肇因於增層積層體之 成品率所導致之1C晶片之浪費之發生，且不需另外設法賦 予剛性，可進行在效率及封裝性上優異之晶片搭載基板之 製造。又，該製造出之晶片搭載基板，由於1C晶片與電容 器間之距離縮小，因此電感變小，可減低干擾。 10 【圖式簡單說明】 第1圖是有關本發明之晶片搭載基板之截面圖。 第2a〜2η圖是顯示同一晶片搭載基板之製造方法之一 連串步驟之截面圖。 第3圖是顯示上述製造方法之一步驟之變形例之截面 15 圖。 第4圖是顯示上述製造方法之一步驟之另一變形例之 截面圖。 【圖式之主要元件代表符號表】 1…支持勒反 la…支持基板表面 lb···支持基板裡面 2…增層積層體 3…1C晶片 4…電容器 10…支持基板 ll···貫通孔 20…絕緣薄片 20a"·緣部 21a〜21f·· ·絕緣層 22a〜22f···配線圖案 26 566065 玖、發明說明 23…穿孔 23a…穿孔穴 24…罩面層 24a…罩面層之開口部 25…抗/触圖案 26···#刻圖案 31…球電極 32…樹脂密封部 41…電極部 50···金屬鍵膜 211 a〜211 f· ··絕緣層裡面 212a〜212f···絕緣層表面 221a…無電解鎳鍍層 222a…無電解銅鍍層 223a…電銅鑛層 242…罩面層表面 Xl···晶片搭載基板 Y1…多層配線基板 5l···保護膜 27Raiser, and GJ Vandentop, "Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric Constant Materials", [online], October 12, 2013, Intel Co. Η · Ρ ·, URL: 7 566065 玖, Description of Invention http://www.intel.com/research/silicon/BBULconferencefoils.p Reference 3: T. Shimoto, K. Kikuchi, H. Honda, K. Kata, KK Baba, and KK Matsui “High-Performance Flip- Chip BGA 5 based on Multi-Layer Thin-Film Packaging Technology ", Proceedings of the 2002 IMAPS, p.10-15. The technology disclosed in the above documents 1 and 2 is based on the 1C chip fixed to the supporting substrate in advance Since the multilayer wiring structure is formed by the layer-adding method, it is difficult to combine the positions of the 1C chip and the multilayer wiring structure. Furthermore, since a multilayer wiring structure is formed after the 1C wafer is fixed to the supporting substrate in advance, it is difficult to reuse the 1C wafer when the multilayer wiring structure is defective. That is, when the yield of the multilayer wiring structure is not 100%, there is a high possibility that the expensive 1C wafer is wasted. In addition, in the technique disclosed in Document 3, in order to reduce the distance between the IC chip and the capacitor 15, the support substrate must be completely removed at the end. If the supporting substrate is removed in this way, the substrate mounted as a wafer component lacks rigidity, and it becomes difficult to perform packaging or other mounting and dismounting. In addition, when a reinforcing material is provided on the surface of the uppermost layer of the multilayer wiring structure for the purpose of imparting rigidity to the wafer component mounting substrate excluding the supporting substrate, the work efficiency is not good because the number of process steps increases. In addition, since the wafer component mounting substrate must be processed after the 1C wafer is mounted, the 1C wafer may be damaged during the processing. [Explanation 3 Summary of the Invention Therefore, the object of the present invention is to provide electronic components with a base of 8 566065, a low inductance of the invention description board, and an electronic component that is excellent in position combination and practicability and excellent in work efficiency. Manufacturing method of mounting substrate. Another object of the present invention is to provide a wafer component mounting substrate manufactured by the method. 5 #The manufacturing method of the electronic material mounting substrate provided in the first aspect of the present invention, & contains a step of layering and laminating alternately forming a layered insulating layer and a layered wiring pattern on the surface of a metal supporting substrate; and Forming a through hole at the position where the electronic component on which the aforementioned support substrate is placed, a step of forming a hole for exposing the innermost layer of the insulating layer; and sealing the electrons in the innermost layer of the insulating layer through the aforementioned 10 through-holes of the supporting substrate Packaging steps for parts. According to this manufacturing method, it is possible to mount an electronic component after forming a laminated body on the surface of a support substrate. Therefore, it is relatively easy to combine the positions when the electronic component is mounted on the multilayer body. In addition, since it is possible to mount the electronic component after forming the laminated body, it is possible to mount the electronic component after confirming that the laminated body 15 is properly formed, so that the electronic component is not wasted and is excellent in practicality. Furthermore, since only the supporting substrate portion of the electronic component mounting range needs to be removed, the remaining portion of the supporting substrate has the same function as the reinforcing material. So it is rigid enough for packaging or other processing. Therefore, there is no need to separately provide a step for imparting rigidity, and work efficiency is excellent. 20 This manufacturing method preferably further includes a bifurcation step of sealing a gap generated around the electronic component with an insulating resin in the through hole after the packaging step. This can not only improve the insulation of each wiring room, but also increase the stability in the mounted state of electronic components. Therefore, the electrical connection between the electronic component and the laminated body can achieve higher reliability. 9 566065 发明, description of the invention manufacturing method, in which A benefits, +, and, before quoting the step of layering, further includes a temporary bonding step of temporarily bonding the inside of the two supporting substrates, and in the foregoing step of layering Later, before the hole forming step, the separation step of separating the two supporting substrates is further included, and the aforementioned step of laminating and stacking is preferably performed on the surface of each supporting plate. By this manufacturing method, when the laminated substrate is fired step by step to heat the supporting substrate or the insulating layer, the n caused by the difference between the thermal expansion coefficients of the two substrates can be alleviated. Bonding ', even if the bending occurs due to the difference in thermal expansion coefficient between the support substrate on the side and the build-up insulation layer formed on the surface of the support substrate, but this is exactly the same as 10, and The difference in the thermal expansion coefficient of the build-up insulating layer on the surface of the support substrate also causes warping, so they cancel each other out. This can improve package reliability. 15 The manufacturing method is performed in which the temporary bonding step is performed by sandwiching the two supporting substrates on two resin sheets fa1 having a size exposing the outer periphery of each supporting substrate, and vacuum laminating the two resin sheets under heating. Better. According to this manufacturing method, the support substrate 2 can be maintained in a bonded state without using an adhesive, and at the same time, for example, the two support substrates can be easily separated only by cutting the resin sheet exposed at the outer periphery. In addition, a part of the resin 20 sheet can be used as the innermost layer of the build-up insulating layer, and is excellent in work efficiency. This manufacturing method 'is preferably a plating step in which at least the aforementioned two resin flakes form a metal plating film on the exposed portion after the aforementioned temporary joining step. By this manufacturing method, in the build-up step, the surface roughening treatment is performed even when the build-up wiring pattern is formed on the build-up insulating layer. 10 566065 发明, the description of the invention The aforementioned metal film is not affected by the surface roughening treatment. Therefore, even in the step of laminating and stacking, even if the resin sheet forming a plurality of the aforementioned exposed portions is not damaged, the temporary bonding state of the two and two supporting substrates can be more stable and maintained. 5 In the manufacturing method, it is preferable that the aforementioned metal plating film is formed simultaneously with a wiring pattern formed on the aforementioned innermost layer of an insulating layer. According to this k-method, the formation of the metal bond film can be performed with a better working efficiency. In this manufacturing method, it is preferable that the aforementioned film-forming step further includes forming a protective film "film-forming step" on the above-mentioned metal 10 metal to form a protective film different from the metal plating film. By this manufacturing method, it is possible to prevent the metal plating film from being removed when, for example, a subtraction method is used when forming a wiring pattern. This prevents damage to the resin sheet in the exposed portion and maintains the temporary bonding of the two supporting substrates in a more stable state. 15 A suitable embodiment of the present invention further includes a polishing step of grinding the electronic component in the innermost layer of the insulating layer without the increased wiring pattern and / or the supporting substrate. With this manufacturing method, it is possible to reduce the size and thickness of the entire electronic component mounting substrate. The electronic component mounting substrate provided by the second aspect of the present invention includes a metal support substrate, a multilayer build-up body that alternately forms a layered insulation layer and a layered wiring pattern on the surface of the support substrate. And the electronic component mounted on the laminated body, the support substrate has a through hole at the position where the electronic component is placed, and the electronic component is mounted on the innermost layer through the through hole of the support substrate. No. 11,566,065 of the increased insulation layer, the description of the invention does not form the inside of the increased wiring pattern. It is preferable that the electronic component mounting substrate is a gap generated around the electronic component by sealing the through hole with an insulating resin. This electronic component mounting substrate is based on the aforementioned electronic component being a 1C chip, and it is preferable that a capacitor is mounted on the surface of the buildup wiring pattern in the buildup insulation layer of the outermost layer. This can shorten the wiring distance between the 1C chip and the capacitor. Therefore, the inductance can be reduced and the occurrence of noise interference can be suppressed. In a suitable embodiment of the present invention, the metal constituting the supporting substrate is preferably a thermal expansion coefficient of 1 ppm / K in a temperature range of -65 c to 280 c and 10 to 20 PPm / K. By using a support substrate formed of a metal having such a thermal expansion coefficient, the difference between a layered laminate having a relatively large thermal expansion coefficient and an electronic component having a relatively small thermal expansion coefficient can be further reduced. Therefore, it is possible to achieve higher reliability in the electrical connection between the laminated body and the electronic component. The metal is selected from 42 alloys, molybdenum, Kehua alloy, 15 steel, 42 steel, titanium, copper / steel / clad copper, non-steel, copper, iron, nickel, and stainless steel. This metal is preferred. Brief Description of Drawings Fig. 1 is a cross-sectional view of a wafer mounting substrate according to the present invention. Figures 2a to 2n are cross-sectional views showing a series of steps of one of the manufacturing methods of the same wafer-mounted substrate. Figure 疋 ", page shows a cross-sectional view of a modified example of one of the steps of the above-mentioned manufacturing method. Figure 4 shows a cross-sectional view of another modified example of one of the steps of the above-mentioned manufacturing method. 12 566065 发明 Description of Invention C Implementation [Mode] FIG. 1 is a cross-sectional view of a wafer mounting substrate X1 related to an embodiment of the present invention. The wafer mounting substrate XI includes: a support substrate 1 having a surface 1a and an inner surface 1b, and a laminated body 2 formed on the surface 1a and an IC. The wafer 3 5 and the capacitor 4. The supporting substrate 1 has a through hole U for accommodating the 1C wafer 3. The through hole 11 is formed from the inner surface lb of the supporting substrate j to the surface la according to the shape of the 1C wafer 3 mounted thereon. The overall shape of the support substrate 丨 is, for example, a plate shape, and the thickness is preferably the same as the thickness of the IC wafer 3. The shape or thickness is not limited to this. The support substrate 1 is formed of a metal. The metal preferably has a thermal expansion coefficient of 1 ppm / K to 20 ppm / K in a temperature range of -65 ° c to 28 ° c. The material constituting the metal may be, for example, 42 alloy, molybdenum, Kehua alloy, Steel, 42 due to steel, titanium, copper / due to steel / clad Materials, stainless steel, copper, iron, nickel, aluminum, etc. The laminated body 2 includes: an insulating layer 21 a to 21 f, wiring patterns 22 a to 22 f, perforations 23, and an over-coat layer 24. Insulation The layer 21a is laminated in a state in which the inner surface 211a is bonded to the surface la of the supporting substrate, and the wiring pattern 22a is formed on the surface 212a of the insulating layer 21a. Furthermore, the insulating layer 21b is formed between the inner layer 211b and the insulating layer 21a. A layer is formed when the surface 212a is bonded, and a wiring pattern 22b is formed on the surface 212b of the insulating layer 2ib. Furthermore, as shown in FIG. I, the insulating layers 21c to 21f are formed in the same order as the insulating layer 21b. The number of layers of the laminated layer body 2 is not limited to the above, but can be arbitrarily determined as required. 13 566065 发明 Description of the invention It is preferable to use a general thermosetting resin as a constituent material of the insulating layers 21 a to 21 f. Examples of thermosetting resins include polyimide resins, epoxy resins, bis-butylene diimide resins, maleimide resins, cyanate resins, and thermosetting polyelongation resins. Phenyl ether resin, polydiphenyl ether resin, 5 fluorine-containing resin, and Aromatic polyester-based liquid crystal polymer resin, etc. The constituent materials of the insulating layers 21a to 21f are not limited to those mentioned above. The wiring patterns 22a to 22f are formed by forming a pattern on each of the insulating layers 21a to 21f. The wiring patterns between the layers (such as wiring pattern 22 and wiring pattern 22b, etc.) are electrically connected by perforations 23. The perforations 23 are formed simultaneously with the wiring patterns 22a to 22f by the method described below. The cover layer 24 is It is provided to protect the wiring pattern 22f, which is a pattern formed on the outermost insulating layer 2f, and has an opening portion 24a so that a part of the wiring pattern 22f faces the cover layer 24. As the material constituting the cover layer 24, the resin described above as the constituent material of the insulating layers 21a to 21f, or an epoxy acrylate resin used for a solder protective layer in general can be used. The 1C wafer 3 has a large number of ball electrodes 31 as shown in FIG. 1 and is mounted on the inner surface 211a of the innermost insulating layer 21a through the through hole π from the back surface 1b of the support substrate 1. The main part of the 1C chip 3 series is composed of general semiconductor element materials such as silicon, and exhibits a thermal expansion coefficient of 30 to 3.5 ppm / K. The ball-counting electrodes 31 are arranged in a grid array shape on the surface 3a of the 1C wafer 3 to form a ball grid array. The ball electrode 31 is formed of gold or a solder of a predetermined composition. In addition, a gap generated around the IC chip 3 in the through hole 11 is sealed with an insulating resin resin to form a resin sealing portion 32. Examples of the insulating resin used for the resin sealing include: epoxy resin, polyimide resin 14 566065 玖, description of the invention, isocyanate resin, and the like. As shown in FIG. 1, the capacitor 4 has a plurality of electrode portions 4 and is mounted on the outermost insulating layer plus the surface from the surface 242 side of the cover layer 24 through an opening. The number or capacity of the capacitors 4 can be arbitrarily determined as needed. Hereinafter, referring to FIGS. 2a to 2n, a method suitable for manufacturing the wafer mounting substrate X1 according to this embodiment by the build-up method will be described. When manufacturing the wafer mounting substrate XI, first, as shown in FIG. 2a, each surface la, la 'of the two support substrates 1, 1, is subjected to degreasing, oxygen treatment, and / or surface roughening treatment (for example, by using The support substrate formed of copper is cz process, etc.), and then two support substrates 1 and Γ are overlapped with the inside lb, lb, facing each other to form the support substrate 10. Next, as shown in FIG. 2b, the supporting substrate 10 is sandwiched between two insulating sheets 2 formed of an insulating resin and having a size of 15 exposed from the outer peripheral portion 1 C 1 C ′ of each supporting substrate 1, 1 ′. Between 20 and 20 minutes, vacuum lamination is applied at a predetermined temperature and a predetermined time. As a result, the two support substrates i, i 'can maintain the laminated state. Examples of the insulating resin constituting the insulating sheets 20 and 20 'are the same as the constituent materials of the insulating layers 21a to 21f which are not disclosed above. Therefore, portions of the insulating sheets 20, 20 'covering the respective supporting substrates 1, 1' function as the innermost 20 insulating layers 21a, 21a '. In addition, based on the simplification of the illustration, FIG. 2b shows the state where the support substrate 1 corresponding to one wafer mounting substrate XI has been vacuum-laminated, but it can also be summarized, for example, corresponding to a plurality of wafer mounting substrates. The large and small supporting substrates are vacuum-laminated, and then divided into a plurality of wafer mounting substrates after performing the steps described below. 15 566065 (ii) Description of the invention Next, an enlarged view of a main part of the base support substrate 10 on which the insulating layers 21a and 21a 'are formed is shown in Fig. 2c. As shown in the figure, a perforated hole 23a is formed at the predetermined location of the insulating layer 21a, and then a desmear process is performed to remove the resin residue inside the perforated hole 23a and the inner wall surface of the perforated 5 hole 23a. And roughening of the surface 211b of the insulating layer 21a. The formation method of the perforation hole 23a may be a carbon dioxide laser, an excimer laser, a UV-YAG laser, or the like. In addition, in the steps shown in Figs. 2C to 2h, the two supporting substrates 1, 1, which support the substrate are the same, so only the supporting substrate 1 on one side is illustrated. 10 Next, as shown in FIG. 2d, an electroless nickel plating layer 221a having a thickness of 0.5 to 2 / zm is formed on the bottom of the through hole 23a by the electroless plating method. Thereafter, an electroless steel plating layer 222a having a thickness of 0.1 to 0.5 / zm is formed on the surface 211b of the insulating layer 21a, the inner wall surface of the perforated cavity 23a, and the electroless nickel plating layer 221a by the electroless copper plating method. The electroless copper plating layer 222a is a seed layer that functions as a current-carrying layer in the electroplating process in the subsequent steps. In addition, a series of processes in each of the electroless money methods can be performed by a conventional method. Next, as shown in Fig. 2e, a residual pattern 25 is formed on the electroless copper plating layer 222a. Specifically, a dry film resist is laminated on the electroless copper plating layer 222a, and the dry film resist pattern is subjected to an exposure process and a development process corresponding to a desired wiring pattern 20 Thus, the resist pattern 25 is formed. Next, as shown in Fig. 2f, electroless copper plating is performed using the electroless copper plating layer 222a as a conductive layer '. As a result, an electric copper plating layer 223a having a thickness of 10 to 30 m in a non-masked area of the resist pattern 25 is deposited and grown. Electric copper plating method 16 566065 玖, description of the invention The conventional method using an acid copper sulfate plating solution can be adopted. Next, as shown in Fig. 2g, the resist pattern 25 is peeled. As the peeler / nighter, for example, an aqueous sodium hydroxide solution or an organic amine-based aqueous solution can be used. Next, as shown in Fig. 2h, the electroless copper plating layer 222a which is not covered with the electric copper plating layer 223a 5 is removed. Specifically, the electroless copper plating layer 222a is removed by a short time using, for example, a mixed aqueous solution of hydrogen peroxide and sulfuric acid or an aqueous solution of copper dichloride (CuCl2). At this time, the etching solution has the same function as the exposed portion of the electroless copper plating layer 222a and the electric copper plating layer 223a, but as described above, the thickness of the electroless steel plating layer 222a is much smaller than the thickness of the electric copper plating layer 223a. The exposed portion of the electrolytic copper plating layer 222a will disappear first. As a result, the wiring pattern 22a having the electroless copper plating layer 222a and the electric copper plating layer 223 & is patterned on the surface 211b of the insulating layer 21a. Then 'repeats a series of steps shown in Figures 2c to 2h a predetermined number of times (for example, six times). As a result, as shown in FIG. 2i, the support substrate 1 forms six layers of wiring patterns 22a to 22f and six layers of insulation layers 21a to 21f electrically connected to each other through the through-holes 23. In addition, as described above, since the steps 2c to 2h are also performed on the supporting substrate 1 'on the other side, six layers of wiring patterns 22a' and 6 layers which are electrically connected to each other are also formed on the surface through the through holes 23. The insulating layer 21a '. In addition, the electroless nickel plating layer may be formed only after the innermost insulating layers 20 21a, 21a ′ 〇, as shown in FIG. 2i, by printing solder resist on the outermost insulating layers 21f, 21f ′. The surface treatment layer 24, 24 'having openings 24a, 24a' is formed by applying an exposure treatment, a development treatment, and a heat hardening treatment. Furthermore, the exposed portions 17a, 566065 on the wiring patterns 22f, 22f 'are exposed by the openings 24a, 24a'. According to the description of the invention, the thickness of the wiring patterns 22f, 22f 'is formed by a thickness of 0.5 to 0.5 by electroless thinning. m of electroless nickel plating (not shown). As shown in Figure 2j, the part on the insulating sheet 'that is not used as the insulating layer 21a, 21a' and exposed from the supporting substrate (also the edge P 20a'20a) is cut and removed. 1 This releases the laminated supporting substrate. In the base layer state, the multilayer wiring board Υ1, ΥΓ which is two intermediate products is obtained by cutting and removing 4 20a, 20a ', and may also be accompanied by cutting of a part of the support substrate n. Here, only the following steps will be described for the multilayer wiring substrate γm. Of course, the same applies to the multilayer wiring substrate ΥΓ. ’As shown in Figure 2k, on the support substrate! The inside figure b is formed on the inside b. Specifically, on the inside lb, a dry 4 film anti-surname y layer is laminated, and the dry film anti-surname agent is patterned by applying an exposure place corresponding to a desired money engraved pattern and a shirt display, whereby And shape 15 into I insect carved pattern 26. Then, as shown in FIG. 21, a through-hole 11 is formed in the support substrate 1 at a later time. Specifically, the support substrate i is removed by using a solution of insoluble epoxy resin such as copper dichloride (CuCl2) water 'night or a mixed aqueous solution of hydrogen peroxide and sulfuric acid. As a result, the through holes 11 are formed in the support substrate 1 again. The electroless nickel plating layer 221a (see Fig. 2h) at the bottom of the perforation 23 and the perforation hole 23a becomes a barrier metal and is not etched. Next, as shown in FIG. 2m, the etching pattern 26 is peeled. As the peeling solution, an aqueous sodium hydroxide solution or an organic amine-based aqueous solution can be used. Next, by the electroless gold plating method, unillustrated crumbs are formed on the exposed non-electrical layer 18a through the through hole 11 and the description of the descriptive money layer 22la. The electroless gold plating with a thickness of 1 to 5 # m is used in the electroless gold It method-a series of processes can be adopted. Next, as shown in FIG. 2n, the 1C wafer 3 is sealed from the inner side of the support substrate through the through hole 11 to 211 a in the innermost insulating layer 21a, so that the ball electrode of the JC wafer 3 The 31 plate is empty π, and the electrical connection 31 and the through hole 23 are conducted through the electroless gold plating layer (not shown). "Receiver" also injects an insulating resin into the gap between the through hole 11 and the 1C wafer 3 as shown in Fig. 2n to form a resin sealing portion 32, thereby sealing the gap. Finally, as shown in FIG. 2n, a capacitor 4 is mounted on the cover layer 24. At this time, the electrode portion 41 of the capacitor 4 is electrically connected to the outermost wiring pattern via the opening portion 24a of the cover layer µ. Thereby, the wafer mounting substrate XI shown in FIG. 1 is produced. The above-mentioned method for forming the multilayer substrates Y1, Y1 'can be performed by laminating the substrate 10 to the laminated support 15 using the insulating sheets 20, 2' and vacuum-laminating them. 〇 、 Metal plating film 50 is formed on the edge portions 20a and 20a ′, and the steps up to the steps 2c to 2h are shown. With the metal plating film 50, even when the number of layers of the laminated body 2 is large, and the perforation 23 is performed repeatedly when the perforation 23 is formed, the edge portions 20a, 20a Since it is protected by 20 to the metal plating film 50, it is possible to more effectively prevent the edges 20a, 20a 'from being damaged or perforated. The constituent material of the metal plating film 50 may be copper or nickel. The metal plating film 50 may also be formed at 19 566065 缘 when the electroless copper plating and electroplated copper plating shown in Figs. 2d to 2f are performed on the edge portions 20a, 20a '. 20a, 2Ga ,. In this way, + requires other steps to form a metal ore film, which can improve work efficiency. When the constituent material of the metal plating film 50 described above is used, as shown in FIG. 10, the protective film 51 can be formed on the metal 5G, and then the steps 2c to 2h are performed. 1 The protective film 5 is provided. In general, even if the number of layers of the laminated layer 2 is large, and the perforation of the seed layer (made of non-electrolytic copper) is repeatedly performed when the perforation μ has to be repeatedly formed multiple times, the metal 5G can still be prevented from being charged, and further It is more effective to prevent the edges 20a'20a from being damaged or perforated. As a constituent material of the protective film?, Polytetrafluoroethylene, polypropylene, or the like can be mentioned. The above-mentioned wafer support board XI is made of two supporting substrates U, and a laminated supporting substrate 10, but it can also be produced by forming an laminated laminate 2 on the supporting substrate 1 and mounting an IC chip 3 and a capacitor 4. . The mounting position of the 1C chip 3 and the capacitor 4 may be replaced. Furthermore, after mounting the IC wafer 3 or the capacitor * on the build-up multilayer body 2 through the through hole u, a step of polishing the internal surface of the supporting substrate i and the wafer 3 or the capacitor 4 can be provided. In the above-mentioned manufacturing of the chip carrier substrate XI, the 20 methods of forming the wiring patterns 22a and 22a 'by the semi-additive method have been described with reference to FIGS. 2c to 2h. However, the present invention forms the wiring patterns 22a and 22a. You can also use the conventional elimination method or the fulLadditive method. The wafer mounting substrate χ formed by the manufacturing method described above can shorten the distance between the 1C wafer 3 and the capacitor 4. This can reduce the inductance and suppress the occurrence of interference. 20 566065 发明 Description of the invention By the above-mentioned manufacturing method, the 1C wafer 3 can be mounted on the support substrate 1 on the surface 1b of the support substrate 1, and thus the 1C wafer 3 can be mounted. The combination of positions for sexual conduction becomes easier. In addition, since the IC chip 3 5 can be mounted after the build-up multilayer body 2 is formed, the IC chip 3 can be mounted after confirming that the build-up multilayer body 2 is properly formed. Excellent. Furthermore, the support soil plate 1 and the lettuce can form through holes 11 ′ by removing the mounting range of the 1C wafer 3, so the rest of the support substrate 1 has the same function as the reinforcing material. Therefore, there is no need to provide a step for imparting rigidity, and the work efficiency is excellent. 10 By stacking two support substrates 1, 1, and forming a multilayer laminate 2, 2, as the multilayer support substrate 10, the laminates 2, 2 'or the support substrates 1, 1 can be laminated and heated. , When, to ease the bending caused by the difference in thermal expansion between the two. That is, by temporarily bonding the insides of the two supporting substrates u ′, even if a difference occurs in the thermal expansion coefficient between the supporting substrate on one side and the 15-layer insulation layer 2 formed on the surface of the supporting substrate, However, in contrast to the bending, the difference in thermal expansion coefficient between the supporting substrate ′ ′ on the other side and the build-up insulating layer 2 ′ formed on the surface of the supporting substrate also causes bending, so they cancel each other out. This can improve package reliability. By sealing the gap generated between the IC chip 3 mounted in the through-hole 11 and the through-hole U and the 20-layer laminated body 2 with an insulating resin, not only the insulation between wirings can be improved, but also the IC chip 3 can be increased. Stability in the mounted state. Therefore, the electrical connection between the 1C chip 3 and the build-up laminate 2 can achieve higher reliability. In addition, after the IC chip 3 or the capacitor 4 is mounted on the build-up laminated body 2 through the through hole 11, the support substrate 1 21 566065 研磨 is further polished, the lb, 1C chip 3 or the capacitor 4 in the description of the invention can be diagrammed. The overall thickness of the wafer mounting substrate XI is reduced. Next, the present invention will be described more specifically based on examples. [Example 1] 5 (Fabrication of wafer mounting substrate) Two copper plates with a thickness of 0.5 mm and a size of 150 x 150 mm were prepared as supporting substrates, and the surfaces on which the build-up layers were formed were each subjected to degreasing and acid treatment. And CZ processing. After that, the two copper plates were stacked facing each other inside, and then they were sandwiched by two pieces of 50 # m thick, 200x 200mm epoxy 10 sheets (made by SH-9 Ajinomoto (Ajinomoto)). , Using vacuum lamination at 130 ° C for 2 minutes. Furthermore, an insulation layer was formed on the surface of each copper plate by lamination at 170t: 3 minutes. Next, a carbon dioxide laser was used to form a perforation (50 μm in diameter) at a predetermined position on each of the insulating layers, and a smearing treatment was performed. Next, an electroless nickel plating layer having a thickness of 1 // m is formed at the bottom of each of the 15 holes. Next, an electroless copper ore layer having a thickness of 0.3 m was formed on each of the insulating layers and each electroless nickel ore layer. Next, on each electroless copper plating layer, a dry film anti-surname agent (trade name: RY_ 3040, manufactured by Rihwa Kasei) was formed in a predetermined pattern, and one side was masked, and the electroless copper plating layer formed before was used as The current-carrying layer forms an electroplated copper 20-plated layer. After the dry film resist is peeled off, the electroless copper plating film previously coated with the dry film resist is removed with a coin. After that, it is heated at 170 ° C for 60 minutes to form a wiring pattern and perforations. After that, the above steps from the step of forming the insulating layer to the step of forming the wiring pattern and the perforation are repeated four times, thereby forming a five-layer wiring structure. 22 566065 发明 Description of the invention Next, by screen printing and lithography imaging, a wiring layer structure formed of 5 layers is laminated to form a cover layer. An opening is provided at a predetermined position of the cover layer so that a part of the wiring pattern formed last faces the cover layer. Next, an electroless nickel plating layer with a thickness of # m 5 is formed on the facing wiring pattern through the opening portion, and then a thick gold plating layer is formed, thereby forming a ground electrode for connection to an external terminal. The ground electrode formed here is arranged so as to correspond to the arrangement of the conductive contact portion of the capacitor mounted later. Next, the epoxy resin sheet exposed from the build-up laminate formed on the surface of the copper plate without forming an insulating layer was cut and removed, thereby releasing the 10-layer laminated state of the two copper plates. Next, a dry thin film resist (trade name: NIT-50, Hemotong (made by Nichichi Co., Ltd.)) was formed in a predetermined pattern on the inside of the copper plate, while masking it, and using an aqueous solution of copper dichloride (CuCl2). (Manufactured by Kanto Chemical Co., Ltd.) The copper plate is etched as an etchant to form through holes. At this time, the electroless nickel plating layer formed on the bottom of the perforation 6-15 becomes the barrier metal, so the perforation is not etched. After the dry film resist is peeled off, The through hole forms a 3 // m thick gold plating layer on the electroless nickel plating layer facing the perforation, thereby forming a land electrode for connection with an external terminal. The ground electrode formed here is configured to correspond to The electrode arrangement of the IC chip to be mounted afterwards. 20 Then the 1C chip with a thickness of 0.5mm is cut into the size of the case, and then it is stored in the through-hole described above, and is mounted on the build-up laminated body through welding by ground electrodes. Next, the gap generated between the IC chip and the through hole was sealed with an epoxy resin (trade name: U8434-6, manufactured by Nanometers (produced by s)). The capacitor was mounted by soldering via a ground electrode. Buildup layer 23 566065 玖, description of the invention. [Example 2] (Fabrication of wafer mounting substrate) Two stainless steel plates with a thickness of 0.3mm and a size of 150x150mm were prepared as support substrates. The surface is respectively subjected to degreasing, acid treatment and surface roughening treatment. After that, two pieces of stainless steel plates are overlapped with each other facing each other, and two pieces of epoxy resin (trade name: SH with a thickness of 50 # m and a size of 200X200mm) are used. -9 Ajinomoto (Ajinomoto)) hold it 'and use vacuum lamination for 2 minutes at 130 ° C. Furthermore, lamination at i70 ° C for 10 30 minutes to form an insulating layer on the surface of each stainless steel plate Then, a perforation laser is used to form perforations (50 / zm in diameter) at predetermined positions on each insulating layer, and the anti-smearing treatment is performed. Next, non-electrolysis with a thickness of 1 // m is formed on each of the perforations. Nickel coin layer. Next, an electroless copper plating layer with a thickness of 0.3 # m was formed on each of the insulating layers and each of the electroless nickel bond layers. At the same time, at the same time, at the edges of each epoxy resin sheet (except the insulating layer) Part) is electroless copper plated to form a film thickness of 0.3 μπχ It is a plating film. Next, a dry thin film resist (trade name: RY-3040) is formed in a predetermined pattern on each electroless copper plating layer, and it is masked on one side, and then The electroless copper coin layer that has been formed is used as the current-carrying layer to form the electroplated copper plating layer 20. After the dry film resist is peeled off, the electroless copper plating film previously covered by the dry film resist is removed by etching. After that, 17 (TC is heated for 60 minutes to form wiring patterns and perforations. After that, a series of steps from the step of forming an insulating layer to the steps of forming wiring patterns and perforations is repeated 4 times to form a 5-layer wiring structure. 24 566065 发明 Description of the Invention Next, by screen printing and lithography imaging, a wiring layer formed of 5 layers is laminated to form a cover layer. An opening is provided at a predetermined position of the cover layer so that a part of the wiring pattern finally formed faces the cover layer. Next, an electroless nickel plating layer with a thickness of 5 m thick is formed on the wiring pattern facing through the opening portion, and then a thick gold plating layer is formed, thereby forming a ground electrode for connection with an external terminal. The ground electrode formed here is arranged so as to correspond to the arrangement of the conductive contact portion of the capacitor mounted later. Next, the epoxy resin sheet which was not formed of the insulating layer and was exposed from the laminated body formed on the surface of the stainless steel plate was cut and removed, thereby releasing the laminated state of the two stainless steel sheets. Next, a dry thin film resist (trade name: NIT-40, Yumotsu (Nippon Chiyuki)) was formed in a predetermined pattern on the stainless steel plate, and the stainless steel plate was etched with an etchant while masking it. Through-holes are formed. In addition, the etching solution is composed of 50% by weight of iron trioxide (FeCl3), 63% by weight of 15 nitric acid and 36% by weight of hydrochloric acid in a ratio of 3: 1: 3 (= three gas iron: nitric acid: hydrochloric acid) The mixed liquid is mixed in the proportion. At this time, the electroless nickel plating layer formed at the bottom of the perforated hole becomes the barrier metal, so the perforation is not etched. After the dry film resist is peeled off, the electroless nickel facing the perforation through the through hole A gold plating layer with a thickness of 3 # m is formed on the plating layer, thereby forming a ground electrode for connecting with the external terminal 20. The ground electrode formed here is configured to correspond to the electrode configuration of the 1C chip mounted later. Next, the thickness After cutting the 0.3mm 1C chip into the case size, the chip is housed in the aforementioned through hole, and is mounted on the build-up laminate by soldering through the ground electrode. Next, the IC chip and the through hole are sealed with epoxy resin 25 566065 hairpin Describe the gap produced (trade name: U8434-6, made by Nanometer (only in Sy)). In addition, the capacitor is mounted on the build-up multilayer body by welding and bonding via the ground electrode. As described above, with the present invention, The 5-position combination of the 1C chip and the build-up laminate becomes easier, which not only suppresses the waste of the 1C chip due to the yield of the build-up laminate, but also does not need to try to give rigidity. Manufacture of a wafer-mounted substrate that is excellent in efficiency and packaging. In addition, the manufactured wafer-mounted substrate has a smaller distance between the 1C chip and the capacitor, so that the inductance is reduced and interference can be reduced. Fig. 1 is a cross-sectional view of a wafer mounting substrate according to the present invention. Figs. 2a to 2n are cross-sectional views showing a series of steps of a manufacturing method of the same wafer mounting substrate. Fig. 3 is a modification example showing a step of the above-mentioned manufacturing method. Figure 15 in section. Figure 4 is a sectional view showing another modification of one of the steps of the above manufacturing method. [Representative symbol table of main elements of the drawing] 1 ... Reverse la ... Supporting substrate surface lb ... Supporting substrate inside 2 ... Laminated laminate 3 ... 1C wafer 4 ... Capacitor 10 ... Supporting substrate 11 ... Through-hole 20 ... Insulation sheet 20a " Edge 21a ~ 21f ... ·· Insulation layer 22a ~ 22f ··· Wiring pattern 26 566065 玖, Description of the invention 23 ... Perforation 23a ... Perforation hole 24 ... Overlay layer 24a ... Opening part 25 of cover layer ... Anti-touch pattern 26 ... Pattern 31 ... ball electrode 32 ... resin sealing portion 41 ... electrode portion 50 ... metal key film 211a to 211 f ... inside of the insulating layer 212a to 212f ... surface of the insulating layer 221a ... electroless nickel plating layer 222a ... no Electrolytic copper plating layer 223a ... electric copper ore layer 242 ... cover layer surface X1 ... wafer mounting substrate Y1 ... multilayer wiring substrate 5l ... protection film 27