TW577150B - Method of fabricating a DRAM cell - Google Patents

Abstract

A dynamic random access memory (DRAM) cell is disclosed. First, a dual damascene trench is formed in a silicon substrate, and the dual damascene trench is composed of an upper first trench and a lower second trench. Then, a buried plate is formed in the silicon substrate to surround the second trench. A node dielectric is formed on a surface of the buried plate, and a collar dielectric is formed on portions of the silicon substrate in the second trench. A buried strap is formed in the second trench, and a trench top oxide (TTO) is formed on the buried strap. Finally, a threshold voltage of a metal oxide semiconductor (MOS) transistor of the memory cell is adjusted, and a source, a drain and a gate of the MOS transistor are formed.

Description

577150 Amendment No. 92100573 V. Description of the Invention (1) The technical field to which the invention belongs / f The invention provides a method for manufacturing a dynamic random access memory (DRAMk memory ceu), especially a method including dual mosaic Method for manufacturing vertical transistor of trench. Prior art DRAM memory cel 1 is composed of a metal oxide semiconductor (MOS) transistor and a capacitor in series. MOS The crystal includes a gate and a first and a second doped region. The first and second doped regions are identical in structure. The operation of the transistor is defined as a source or a source according to its function. Drain. With the gradual development of very large scale integration (VLSI), the size of the component design is shrinking. At present, a method using a vertical transistor design to improve the integration density More and more attention has been paid. Compared with the traditional transistor, the source, gate and drain are placed horizontally. The vertical M0S transistor uses the thick, gate and source electrodes. A vertical placement 'to form a vertical channel, so the lateral area of the MOS transistor can be greatly reduced to effectively increase the integration of the semi-conductor components. Please refer to Figures 1 to 5, and Figures 1 to 5 are examples. Schematic diagram of a method for making a memory cell of a DRAM using known technology. As shown in FIG.

Page 6 577150 Case No. 92100573 — Revised Year 5. Description of the invention (2) There is a substrate 12 and a pad stack 16 composed of an oxygen layer 18 and a silicon silicon layer 2 0. On the substrate 12. Firstly, a trench (t r e n c h) 1 4 is formed on the substrate 12 by the conventional yellow light process 4 of the cutting process. Next, an arsenic si 1 i cate glass (ASG) diffusion technology is used to form a buried electrode (not shown) at the bottom of the trench 14, and then a dielectric layer (not shown) is sequentially formed on the surface of the buried electrode. (Shown), a neck oxide layer (c0 lar ox i de) 2 2 and a buried conductive strip (bur i ed st rap) 2 8. Among them, the buried conductive tape 28 is used as a storage electrode (s ^ 〇ragen 〇de), and the dielectric layer and the neck oxide layer 22 are used to isolate the buried electrode and the storage electrode to form a capacitor. structure. After s, as shown in Fig. 2, an insulating layer is formed in the trench 14, that is, the so-called trench top oxide (TTO) 32. The TT0 layer 3 2 covers the buried conductive strip 28 and exposes a part of the sidewall of the trench i 4, which is used as a vertical channel of the vertical transistor. Next, a tilted ion implantation process is performed, using an inclination angle to the silicon substrate. 2 The surface and the exposed trench 14 sidewalls are subjected to an ion implantation 23, 23 to adjust the initial voltage of this vertical transistor . As shown in FIG. 3, a deposition process is then performed to sequentially form a gate oxide layer 3 4 and a gate polycrystalline silicon layer (using P0lySiliCon) 36, which are stacked on the surface of the semiconductor wafer 10 . Subsequent-shallow trench isolation (sti) process ’% shown in Figure 4, at a position overlapping the part of this trench 14, using conventional yellow light and etching techniques to form _ shallow trench (shaU〇w 第

As shown in Figure 5, 'then the conventional yellow light, money carving, ion implantation, thermal diffusion and other techniques are used to form the gate structure, source 40, and drain side walls of the vertical transistor. 46. A bit line contact 52 and a bit iine 54 are used to complete the production of the vertical transistor and its peripheral circuit components. Although the traditional vertical transistor has greatly reduced the lateral area of the M0S transistor, the limit line width (CD) of the trench is still limited by the exposure resolution and cannot be further reduced, especially when the line width of the trench is required to be 0.1 Processes below / zm are often difficult to control. In addition, in the fabrication of the lower capacitor structure, the neck oxide layer 22, the buried conductive tape 28, and the TT0 layer 32, it is often necessary to use polyrecess etch multiple times, and when the trench is The line width is very small. The remaining polysilicon height is often difficult to accurately control, which may easily cause the height of the subsequent neck oxide layer 22 and TT0 layer 32 to vary. Therefore, the gate channel length will be inconsistent, which will affect the electrical performance of the device , Leading to a decline in product reliability. Summary of the Invention

577150 I-Case No. -921 Calendar 73 '9 Qiaoyue 9; Article iL _ V. Description of the invention (4) The main purpose of the present invention is to provide a method for manufacturing a vertical transistor including a double inlaid trench to overcome the conventional Know the line width (CD) issues encountered by technology. In a preferred embodiment of the present invention, the method of the present invention is to first provide a silicon substrate, and then form a double town embedded trench formed by a first and a second trench in the Shixi substrate. dua 1 damascen i ng trench). A buried plate is then formed in the silicon substrate in the second trench, and a node dielectric and a dielectric layer are formed on the surface of the buried electrode and the stone substrate in the second trench, respectively. A neck dielectric. A buried strap is formed in the second trench, and a trench top ox ide (ττο) is formed over the buried trench. Finally, the threshold voltage (threshold vo It age) of the MOS transistor of the memory cell is adjusted, and the source / non-electrode and gate of the MOS transistor are formed. Because the present invention uses a double inlaid trench structure, that is, a first trench with a larger opening is formed first, and then a side wall is formed at the bottom of the first trench. With this side wall as a cover, an opening is then formed. The small second trench can therefore further reduce the line width of the second trench without being limited by the exposure resolution. In addition, compared with the conventional technology, the first trench of the present invention has a larger line width. Therefore, in the process of etching the first trench, it can have better control and form a uniform first trench. Trench 'so the gate in the first trench will have a more stable channel length,

577150 92 ·!. ::. :: _Case No. 92100573 _ Year Month ~ Day ____ V. Description of the invention (5) Effectively improve the reliability of the product. Embodiments Please refer to FIGS. 6 to 12. FIGS. 6 to 12 are schematic diagrams of a method for manufacturing a DRAM memory cell according to the present invention. As shown in FIG. 6, a semiconductor wafer 100 has a Shi Xi substrate 11 0 ′ and a liner layer (p a d s t a c k) 1 1 2 on the Shi Xi substrate 110. First, a pattern is formed in the cushion layer 112 by a traditional yellow light process, and a patterned cushion layer 11 2 is used as a mask, and then a first trench is etched on the silicon substrate 110 ( trench) 11 8. Among them, the Shi Xi substrate 110 is a single crystal Xi wafer, a Si 1 icon-on-insulator (SOI) substrate, an epitaxy silicon substrate, or other semiconductor materials that can be used in semiconductor processes. The substrate and the cushion layer 11 2 further include a stone oxide layer π 6 and a nitrogen stone layer 11 4, and the line width CD 2 of the first trench 1 1 8 is approximately 0 · 2 5 in m and the depth is approximately 4 From 0 to 600 nm, as shown in FIG. 7, a chemical vapor deposition method is used to deposit a silicon nitride layer (not shown) on the surface of the semiconductor wafer 100, and then an isotropic etching process is performed. The silicon nitride layer is etched to form a sidewall 1 2 0 around the sidewall of the first trench ii 8. Subsequently, using the patterned cushion layer π 2 and the side wall 120 as a mask, the Shi Xi substrate 11 at the bottom of the first trench 118 is further etched to form a second trench 122 in the silicon substrate 110. The wide CD3 is about 0.1 / zm and the depth is about 400 to 600 nm.

Page 10 577150 t No. 92100573 V. Description of the invention (6) Bottom 1 picture shows' Using a Shishen Shixi glass (ASG) diffusion technology, Yu Shixi is based on the buried chip piate of the first type Qiu Soi i24 Around the bottom of nl a / Λ Γ is used as an electric and capacitive upper electrode. Next, a silicon nitride layer is formed on the surface of the Shixi substrate ^ ^ 1 8 and the surface of the first trench 1 2 (not filled with a transition layer (not shown) in the second trench 122, and the Tibetan electrode 124 is tangent Then, perform a wet process, for example, #Dendroic acid / fluid, to remove the silicon nitride layer not covered by the transition layer to expose the surface of the silicon substrate u0 at the upper neck portion of the second trench 112. Among these, Utilizing arsenic-silicon glass (ASG) diffusion technology, the technique of forming an N-type doped buried electrode 124 in a silicon substrate is well known to those skilled in the art, so it will not be repeated here. In addition, The layer may be a photoresist layer or a doped polycrystalline silicon layer. After removing the transition layer, a high temperature oxidation process is performed, for example, rapid thermal oxidation is performed after heating to about 900 to 100 (rc). In a rapid thermal process (RTP) environment containing water vapor, a first oxide film (not shown) is formed on the surface of the silicon nitride layer, wherein the first oxide film and the silicon nitride layer can be used together as a capacitor. The dielectric layer 126 is exposed at the same time as the upper neck portion of the second trench 112. A second oxide film with a thickness of about 200 to 300 Angstroms ', which is thicker than the first oxide film, is also formed on the surface of the silicon substrate n 〇, and is also called a neck oxide layer 1 2 8' in order to reduce the parasitic leakage current (paras 丨tic leakage). After that, the sidewall 120 is removed. As shown in FIG. 9, a doped polycrystalline silicon is filled in the second trench 122.

92 .: 577150 mH 92100573 V. Description of the invention (7) The Shi Xi layer 'forms a buried conductive strip (bur ie (j strap) 130, which is used as a storage electrode). Among them, if the above When the transition layer is a doped polycrystalline silicon layer, the transition layer does not need to be removed, and becomes a part of a buried conductive strip (buriedstrap) 130. Then, a chemical vapor deposition process is performed on the semiconductor An oxide layer (not shown) is selectively deposited on the wafer surface 100, so that the thickness of the oxide layer at the bottom of the first trench 8 is greater than other positions, and then an etching process is performed to remove part of the oxide ^, leaving A part of the oxide layer located at the bottom of the first trench 丨 丨 8, which is the oxide layer on the trench (trench t〇p 〇χΗε, [το) 132. Among them, 'this TTO layer 132 is approximately aligned with the first The bottom of the trench 118 has a thickness of about 10 nm to 100 nm, and preferably 30 nm to 40 nm. Then, as shown in FIG. 10, an inclined ion implantation process is performed to position the gate channels on the sidewall of the trench 118. To plant to The whole gate is started and pressed. Then a vertical ion implantation process is performed to form the source i & and the drain 135. Among them, the thermal diffusion method can also be used to diffuse the buried conductive strips outward. To form the source electrode 134, or to directly use the inclined ion implantation to form the source electrode 134 and the drain electrode 135. In the absence, the "car wafer" 100 is placed in a -heating furnace tube (not shown), Press down the gas ^ Use a dry or wet oxidation method to use a dry or wet oxidation method to oxidize the surface of the silicon substrate as the gate insulating layer (not shown) and then use a chemical vapor phase: fill a polycrystalline silicon or The doped polycrystalline silicon layer is subjected to a planarization process to form a gate conductor 36.

Page 12 577150 --Ά 92100573 --year Η q 倏 正 5. Description of the invention (8) As shown in Figure 11, a shallow trench isolation (STI) process is performed. A shallow low trench (not shown) is formed at a position that partially overlaps the first trench 118 by conventional yellow light and etching techniques, and its depth must exceed ττ〇 layer 1 32 to expose a portion of the buried conductive With 13〇. Then, an insulating material, usually a silicon oxide compound, is filled in the shallow trench, and a planarization process is used to form a shallow trench isolation layer 138. The semiconductor wafer 100 is then planarized to complete this shallow trench isolation process. As shown in FIG. 12, a polycrystalline silicon layer (not shown) is then deposited on the semiconductor wafer 100, and a photo-etching process (PEP) is performed, and a portion of the polycrystalline silicon layer is removed to form a word. Word line 140. Thereafter, a dielectric layer 142, a bit line contact plug 144, and a bit line 146 can be further formed to complete the production of the DRAM memory cell and its peripheral circuit components. As this part can be easily completed by those skilled in the art, and there are many optional designs, for example, a metal silicide layer, a top protective layer and a protective layer can be formed on and around the bit line 146, respectively. The spacer is not described in detail here. It can be known from the above description that the present invention uses a double-inserted trench structure, that is, a first trench with a large opening is formed first, and then a sidewall is formed at the bottom of the first trench, and a sidewall is used as a cover, and then A second trench with a small opening is formed, so the line width of the second trench can be further reduced without being limited by the exposure resolution.

Page 13 577150 Case No. 92100573

V. Description of the invention (9) Compared with the previous reduction of the second trench, it helps to reduce the larger line width (CD 2 recess etch) below 0.1 m // to avoid the reliability of the gate in the subsequent trench. . The above is only the scope of patent coverage. Amend

This is a comparatively equal and modified technology of the present invention. The dual-mosaic trench structure of the present invention can be advanced in line width without being limited by exposure resolution, and there will be process development. In addition, since the first trench 1 1 8 has a polysilicon recessed etching process (p0ly when manufacturing the lower capacitor structure, the gate length that can have better height control is affected, so the second trench will have a more Stable channel length and effective improvement of product embodiments. Any application according to the present invention shall belong to the patent of the present invention. 577150 _ Case No. 92100573_ Year Month Day __ Simple illustration of the diagrams. Schematic diagram of a method for making a memory cell for a DRAM for a conventional technology. Figures 6 to 12 are schematic diagrams of a method for making a DRAM memory cell for the present invention.: 5 :: ¾ Explanation of symbols: 10 semiconductor wafer 12 silicon substrate 14 Ditch 16 Hard cover curtain layer 18 Oxygen layer 20 Nitrogen silicon layer 22 Neck oxide layer 28 Buried conductive tape 32 TTO layer 34 Gate oxide layer _ 36 Gate conductive layer 40 Ion-doped region 41 Ion doping: region 42 Shallow trench isolation layer 46 Dielectric layer 52 Plug 54 bit line 100 Semiconductor wafer 110 Shi Xi substrate 112 Liner layer 114 Nitrogen silicon layer 116 $ Xiang layer 118 First trench 120 Side wall 124 Upper electrode 126 Trench oxide layer 132 on the polysilicon layer 130 dielectric layer 134 source electrode 128 collar oxide

577150 Case No. 92100573 Q-j 'year ^ Month and month Amendment Brief description of the drawing 135 Drain 136 Polycrystalline silicon layer 138 Shallow trench isolation layer 140 Word line 142 Dielectric layer 144 Plug 146 bit line Page 16 577150 Case number 92100573 Amendment

Page 4

Claims (1)

577150 Case No. 92100573 VI. Application Patent Scope 1. A method for making a memory cell (memory cel 1) of a dynamic random access memory (DRAM), which is ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ In the substrate, and the double mosaic trench is formed by one of the first trench and a second trench in the silicon substrate, the thin layer in the second trench (plate); ^ ^ Μ € ^ ^-t ^ ^ f > f (node dielectric); the col lar dielectric in the second channel of the class; forming a bured strap in the second channel;. · · :: ....:. .....;: ....... On top of a buried trench forming a trench top oxide (TTO); ..--* ',. 1.. :.. · Adjust the starting voltage of the MOS transistor of the memory sheet (thresh ο 1 d..................... .: • ...... ..:: '·...,' ''................................. ... ...,.. voltage); •-... .... ...-. ./../: ... " Source for forming the MOS transistor And drain;. And ._ - 'is formed of the MOS transistor to the gate of the first trench. 2. If the method of making a patent application item 1, the method of forming the dual damascene trench further comprises the following steps: forming a patterned pad layer (pad stack) on the surface of the silicon substrate; 577150 Case No. 92100573 6. The scope of the patent application is based on this. The patterned pad layer is used as a mask to etch the silicon substrate into the silicon substrate. It is in the first _ Huashi side sound week · failure to use patterning The liner layer and the sidewall are used as a mask to etch the bottom of the tomb at the bottom of the first trench. .: ............... · ............ The liner layer is composed of an oxide layer and a silicon nitride layer stacked on top and bottom, and the sidewall sub-system is composed of a silicon nitride compound. 4 · If you apply for the first level of the scope of the United States Department of Science ^ use a bangxi Xiangli (arsenic si 1 icat wide formed.............. .. …….; ·:. ·. Λ,:: ... Λ .. ......... .-. .. * _, '_': 5 The manufacturing method layer of item 1 and the method of the electrode dielectric layer further include the following steps: .....:.:-;-·. ;;........ 1. ：,: ........ On the silicon-based watch and the double setting | fill a transition layer in the second trench and make the top of the transition layer approximately equal to the top of the buried electrode Tangent alignment; removing the dielectric layer not covered by the transition layer to expose the silicon substrate located in the upper half of the second trench and the first trench; and performing a ^^ oxidation process to simultaneously A first oxide film and an I surface are respectively formed on the surface of the dielectric layer and the surface of the silicon substrate exposed in the dual damascene trench. Page 18 577150 _ Case No. 92100573 _ Month and Day __ VI. The first oxide film is thick and the second oxide film; wherein the first oxygen The film and the dielectric layer are used as the electrode dielectric layer, and the second oxide film is used as the neck dielectric layer. The transition layer is a photoresist layer, and the oxidation process is performed to completely remove the transition layer. For example, in the method of claim 5, the transition layer is composed of a doped polycrystalline silicon. Let ’s consider it as part of the buried conductive tape. 8. The manufacturing method of item 1 in the scope of patent application, wherein the buried conductive tape system is composed of a doped polycrystalline silicon. The manufacturing method further includes an inclined ion implantation process for adjusting the starting voltage, and a vertical ion implantation process for forming the source and the drain of the MOS transistor. The manufacturing method of the first scope of the patent, wherein the source and the drain of the MOS transistor are simultaneously formed in an ion implantation process. 1 1. The manufacturing method of the first scope of the patent application, wherein the The gate method also includes the following Steps of: a first conductive layer fills the dual damascene trench; Page 19 577150-Amendment No. 92100573 _ Sixth, the scope of the patent application for a shallow trench isolation (sTI) process to form at least one shallow trench isolation in the silicon substrate to isolate the memory cell Forming a second conductive layer on the surface of the broken substrate, and performing photo-etching-process (PEP) to remove a portion of the second conductive layer; wherein the first conductive layer is used for As the gate of the transistor, the second conductive layer after a while is used as a word line (w rd 1 ine) of the dynamic random access memory (DRA M). 1 2. The manufacturing method according to item 1 in the scope of the patent application, wherein the silicon substrate system comprises a single crystal wafer and a stone-clad insulation (si 1 ic 〇n _ 〇n-insu 1 at 〇r, SOI) substrate. , Or an epitaxy substrate. 13. —A method for manufacturing a memory cell (memory ce 1 1) of a dynamic random access memory (drAM), which includes the following steps: A silicon substrate is provided, and a patterned surface is formed on the surface of the silicon substrate. Pad stack; using the patterned rough layer as a mask to etch the broken substrate so as to form the first trench on the silicon substrate; and forming a sidewall around the sidewall of the first trench ( spacer); using the patterned pad layer and the sidewall as a mask to etch the silicon substrate at the bottom of the first trench to form the second trench in the silicon substrate; the inside of the second trench A buried electrode is formed in the Shi Xi substrate. Page 20 577150 __case number 92100573_a car q_day_correction__ VI. Patent application scope plate); forming a dielectric layer on the silicon substrate and the surface of each of the trenches; filling in the second trench A transition layer with the top of the transition layer approximately tangent to the top of the buried electrode; removing the dielectric layer not covered by the transition layer to expose the silicon substrate located in the upper half of the second trench; Performing an oxidation process to form a first oxide film on the surface of the dielectric layer, and forming a second oxide film with a thickness greater than that of the first oxide film on the surface of the Shi Xi substrate exposed in the second trench; Removing the sidewall; forming a buried conductive strip (buried strap) in the second trench; forming a trench top oxide (TTO) over the buried conductive strip; removing the liner layer; forming A source and a drain of the MOS transistor; and a gate of the MOS transistor is formed in the first trench t. 1 4 · = The manufacturing method of item 13 in the scope of patent application, wherein the pad layer is composed of an oxide layer and a silicon nitride layer stacked on top and bottom, and the sidewall sub-system is composed of a silicon nitride compound . 577150 _ Case No. 92100573_ Year Month Date _ Amendment 6. The application of patent snake perimeter surgery. ^ ¾ The oxygen-dielectric-pole-dielectric neck of the cell should be filled with its electricity bill, and the method of remembering the cell and the cell should be used as the memorandum for the purpose of the item. 3 1 When it is the first item, use the film around. Fan Lihua ’s oxygen special electric power second, please refer to the application should be as soon as possible, ο 6 1 The film layer is the layer of the later system. After passing through the layer, the whole method is completed. The progress of the system is 31. The chemical system of the oxygen system is beneficial and specialized, please apply resistance as light 1 8. The manufacturing method according to item 13 of the scope of patent application, wherein the transition layer is made of a doped polycrystalline silicon The structure is used as a part of the buried conductive tape. 19 • The manufacturing method of item 13 in the scope of patent application, further comprising a tilt-type ion implantation process for adjusting the initial voltage of the MOS transistor. 20. The manufacturing method according to item 13 of the scope of patent application, wherein the source and the drain of the MOS transistor are formed simultaneously in an ion implantation process. 2 1. The manufacturing method according to item 13 of the scope of patent application, wherein the method of forming the gate electrode further comprises the following steps: filling a first conductive layer in the first trench; Page 22 577150 _Case No. 92100573_ Years and Months Amendment_ 6. Apply for a shallow trench isolation (STI) process to form at least one shallow trench isolation in the silicon substrate to isolate the memory cell; Forming a second conductive layer on the surface of the silicon substrate; and performing a photo-etching-process (PEP) to remove a portion of the second conductive layer; wherein the first conductive layer is used as The gate of the MOS transistor, and the etched second conductive layer is used as a wordline of the dynamic random access memory (DRAM). Page 23