TW591376B - System and method for detecting server failure and the restoring of the same - Google Patents

Abstract

There is provided a system for detecting server failure and the restoring of the same, which is suitable for a server and includes an event signal interception module and a power control circuit. The event signal interception module receives a system signal and sends a counter reset signal to the power control circuit based on the system signal. The power control circuit includes a counter which is decremented according to a time unit. When the power control circuit receives the counter reset signal, the counting value of the counter is reset to a first predetermined value. When the counter equals to a third predetermined value, the power of the server is turned off and the server is reset.

Description

591376 V. Description of the invention (1) The present invention relates to a server fault detection system and method, and particularly to a system and method for detecting and recovering a server fault by automatically recovering the faulty server. In recent years, due to the vigorous development of the network, the system management work (M IS) of the overall network system has become increasingly important. At the same time, how to maintain and provide a stable and normal server (Ser v er) at any time and place Working conditions have also become an important issue. In addition, due to the formation of the concept of a global village, long-distance, multinational services, and information services anytime and anywhere have become common work patterns. And in the middle of the night or in the absence of system administrators, if the server temporarily fails, such as improper user operation or system software, etc., the server must be waited for when the server fails. Network management personnel perform troubleshooting and other processing, which in turn causes server service interruption and affects the overall service quality of the system. However, in many cases, the server crash is caused by the detailed design problems of the system software itself, or the user's improper access to the server, and the server can be recovered only by shutting down / booting the server again. Normal service. Therefore, in such a situation that the server can be resolved by simply restarting the server, how to shorten the time from the server crashing to restarting has become another important issue. In view of this, the main object of the present invention is to provide a server that can automatically restart the server when it is down, so as to facilitate the detection and recovery of the restarted service of the failed server. System and method for waiting for server failure, thereby reducing

0506-6768TWf; MRS90-003; y i anhou.ptd page 4 591376 V. Description of the invention (2) Loss incurred. In order to achieve the above object, the system and method for detecting and recovering a server failure provided by the present invention can be achieved. The system for detecting and recovering a server failure according to the embodiment of the present invention is applicable to a server. The system for detecting and recovering a server failure includes an event signal interception module and a power control circuit. The event signal interception module receives a system signal and sends a counter reset signal to the power control circuit according to the system signal. The power control circuit may include a counter that is decremented with a unit time. When the power control circuit receives the counter reset signal, it resets the count value of the counter to the first predetermined value, and when the count value is equal to the third predetermined value, During the air strike, the server power will be turned off and the server will be restarted. In addition, when the count value is equal to the third predetermined value, a fault occurrence signal is also output at the same time to notify the system management personnel. Among them, the system signal can be an idle event signal from an operating system module, and the power control circuit is an independent power control circuit and can be arranged on the motherboard or interface card of the server. In order to make the above-mentioned objects, features, and advantages of the present invention clearer and easier to understand, a specific embodiment is described below in detail with the accompanying drawings as follows: Figure 1 shows an embodiment according to the present invention Schematic diagram of the system architecture of the detection and recovery server failure system.

0506-6768TWf; MRS90-003; y i anhou.ptd Page 5 591376 V. Description of the invention (3) Figure 2 shows a flowchart of a method for detecting and recovering a server failure according to an embodiment of the present invention. Explanation of symbols 1 0 ~ operating system module; 2 0 ~ event signal interception module; 3 0 ~ power control circuit; 3 counter; S 1 0 0, ..., S 1 0 8 ~ operation steps. EXAMPLES Next, examples of the present invention will be described in detail with reference to accompanying drawings. FIG. 1 is a schematic diagram of a system architecture of a fault detection and recovery server system according to an embodiment of the present invention. Referring to FIG. 1, a fault detection and recovery server system according to an embodiment of the present invention includes an operating system module 10, an event signal interception module 20, and a power control circuit 30. The power control circuit 30 is an independent power control circuit that controls the server on / off and can control the power on / off ability. The power control circuit 30 can be configured on the motherboard or interface card of the server (not shown). on. The power supply control circuit 30 includes a counter 31, and the counter 31 has a count value of a first predetermined value, and after each predetermined unit time, the count value is subtracted from a second predetermined value. Among them, the first predetermined value is larger than the second predetermined value. For example, the initial value (the first predetermined value) of the counter 31 is 1 8 0, and the value is subtracted every 1 second (the predetermined unit time) 丨 (the second

0506-6768TWf; MRS90-003; yianhou.ptd page 6 591376 V. Description of the invention (4) Prescribed value). The operating system module 10 can be an operating system (Operating System) installed in the server, such as Windows or Linux® or other operating systems. When the central processing unit (CPU) of the server has nothing to process > processing, then the operating system module 10 will issue a system signal, such as an Idle Event signal, to the overall server system for power Management (Power Management) program. The event signal interception module 20 may be a circuit or a driver (river), which is used to intercept and receive the system signal sent by the operating system module 10, and output a reset signal to the power control according to the received system signal. Circuit 30. ° ° When the power control circuit 30 receives the counter reset signal, it resets the count value of the counter 31 to the initial value (the first predetermined value). On the other hand, when the counter 31 of the power control circuit 30 When the count value decreases to a third predetermined value with time, for example, the 0 (represents that the feeder has not sent a system signal for a period of time 疋; if the signal is an idle event signal, it represents the server's The CPU is down or has been busy (this situation is extremely unlikely)), so °, the electrical source control circuit 30 will turn off the server's power and restart the server, and will output a fault An occurrence signal, such as Pager, is used to notify system administrators that the server has failed. A next 'FIG. 2 shows a flowchart of a method for detecting and recovering a server fault according to an embodiment of the present invention. Referring to FIG. 丨 and FIG. 2 at the same time, the operation flow of the embodiment of the present invention will be described as follows.

0506-6768TWf; MRS90-003; yi anhou.ptd

591376

First, as in step SI 00, the count value of the counter 31 in the power control circuit 30 is reduced by one every second (predetermined unit time) (a second predetermined value). Then, as in step 31〇2, it is determined whether the count value is equal to zero (third, a predetermined value). If the count value is not equal to zero, then in step S1〇4, it is determined whether an event signal interception module 2 has been received. 〇 One of the counter reset signals sent. If the power control circuit 30 does not receive the counter reset signal, it directly returns to the procedure of step = S / 0 〇; and if the power control circuit 30 receives the counter reset signal, it proceeds to step s0 0 , Reset the count ^ of the counter 3 丨 to 180 (the first predetermined value), and then continue to the procedure of step §100. On the other hand, if the count value is equal to zero in step 5102, then in step S108, the power control circuit 30 turns off the power of the server, restarts the server, and outputs a fault. Signals (not shown in Figure 2) ', such as Pager, to notify system administrators. Therefore, with the system and method for detecting and recovering a server failure provided by the present invention, when the server is down, the administrator and the server can be automatically restarted at the same time to facilitate the failed server ^ Restart in the shortest time to restore service, thereby reducing losses due to server outages. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can 'do some changes and retouching' without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. °

Claims (1)

591376 VI. Scope of patent application 1. A system for detecting and recovering server faults, applicable to a server, the system includes: an event signal interception module for receiving a system signal, and according to the system signal A counter reset signal is sent out; and a power control circuit for receiving the counter reset signal, the power control circuit includes: a counter having a count value of a first predetermined value, after each predetermined unit time, Subtract a second predetermined value from the count value, reset the counter value to the first predetermined value when the power control circuit receives the counter reset signal, and when the count value is equal to a first predetermined value When the predetermined value is three, power off one of the servers and restart the server. 2 · The system described in item 1 of the scope of patent application, which further includes an operating system module for outputting the system signal. 3. The system according to item 1 of the scope of patent application, wherein the power control circuit further comprises outputting a fault occurrence signal when the count value is equal to the third predetermined value. 4. The system according to item 1 or 2 of the patent application scope, wherein the system signal is an Idle Event signal. 5. The system according to item 1 of the scope of patent application, wherein the power control circuit is configured on a motherboard of the server. 6. The system according to item 1 of the scope of patent application, wherein the power control circuit is configured on an interface card of the server. 7. The system according to item 1 of the scope of patent application, wherein the first both 0506-6768TWf; MRS90-003; y i anhou.ptd page 9 591376 6. The scope of patent application The set value is greater than the second set value. 8. The system described in item 1 of the scope of patent application, wherein the third predetermined value is zero. 9. A method for detecting and recovering a server failure, comprising the following steps: subtracting a second predetermined value from a count value of a counter after each predetermined unit time; When the signal is set, the count value is set to a first predetermined value; and when the count value is equal to a third predetermined value, a power source of a server is turned off, and the server is turned on again. 10. The method according to item 9 of the scope of patent application, further comprising receiving a system signal and sending the counter reset signal according to the system signal. 11. The method according to item 10 of the patent application scope, further comprising an operating system module outputting the system signal. 1 2. The method according to item 9 of the scope of patent application, further comprising outputting a fault occurrence signal when the count value is equal to the third predetermined value. 1 3. The method according to item 10 or 11 of the scope of patent application, wherein the system signal is an Idle Event signal. 14. The method according to item 9 of the scope of patent application, wherein the counter is arranged on a power control circuit. 1 5. The method according to item 9 of the scope of patent application, wherein the first predetermined value is greater than the second predetermined value. 0506-6768TWf; MRS90-003; yianhou.ptd Page 10 591376 6. Scope of patent application 1 6. The method described in item 9 of the scope of patent application, wherein the third predetermined value is zero. 17. The method according to item 14 of the scope of patent application, wherein the power control circuit is configured on a motherboard of the server. 18. The method according to item 14 of the scope of patent application, wherein the power control circuit is configured on an interface card of the server. 0506-6768TWf; MRS90-003; yianhou.ptd Page 11