TWI231994B - Strained Si FinFET - Google Patents

Strained Si FinFET Download PDF

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TWI231994B
TWI231994B TW092107789A TW92107789A TWI231994B TW I231994 B TWI231994 B TW I231994B TW 092107789 A TW092107789 A TW 092107789A TW 92107789 A TW92107789 A TW 92107789A TW I231994 B TWI231994 B TW I231994B
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silicon
strained
layer
germanium
central body
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TW092107789A
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TW200421611A (en
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Shu-Tong Chang
Shi-Hao Hwang
Chee-Wee Liu
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Univ Nat Taiwan
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

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  • Thin Film Transistor (AREA)

Description

1231994 九、發明說明： 【發明所屬之技術領域】 本案係-種場效電晶體，尤指應用於解決元件 遇到物理極限的問題。可使元件密度增加，電流變大，速度變快s。 【先前技術】 鰭形場效電晶體（FinFET)的好處之一為通道不需要摻雜 (doping)，當電晶體往小尺寸縮小時，這個特性就變得很重要了。 換句話說，沒有摻雜的通道讓閘極更能控制臨界電壓 voltage)。另一個優點是這個鰭（^⑴可以报窄，這個特性意味著 在鰭（fin)的區域沒有能夠不受閘極的控制。在此種元件因&當元 件關掉時，載子在沿源極到汲極，沒有產生漏電流的路徑]^此 功率耗損很小。 而在應變矽（strained Si)的金氧半電晶體場效電晶體(Metal
Oxide Semiconductor Field Effect Transistor，M0SFET)中，電 子與電洞的遷移率（mobility)已被證實有增加的效果，應變矽現 有的方法’是利用矽成長於鬆弛(relaxecl)矽鍺層上。此鬆弛的矽 鍺層可長在SOI (silicon-on-insulator)的基板上，稱為 SGOI(silicon-on-SiGe-on insulator，或者傳統的矽基板（bulk
Si)。但均證實可增強P型及N型金氧半場效電晶體的速度。事實 上，Intel已將應變矽技術用於其⑽⑽製程節點（techn〇1〇gy n〇de) 中。 (註Intel的技術是利用bulk Si的基板。） 本發明即結合上述兩種元件的優點，設計出應變矽鰭形場效 電晶體(Strained Si FinFET)結構，此電晶體可以使元件縮小， 並k升元件的電流驅動力’突破傳統的物理極限。 【發明内容】 1231994 本案係為-種結合應_與鰭式場效電晶體的新型 里 包含：絕緣層上石夕（Si on insulator，s〇I)基底；一石夕射 用以產生應變U繞補中心體的應财，使 a 向增加遷移率，此鰭形應變矽可以調整矽鍺中心沪 ，办 _制應變的大小；-氧化層；—複晶科，極^極^全^ 極）；以及源極無極在鰭形通道兩端，形成場效電晶體結構屬甲1 根據上述構想’獅應變柯如下财式得到 S0I(S1l=n on insulator)基底上成長矽鍺層，然後將矽： /、下之SOI的紗層透過微影、姓刻或其他可能之方式一起钮^法： 中心體之結構，此時再成切，圍繞销中'讀㈣成元件1 道。當石夕錯中心體的高度遠大於底層石夕的厚度，且S0I基底之⑽ 巧底，間在中：體^度f 10〜_m内時’是可 2 (free sliPplng)(麥考文獻！），則矽鍺中心體 (relaxed)，此時圍繞矽鍺中心體之矽磊晶 ^為 I， strain的應變石夕。其詳細圖解說明見施例說明。為凡王又她❿ —當補中心體的高度遠小於底層石夕的厚度，則石夕錯中 完全應變（strained) ’此時此時圍繞石夕錯中心體石 orth—c strain的應變石夕。其詳細圖解說明見‘:為叉 其他可能的情況端視石夕錯中心體的鬆弛 ί下將使圍繞在補中心體上的應變石鳩層介於上Γ兩 電子Γίΐ述構想’在該圍繞在補中"體的應變科載子可為 加速Ϊ據上述構想’該應㈣所受之應變可使載子在傳輸方向增 根據上述構想，複晶矽閘坧rnn1v ^ 或P+ P〇ly _。 間極(poly 她），可為n+ poly gate 1231994 【實施方式】 圖一其係本案提出之應變矽鰭形場效電晶體的結構示意圖， 其中主要單元係由如圖所示之SOI (silicon on insulator，絕緣 層上石夕）1、應變矽鰭2、氧化層3、複晶矽閘極電極4及源極5 與汲極電極6所完成。其中A-A’為應變矽鰭2在垂直通道方向的截 面，如圖二所示。對應於圖二的應變矽鰭形結構製作，其製作步 驟如圖三所示。 對應名知之鰭形矽場效電晶體，其載子的等效遷移率 (effective mobility)與等效電場的關係如圖四所示。電子與電 洞均遵照universal mobility的曲線。 /在圖一中用新型的應變矽（s1：rained Si)結構來取代傳統的鰭 幵矽（Fin Si)，而新型的應變矽（strained Si)結構與其A-γ截面 面圖如圖二所示，若當内層矽鍺中心體之高度（H)及寬度 Ϊίί料厚度Tl(13)大很多，以致秒錯中心體為鬆弛(relaxed) 盘^ ’而周圍的石夕為應變（s1：rained)的狀態。因應變矽的遷移 而應變補形場效電晶體的速度也較快。Relaxation 百刀比在熱平衡下，可用下式估計： relaxati〇n=H/(H+Ti) 矽鍺8因埋層氧切層上之剌上成長鬆弛㈣axed)的 侧的糊、秒11、石夕12,所以W獨t服 計下(WaIH{yn、T4(16)較無關係，因此在Η夠大的正常元件設 鍺中心體周圍之^幾可以幾乎完全relaxed，圍繞其石夕 道，而得到的载子遷銘aln ’則用此stralned Si做為通 進一步了 率增加。如圖五的單位晶胞關說明，可 了解應_形成的機制與遷移率增加的原因。 假設兩材財帥晶格随㈣且时錯减生，因此平行 1231994 界面的晶格常數與較厚的材料幾乎相同，在矽鍺中心體寬度在 10〜ΙΟΟμηι内，則矽（1)與s〇I之氧化層是自由滑動（斤沈 slipping)(詳見參考文獻G· KastnerandG〇sele，，，Principles〇f strain relaxation in heteroepitaxial films growing on compliant substrate，n J· Appl. Phys·，Vol· 88，pp· 4048-4055, 2000:)此時圍繞矽鍺中心體四侧的矽為受tensile strain之 strained Si。會叫做tensile strain，主要因為在圖五中的矽g、 矽10、矽11、矽12的單位晶胞是要與晶格常數一樣大小的矽鍺中 心體四個側面匹配，使得方向一51平行的晶格常數及與通道方向 53同向的晶格常數與完全鬆他的石夕錯中心體一樣，而與方向二π 平行的晶格常數最短，故稱矽9、矽1〇、矽u、矽12為受tensile strain的strained Si ’而四側通道方向的遷移率均會因strain的 關係增加。圖六代表矽受到雙軸拉伸應變（tensile strain)後， 電子與電洞遷料增加因錢到應變影響的航，其遷移率是在 通道方向，計算過程可參考文獻(F· Μ· Bufleretal·，„H〇leand
Electron Transport in Strained Si: Orthorhombic versus biaxial tensile strain,^ Appl. Phys. Lett., Vol. 81, pp. 82^84, 2002)之結果。一般來講，在圍繞矽鍺中心體四側的應變矽中的通’ ，方向，0.8%之應變會增加約6〇%電子遷移率及2·25倍電洞遷移 厂。此a守用鬆弛矽鍺中心體來成長應變矽，則需要2〇%鍺莫耳比 (mole fraction) 〇 若矽鍺因成長技術改變，而完*strained，例如Ή夠大 非平衡成長，_鍺巾讀依麵有strain,職tetragonai :曰口，則在圍，此矽鍺中心體左右兩側上之矽的載子遷移率增 ^如圖七所示，之所以會叫丨对，主要因 圖=中侧與單位晶胞是長在晶格常數不-樣大小的石夕 半-mi ’與方向一51相平行的晶格常數較長而與通道方向 #數與relaxed Si 一樣，與方向二52平行的晶格常數 丑，稱矽10與矽 11 為受orthorhombic strain的strained Si， 1231994 與通道方向53均有增加(因為有效導電質量 雙小之故）。而在矽鍺中心體底部與頂部的矽9盥矽12均為relaxed Si，遷移率並沒有择知。冃主闽从 yi^i^reiaxea 石夕，盆受ϊ非^;in，賊石夕錯中心體左右兩側上的 , # ^^(〇rth〇rh〇mbic tens^e strain)^ ^ 遷ί率沿通道方向增加因數受到應變影響的情況(計 h Κ· ^ ： F. Μ· Bufle^ "Hole Transport in Orthorhombically strained Si, "Journal of Computational
Electronics，Vol. 1，pp. 175_m，2〇〇2 ^Monte Carlo Slfflulat1〇n of Electron Transport ^ Si； 1； ^ ^ APPL Ph^s- Vol. 88, PP. 4717-4724, 2000； F. M. Bufler et al. 5 ^Hole and Electron ransport in Strained Si： Orthorhombic versus biaxial tensile strain，"Appl· PhyS· Lett·，Vol· 81，PP· 82-84， 2002)。-般來講，當石夕鍺中心體為完全應變時，圍繞其上來成長 應隻矽，當20%鍺莫耳比例（mole fracti〇n)時，在圖二中的矽切 ，石夕11在其通道方向之應變會!· 5倍電子遷移率及〗· 8倍電洞遷移 率，然而在矽9與矽12因為並沒受strain，所以遷移率並未增加。 以上圖四、六、八所示之遷移率均未考慮Si/Si〇2界面表面粗糙 (surface r0Ughness)對遷移率所造成的影響，一般來說，愈粗糙 的界面其遷移率愈低。根據參考文獻(Μ· v· Fischetti，F. and W. Hansch, ,f〇n the enhanced electron mobility in strained-silicon inversion layers, Journal 〇f Applied
PhyS1CS，Vol· 92, pp· 7320-7324, 2002·)的模擬結果，strained gi的表面粗糙的程度用比傳統矽要來得小的參數來模擬才能與其 f效遷移率對等效電場的曲線吻合，在實驗上，在有氧化層日ϋ 實看到遷移率增加的現象，此現㈣電子而言較明顯，電^則沒 看巧此一現象。足見載子在應變矽中遷移率能大大提升，而本案 所提之應變矽鰭形場效電晶體亦受惠其遷移率增加之優點，^ 改善電晶體速度。 1231994 綜上所述，本案所揭露之應變矽鰭形場效電晶體，其係利用 矽鍺中心體來產生應變矽，使此鰭形應變矽兼具應變矽場效電晶 體與鯖形場效電晶體的優點。本案所揭露之應變石夕鰭形場效電晶 體，將可有效地克服元件在縮小化所遭遇物理的極限，
快速的電晶體元件。 $ F 故本案發明得由熟習此技藝之人士任施匠思而為諸般修飾， w白不脫如附申請專利範圍所欲保護者。 【圖式簡單說明】 本案得藉由下列圖式及詳細說明，俾得更深入之了解·· 第-圖：本專利之應變補場效電晶體實施例結構示意圖。 第二圖··第一圖中沿A_A，的應變石夕鰭形結構之截面圖。 其中17.石夕錯中心體之高度。π:石夕錯中心 Q ^ 底部之石夕。1G:為石夕鍺中心體左側之應變石夕。 11、12專四個應變補的厚度分別為13、14、15、^ 第三圖：應變石夕縛場效電晶體之簡易製作流程圖。 (a) 為製作鰭形矽/矽鍺孤島之微影步驟。 (b) 蝕刻完成後的鰭形矽/矽鍺孤島。 (C)在卿卿錯孤島的左右兩細巾咖）與頂部（圖 中12)磊晶成長應變矽。 (d) 接著在應變矽上成長氧化層。 (e) ：^：後在氧化層上成長複晶石夕間極。 率對場石夕場效電晶體中縛形砂载子的等效遷移 10 1231994 第五圖.其係本案實施例之單位晶 鬆他。其中剌、則G、梦11、則2均A、:魏中心體為完全 應變矽單位晶胞。 J^^tensile strain的 變石夕Ϊ係本案實施例之圍繞完全鬆⑲之⑧鍺中心體的應 艾矽甲電子、電洞遷移率增加因數對鍺濃度之關係。 入弟七圖·其係本案貫施例之早位晶胞圖示：秒錯中心體為完 王應欠。其中石夕1〇與石夕為受〇rth〇rh〇mbicai strain的應變石夕單 =晶胞’而矽9與矽12則未受strain，其晶格常數與reiaxed Si相 ^第八圖：其係本案實施例之圍繞完全應變之石夕鍺中心體的應 變石夕中電子、電洞遷移率增加因數對鍺濃度之關係。 【主要元件符號說明】 S〇I(silicon on insulator,絕緣層上石夕）1。 應變矽鰭2。 氣化層3。 複晶石夕閘極電極4。 源極5。 及極6。 通道長度7。 矽鍺中心體8。 矽鍺中心體底部之應變矽9。 矽鍺中心體左侧之應變矽10。 矽鍺中心體側右之應變矽11。 矽鍺中心體頂部之應變矽12。 1231994 > 對應應變矽9之厚度13。 對應應變矽10之厚度14。 對應應變矽11之厚度15。 對應應變矽12之厚度16。 矽鍺中心體之高度17。 矽鍺中心體之長度18。 埋層氧化矽層31。 矽41 〇 通道方向53。 隹 方向一 51。 方向二52。 石夕在垂直界面方向的晶格常數61。 鬆他石夕錯合金之晶格常數62。 受Tensile strain之應變矽在垂直界面方向的晶格常數肋。 鬆弛矽晶格常數71。 應變石夕錯合金在垂直界面方向的晶格常數72。 受Or thorhomb i ca 1 s t ra i η之應變石夕在垂直界面方向的晶格常 數73。 光罩81。 12

Claims (1)

  1. 丨輝珊叫 ·、 I修正 本] 十、申請專利範圍： 1· 一鰭形應變石夕場效電晶體，其包含·· 一SOI(silicon on insulator，絕緣層上矽）基底； •-石夕錯中心體，其具有一鰭形孤島結構，並位於該s〇J基底 —tl 9 一應變矽通道，其係圍繞該矽鍺中心體； 氧化層，其係圍繞該應變砍通道之外側； 一複晶石夕閘極電極，其係位於該氧化層上；以及 -源極與汲極電極，其係分別位於該複晶㈣極電極 側0 • ^明專利fen第1項所述之鰭形應變石夕場效電晶體，其傳導載 電子或電洞，亦即該鰭形應㈣場效電晶體可為一 M0S)場效電晶體或一N型通道(NM〇s)場效電晶體。 3·如申请專利範圍第1項所述之·_應财場效電晶體，其中 曰^石夕閘極電極亦可為—複晶石夕鍺閘極電極，並且皆包^2 私雜之複晶矽或複晶矽鍺或金屬閘極電極。
    4· 一種電晶體製造方法，其包含下列步驟： (a) &t、SOI(silicon on insulator，絕緣層上石夕）基底； (b) 形成一矽鍺層於該s〇I基底上； 以形成一 矽層係藉 (c) 蝕刻該矽鍺層與該S0I基底所包含之一第一矽層， 具有續形孤島結構之一秒錯中心體； (d) 形，一第二矽層於該矽鍺中心體上，其中該第二 由該矽鍺中心體之厚度調整，而成為一應變矽； (e)形成一氧化層於該第二矽層上； 13 1231994 (Ο形成一複晶矽閘極於該氧化層上；以及 (g)形成一源極與汲極電極於該複晶矽閘極上。 5.如申請專利範圍第4項之方法，其於步驟(d)中，係利用一磊 晶成長方式而形成該第二砍層。
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