TWI312519B - Chip and system for performing memory operations - Google Patents

Chip and system for performing memory operations Download PDF

Info

Publication number
TWI312519B
TWI312519B TW094139881A TW94139881A TWI312519B TW I312519 B TWI312519 B TW I312519B TW 094139881 A TW094139881 A TW 094139881A TW 94139881 A TW94139881 A TW 94139881A TW I312519 B TWI312519 B TW I312519B
Authority
TW
Taiwan
Prior art keywords
command
wafer
memory
type signal
value
Prior art date
Application number
TW094139881A
Other languages
English (en)
Chinese (zh)
Other versions
TW200623146A (en
Inventor
Kuljit Bains
Original Assignee
Intel Corporatio
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporatio filed Critical Intel Corporatio
Publication of TW200623146A publication Critical patent/TW200623146A/zh
Application granted granted Critical
Publication of TWI312519B publication Critical patent/TWI312519B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW094139881A 2004-11-18 2005-11-14 Chip and system for performing memory operations TWI312519B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/992,953 US7433992B2 (en) 2004-11-18 2004-11-18 Command controlling different operations in different chips

Publications (2)

Publication Number Publication Date
TW200623146A TW200623146A (en) 2006-07-01
TWI312519B true TWI312519B (en) 2009-07-21

Family

ID=36130071

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094139881A TWI312519B (en) 2004-11-18 2005-11-14 Chip and system for performing memory operations

Country Status (7)

Country Link
US (1) US7433992B2 (fr)
JP (1) JP4599409B2 (fr)
CN (1) CN100592276C (fr)
DE (1) DE112005002336T5 (fr)
GB (1) GB2432945B (fr)
TW (1) TWI312519B (fr)
WO (1) WO2006055497A2 (fr)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7532537B2 (en) 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
KR100670674B1 (ko) * 2005-06-30 2007-01-17 주식회사 하이닉스반도체 반도체 메모리 장치
KR100711100B1 (ko) * 2005-07-11 2007-04-24 삼성전자주식회사 메모리 모듈 및 이를 구비하는 메모리 시스템
KR100792213B1 (ko) * 2005-08-11 2008-01-07 삼성전자주식회사 메모리 컨트롤러와 메모리를 인터페이싱하는 랩퍼 회로
JP5242397B2 (ja) 2005-09-02 2013-07-24 メタラム インコーポレイテッド Ｄｒａｍをスタックする方法及び装置
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7486104B2 (en) * 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
US7564735B2 (en) * 2006-07-05 2009-07-21 Qimonda Ag Memory device, and method for operating a memory device
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
JP5087886B2 (ja) * 2006-08-18 2012-12-05 富士通株式会社 メモリ制御装置
GB2444745B (en) * 2006-12-13 2011-08-24 Advanced Risc Mach Ltd Data transfer between a master and slave
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8041865B2 (en) * 2008-08-04 2011-10-18 Qimonda Ag Bus termination system and method
WO2010144624A1 (fr) 2009-06-09 2010-12-16 Google Inc. Programmation de valeurs de résistance de terminaison dimm
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
JP5346259B2 (ja) * 2009-09-08 2013-11-20 ルネサスエレクトロニクス株式会社 半導体集積回路
KR101115653B1 (ko) * 2010-07-09 2012-02-15 주식회사 하이닉스반도체 멀티 칩 패키지 장치 및 그 동작 방법
US8688955B2 (en) 2010-08-13 2014-04-01 Micron Technology, Inc. Line termination methods and apparatus
KR101894469B1 (ko) * 2012-02-24 2018-10-04 에스케이하이닉스 주식회사 제어신호생성회로 및 이를 이용한 반도체모듈 및 반도체시스템
US10902890B2 (en) * 2012-06-22 2021-01-26 Intel Corporation Method, apparatus and system for a per-DRAM addressability mode
JP2014102867A (ja) 2012-11-20 2014-06-05 Toshiba Corp 半導体記憶装置及びその制御方法
WO2014085268A1 (fr) 2012-11-30 2014-06-05 Intel Corporation Appareil, procédé et système d'accès à un dispositif de mémoire avec une instruction multi-cycle
CN110428855B (zh) 2013-07-27 2023-09-22 奈特力斯股份有限公司 具有本地分别同步的内存模块
JP5591387B2 (ja) * 2013-08-16 2014-09-17 ルネサスエレクトロニクス株式会社 記憶装置
US9934143B2 (en) 2013-09-26 2018-04-03 Intel Corporation Mapping a physical address differently to different memory devices in a group
KR102107072B1 (ko) * 2013-11-29 2020-05-07 에스케이하이닉스 주식회사 메모리의 전원을 관리하는 메모리 컨트롤러를 포함하는 시스템
US9780782B2 (en) * 2014-07-23 2017-10-03 Intel Corporation On-die termination control without a dedicated pin in a multi-rank system
CN104332176A (zh) * 2014-11-14 2015-02-04 福州瑞芯微电子有限公司 一种省掉内存odt引脚的方法和系统
US10199084B2 (en) * 2016-03-28 2019-02-05 Intel Corporation Techniques to use chip select signals for a dual in-line memory module
US10340022B2 (en) * 2017-05-16 2019-07-02 Samsung Electronics Co., Ltd. Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
KR102471160B1 (ko) * 2017-05-16 2022-11-25 삼성전자주식회사 온-다이-터미네이션 회로를 포함하는 비휘발성 메모리 및 상기 비휘발성 메모리를 포함하는 스토리지 장치
US10997096B2 (en) 2017-05-22 2021-05-04 Intel Corporation Enumerated per device addressability for memory subsystems
KR102553266B1 (ko) * 2017-11-03 2023-07-07 삼성전자 주식회사 온-다이-터미네이션 회로를 포함하는 메모리 장치
US10424356B2 (en) * 2017-11-22 2019-09-24 Micron Technology, Inc. Methods for on-die memory termination and memory devices and systems employing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118383A (ja) * 1999-10-20 2001-04-27 Fujitsu Ltd リフレッシュを自動で行うダイナミックメモリ回路
KR100474421B1 (ko) * 2000-08-31 2005-03-14 엔이씨 일렉트로닉스 가부시키가이샤 반도체 기억 장치 및 그 테스트 방법과 테스트 회로
US6785180B2 (en) * 2001-03-15 2004-08-31 Micron Technology, Inc. Programmable soft-start control for charge pump
DE10136853B4 (de) * 2001-07-27 2004-11-18 Infineon Technologies Ag Verfahren zur Datenkommunikation mehrerer Halbleiterspeicherbausteine mit einem Controllerbaustein und dafür eingerichteter Halbleiterspeicherbaustein
US6754132B2 (en) * 2001-10-19 2004-06-22 Samsung Electronics Co., Ltd. Devices and methods for controlling active termination resistors in a memory system
US6981089B2 (en) * 2001-12-31 2005-12-27 Intel Corporation Memory bus termination with memory unit having termination control
JP3831309B2 (ja) * 2002-01-29 2006-10-11 株式会社東芝 同期型半導体記憶装置及びその動作方法
US7142461B2 (en) * 2002-11-20 2006-11-28 Micron Technology, Inc. Active termination control though on module register

Also Published As

Publication number Publication date
GB2432945B (en) 2008-07-09
GB2432945A8 (en) 2007-06-07
WO2006055497A3 (fr) 2006-07-13
TW200623146A (en) 2006-07-01
WO2006055497A2 (fr) 2006-05-26
JP2008521158A (ja) 2008-06-19
GB2432945A (en) 2007-06-06
CN100592276C (zh) 2010-02-24
DE112005002336T5 (de) 2007-10-04
GB0706015D0 (en) 2007-05-09
US20060106951A1 (en) 2006-05-18
JP4599409B2 (ja) 2010-12-15
US7433992B2 (en) 2008-10-07
CN101040274A (zh) 2007-09-19

Similar Documents

Publication Publication Date Title
TWI312519B (en) Chip and system for performing memory operations
US12235760B2 (en) Apparatus having selectively-activated termination circuitry
US11994982B2 (en) Memory module with distributed data buffers
KR100936637B1 (ko) 메모리 모듈들에 대한 동적 명령 및/또는 어드레스 미러링시스템 및 방법
US9916873B2 (en) Extended capacity memory module with dynamic data buffers
CN121785960A (zh) 用于高带宽存储器通道的dimm
KR20080076851A (ko) 바이트 레인마다의 동적 온-다이(ｏｎ－ｄｉｅ) 종단
US9412423B2 (en) Memory modules including plural memory devices arranged in rows and module resistor units
TW201042654A (en) Memory device and method of terminating transmission line from memory device
KR20060119785A (ko) 메모리 모듈에서의 랭크 어드레스 설정 방법 및 반도체메모리 시스템
TWI352357B (en) Motherboard and memory device thereof
CN115129239A (zh) 具有可扩展元数据的动态随机存取存储器（dram）

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees