TWI347660B - Chip package structure and process thereof - Google Patents

Chip package structure and process thereof

Info

Publication number
TWI347660B
TWI347660B TW096121160A TW96121160A TWI347660B TW I347660 B TWI347660 B TW I347660B TW 096121160 A TW096121160 A TW 096121160A TW 96121160 A TW96121160 A TW 96121160A TW I347660 B TWI347660 B TW I347660B
Authority
TW
Taiwan
Prior art keywords
package structure
chip package
chip
package
Prior art date
Application number
TW096121160A
Other languages
Chinese (zh)
Other versions
TW200849512A (en
Inventor
Chang Chi Lee
Ron Tai Liu
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW096121160A priority Critical patent/TWI347660B/en
Publication of TW200849512A publication Critical patent/TW200849512A/en
Application granted granted Critical
Publication of TWI347660B publication Critical patent/TWI347660B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
TW096121160A 2007-06-12 2007-06-12 Chip package structure and process thereof TWI347660B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW096121160A TWI347660B (en) 2007-06-12 2007-06-12 Chip package structure and process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096121160A TWI347660B (en) 2007-06-12 2007-06-12 Chip package structure and process thereof

Publications (2)

Publication Number Publication Date
TW200849512A TW200849512A (en) 2008-12-16
TWI347660B true TWI347660B (en) 2011-08-21

Family

ID=44824169

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096121160A TWI347660B (en) 2007-06-12 2007-06-12 Chip package structure and process thereof

Country Status (1)

Country Link
TW (1) TWI347660B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI828054B (en) * 2022-01-28 2024-01-01 群創光電股份有限公司 Electronic device
US12224226B2 (en) 2022-01-28 2025-02-11 Innolux Corporation Electronic device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115377024A (en) * 2021-05-18 2022-11-22 日月光半导体制造股份有限公司 Semiconductor packaging structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI828054B (en) * 2022-01-28 2024-01-01 群創光電股份有限公司 Electronic device
US12224226B2 (en) 2022-01-28 2025-02-11 Innolux Corporation Electronic device

Also Published As

Publication number Publication date
TW200849512A (en) 2008-12-16

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