TWI469112B - Pixel array and display panel - Google Patents

Description

Pixel array and display panel

The present invention relates to a display array and a display panel, and more particularly to a pixel array and a display panel having the pixel array.

In response to the requirements of high speed, high efficiency, light weight and shortness of modern products, all electronic components are actively developing towards miniaturization. A variety of portable electronic devices have also become mainstream, such as: Note Book, Cell Phone, electronic dictionary, Personal Digital Assistant (PDA), web pad and Tablet PC, etc. For the image display of the portable electronic device, in order to meet the demand for miniaturization of the product, a flat panel display having superior space utilization efficiency, high image quality, low power consumption, and no radiation is widely used.

In general, a flat panel display is mainly composed of a display panel and a plurality of driver ICs, wherein the display panel has a pixel array, and the pixels in the pixel array are corresponding to the scan lines and Driven by the corresponding data line. In order to make the products of flat-panel displays more popular, the industry is in full swing to reduce costs. Because the cost of data-driven chips is relatively expensive, and the signals processed by data-driven chips are more complicated and consume more power, in recent years, a data-driven A technique of half source driver is proposed, which mainly uses the layout on the pixel array to reduce the amount of data driven wafers used to reduce costs.

In addition, in order to meet consumers' expectations for low-cost and high-quality flat-panel displays, it is necessary to take into account the manufacturing errors that are inevitable in the layout of the pixel array, so that the actual products are more competitive in the market. force. For example, a plurality of pixels on a pixel array perform data signal writing by corresponding active components. However, when the precision of the machine is insufficient or the alignment error on the process, the relative displacement between the gate of the active device and the source and the drain will cause the characteristics of the active component to deviate from the original design value. In other words, when the gate and the drain of the active device are relatively displaced, the change in the overlap area between the gate and the drain of the active element in the pixel will cause the gate-drain parasitic capacitance Cgd (parasitic capacitance, Cgd) produces a change, and when the gate-drain parasitic capacitance Cgd of the pixel in the pixel array has a large difference, it is easy to cause flicker and display unevenness in the display process, which seriously affects the display quality.

The present invention provides a pixel array that reduces variation in gate-drain parasitic capacitance due to alignment offset during fabrication.

The present invention provides a display panel which can improve variations in gate-drain parasitic capacitance caused by process alignment offset between adjacent pixels, thereby contributing to improvement in display quality.

The invention provides a pixel array comprising a plurality of scan lines, a plurality of data lines, a plurality of first pixels, and a plurality of second pixels. The data line intersects the scan line, wherein each data line defines a first pixel area on one side and two adjacent odd-numbered scan lines, and is defined on the other side of the data line and adjacent two even-numbered scan lines In the second pixel area, the first pixel area is adjacent to the second pixel area and is located on both sides of the data line. The first pixels are respectively located in the first pixel region, and each of the first pixels includes a first transistor and a first pixel Pixel electrode. The second pixels are respectively located in each of the second pixel regions, and each of the second pixels includes a second transistor and a second pixel electrode, and the first pixels on both sides of the same data line are The second pixels are electrically connected to the data line. Wherein a first drain of each first transistor protrudes from a first gate of each first transistor and a second drain of each second transistor from each second transistor A second gate protrudes in the same direction.

The invention further provides a display panel comprising a pixel array substrate, a pair of substrates and a display medium layer. The pixel array substrate includes a substrate, a plurality of scan lines and a plurality of data lines, a plurality of first pixels, and a plurality of second pixels, wherein the scan lines and the data lines are disposed on the substrate, and the data lines intersect the scan lines. Each data line defines a first pixel area on one side and two adjacent odd-numbered scan lines, and defines a second pixel area on the other side and adjacent two even-numbered scan lines, the first picture The prime region is adjacent to the second pixel region and is located on both sides of the data line. The first pixels are respectively located in the first pixel region, and each of the first pixels includes a first transistor and a first pixel electrode. The second pixels are respectively located in the second pixel region, and each of the second pixels includes a second transistor and a second pixel electrode, and the first pixels on both sides of the same data line and the second pixels The second pixel is electrically connected to the data line. Wherein a first drain of each first transistor protrudes from a first gate of each first transistor and a second drain of each second transistor from each second transistor A second gate protrudes in the same direction.

In an embodiment of the invention, in each of the first transistors, the first gate is connected to one of the odd scan lines, and the first drain and the first gate have a projection direction. a first overlap region generates a first gate-drain parasitic capacitance, and in each of the second transistors, the second gate is connected to one of the even scan lines, and the second drain and the second The second gate has a second overlapping area in the projection direction And generating a second gate-drain parasitic capacitance, and the second drain, the second gate, the first drain, and the first gate are set to: when the first overlap region is reduced to cause the first gate When the drain parasitic capacitance is lowered, the second overlap region is correspondingly reduced to reduce the second gate-drain parasitic capacitance, and when the first overlap region becomes large, causing the first gate-drain parasitic capacitance to increase, The second overlap region is correspondingly enlarged to increase the second gate-drain parasitic capacitance.

In an embodiment of the present invention, in the first pixel and the second pixel connected to the same data line, the structures of the first transistor and the second transistor exhibit line symmetry of the type of the data line. .

In an embodiment of the invention, the first drain is aligned in a direction from the first overlap region in the row direction, and a direction in which the second drain protrudes from the second overlap region.

In an embodiment of the invention, the first drain is aligned, for example, from a direction in which the first overlap region protrudes in the column direction and a direction in which the second drain protrudes from the second overlap region.

In an embodiment of the invention, the first pixels located in the odd rows are aligned with each other, the second pixels in the even rows are aligned with each other, and the first pixels and the second pixels are not aligned with each other.

In an embodiment of the invention, the odd-numbered scan lines electrically connected to the first pixel are used as the lower capacitor electrode of the second pixel, and the even-numbered scan lines electrically connected to the second pixel are used as the first A pixel lower capacitor electrode.

In an embodiment of the invention, each of the first pixels further includes a first upper capacitor electrode located in the first pixel region, and in each first pixel, the first upper capacitor The electrode overlaps the even column scan line below the first pixel electrode to form a first storage capacitor. At this time, in each of the first pixels, the first pixel electrode is electrically connected to, for example, the first upper capacitor electrode.

In an embodiment of the invention, each of the second pixels further includes a second upper capacitor electrode located in the second pixel region, and in each second pixel, the second upper capacitor electrode is, for example, An odd column scan line located below the second pixel electrode is overlapped to form a second storage capacitor. At this time, in each second pixel, the second pixel electrode is electrically connected to the second upper capacitor electrode.

Based on the above, the pixel array and the display panel of the present invention use the same data line to write the corresponding signals into the pixels of the adjacent two rows, thereby achieving a data driven wafer half source driver and reducing the cost. In addition, the gate and the drain of the transistor electrically connected to the same data line and located on both sides of the data line are arranged such that the drain and gate overlap regions are synchronously reduced or enlarged, so that The variation of the gate-drain parasitic capacitance caused by the variation of the drain and gate overlap regions of the pixel array tends to be uniform, thereby avoiding the problem of flicker and display unevenness during display, and improving display quality. .

The above described features and advantages of the present invention will be more apparent from the following description.

200‧‧‧ pixel array

210, 210B‧‧‧ first pixels

210R‧‧‧ first picture area

218‧‧‧First upper capacitor electrode

210, 210A, 210B‧‧‧ first pixels

212, 212', 212''‧‧‧ first transistor

212D‧‧‧First bungee

212G‧‧‧first gate

212S‧‧‧first source

214‧‧‧ first pixel electrode

216‧‧‧First overlapping area

220, 220B‧‧‧ second picture

222, 222', 222'' ‧ ‧ second transistor

222D‧‧‧Second bungee

222G‧‧‧second gate

222S‧‧‧second source

224‧‧‧second pixel electrode

226‧‧‧Second overlapping area

Cgd1‧‧‧first gate-bungee parasitic capacitance

Cgd2‧‧‧Second gate-bungee parasitic capacitance

D, D4, D5‧‧‧ data lines

S, S4-S7, S1-S8‧‧‧ scan lines

SE, SE1, SE2, SE3, SE4‧‧‧ even scan lines

SO, SO1, SO2, SO3, SO4‧‧‧ odd scan lines

Y1‧‧‧ first direction

217‧‧‧Protective layer

219, 229‧‧‧ capacitor electrode

220, 220A, 220B‧‧‧ second picture

220R‧‧‧Second Picture Area

228‧‧‧Second upper capacitor electrode

300‧‧‧ display panel

310‧‧‧ pixel array substrate

320‧‧‧ opposite substrate

330‧‧‧Display media layer

Cst1‧‧‧first storage capacitor

Cst2‧‧‧Second storage capacitor

D, D1-5‧‧‧ data line

H1, H2‧‧‧ openings

1A is a top plan view of a pixel array in accordance with an embodiment of the present invention.

Figure 1B is a partial enlarged view of the pixel array at B of Figure 1A.

2A and FIG. 2B are further schematic diagrams showing a set of adjacent first pixels and second pixels connected to the same data line in FIG. 1B due to alignment offset on the process.

3A is a top view of a storage capacitor of a first pixel according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line AA and BB of FIG. 3A.

4 is a schematic diagram of a display panel according to an embodiment of the invention.

1A is a top plan view of a pixel array in accordance with an embodiment of the present invention. Referring to FIG. 1A, the pixel array 200 includes a plurality of scan lines S, a plurality of data lines D, a plurality of first pixels 210, and a plurality of second pixels 220. The data line D intersects with the scan line S, each data line D and two adjacent odd-numbered scan lines SO define a first pixel area 210R, and the other side of the data line D and the adjacent two even-numbered scan lines The SE defines a second pixel region 220R, and the first pixel region 210R is adjacent to the second pixel region 220R and is located on both sides of the data line D. The first pixel 210 and the second pixel 220 are located in the first pixel region 210R and in the second pixel region 220R, respectively. In more detail, in the embodiment, the first pixel 210A is taken as an example, which is located on the left side of the data line D1 and between the adjacent two odd-numbered scanning lines SO1 and SO2, where the scanning lines SO1 and SO2 are located. For example, the first scanning line S1 and the third scanning line S3. And taking the second pixel 220A adjacent to the first pixel 210A as an example, the second pixel 220A is located on the right side of the data line D1 and is located between the adjacent two even-numbered scanning lines SE1 and SE2, where The scan lines SE1 and SE2 are, for example, a second scan line S2 and a fourth scan line S4. The first pixel 210 and the second pixel 220 generally conform to the shape, size, and the like. In other words, in the present embodiment, the first pixels 210 located in the odd rows are aligned with each other, and the second pixels in the even rows are aligned. The 220s are aligned with each other, but since the first pixel 210 and the second pixel 220 are disposed between the different scanning lines S in the row direction, the first pixels 210 and the second pixels 220 are not aligned with each other.

Furthermore, FIG. 1B is a partial enlarged view of the pixel array at B of FIG. 1A. Referring to FIG. 1A and FIG. 1B simultaneously, each first pixel 210 includes a first transistor 212 and a first a pixel electrode 214, wherein the first gate 212G of the first transistor 212 is connected to one of the odd scan lines SO (such as the scan line SO3), such as the first gate in the first pixel 210B in FIG. 1B. The pole 212G is connected to the fifth scanning line S5. The first source 212S of the first transistor 212 is connected to one of the data lines D, for example, the first source 212S of the first pixel 210B is connected to the data line D4. The first drain 212D of the first transistor 212 is coupled to the first pixel electrode 214, and the first drain 212D and the first gate 212G have a first overlap region 216 in a projection direction to generate a first gate. Bungee parasitic capacitance Cgd1. On the other hand, each second pixel 220 includes a second transistor 222 and a second pixel electrode 224, wherein the second gate 222G of the second transistor 222 and one of the even scan lines SE (such as scanning) The line SE3) is connected, for example, the first gate 212G of the second pixel 210B is connected to the sixth scanning line S6. The second source 222S of the second transistor 222 is connected to the first data line D4 of the first transistor 212 and the second source 222D of the second transistor 222 is connected to the second pixel electrode 224. The second drain 222D and the second gate 222G have a second overlap region 226 in a projection direction to generate a second gate-drain parasitic capacitance Cgd2.

It is worth noting that the difference in the alignment between the different layers of the process (such as the first metal layer forming the gate and the scan line and the second metal layer forming the source, the drain and the data line) is considered. Variation of the gate-drain parasitic capacitance Cgd, as shown in FIG. 1B, in the first transistor 212 of the first pixel 210 and the second transistor 222 of the second pixel 220, the second drain 222D The setting pattern of the second gate 222G, the first drain 212D, and the first gate 212G must have a relationship of first overlapping the first drain 212D of the first pixel 210 with the first gate 212G. The region 216 is reduced in size or synchronously with the second drain region 222D of the second pixel 220 and the second overlap region 226 of the second gate 222G such that the first pixel 210 and the second pixel 220 Variation of the first gate-drain parasitic capacitance caused by the variation of the drain and gate overlap regions Cgd1 and the second gate-drain parasitic capacitance change Cgd2 tend to be uniform, thereby avoiding flicker and display unevenness problems. That is, when the first overlap region 216 is decreased to cause the first gate-drain parasitic capacitance Cgd1 to decrease, the second overlap region 226 is correspondingly reduced to lower the second gate-drain parasitic capacitance Cgd2. When the first overlap region 216 becomes large and the first gate-drain parasitic capacitance Cgd1 increases, the second overlap region 226 becomes correspondingly larger to increase the second gate-drain parasitic capacitance Cgd2.

Further, the layout pattern of the first pixel and the second pixel of the present invention will be described in detail below. As shown in FIG. 1A and FIG. 1B, in the first pixel 210 and the second pixel 220 connected to the same data line D, the structures of the first transistor 212 and the second transistor 222 are line-symmetric. The type of line D. In the present embodiment, the direction in which the first drain 212D protrudes from the first overlap region 216 in the row direction coincides with the direction in which the second drain 222D protrudes from the second overlap region 226. For example, the first drain 212D of the first pixel 210 extends, for example, from the first gate 212G along the direction of the data line D to the first direction Y1, and likewise, the second drain of the second pixel 220. 222D also extends from the second gate 222G in the direction of the data line D toward the first direction Y1. In this way, the first overlap region 216 between the first drain 212D and the first gate 212G and the second overlap region 226 between the second drain 222D and the second gate 222G may be offset. The shift time is synchronously reduced or synchronously increased, so that the gate-drain parasitic capacitance variation due to the variation of the drain and gate overlap regions tends to be uniform, thereby avoiding flicker and display unevenness. In particular, it is effective to prevent flicker and display unevenness caused by gate-drain parasitic capacitance variation due to vertical alignment offset.

To further illustrate the features of the present invention, FIG. 2A and FIG. 2B further illustrate a schematic diagram of a set of adjacent first pixels and second pixels connected to the same data line in FIG. 1B due to alignment offset on the process. , in which FIG. 2A is that the drain is offset from the gate to the first direction Y1 FIG. 2B is a schematic diagram showing a state in which the drain is offset from the gate in the second direction Y2. Referring first to FIG. 2A, the first transistor 212 of the first pixel 210 at the upper left and the second pixel 220 at the lower right of the figure are taken as an example, and the first transistor 212 and the second electrode are drawn in a broken line. The crystal 222 represents the original design position when not offset, and the first transistor 212' and the second transistor 222' drawn in solid lines are positions where the drain is offset from the gate in the first direction Y1. As shown in FIG. 2A, when the first overlap region 216' is decreased to cause the first gate-drain parasitic capacitance Cgd1 to decrease, the second overlap region 226' is correspondingly reduced to parasitize the second gate-dip The capacitance Cgd2 is lowered.

On the other hand, please refer to FIG. 2B, taking the first transistor 212 of the first pixel 210 located at the upper left in the figure and the second pixel 220 located at the lower right as an example, the first transistor 212 drawn by a broken line and The second transistor 222 represents the original design position when not offset, and the first transistor 212'' and the second transistor 222'' drawn in solid lines are offset from the gate to the first direction Y1 with respect to the gate. After the location. As shown in FIG. 2B, when the first overlap region 216'' becomes large to cause the first gate-drain parasitic capacitance Cgd1 to increase, the second overlap region 226" becomes correspondingly larger to make the second gate-汲The parasitic capacitance Cgd2 increases.

Therefore, even when a misalignment occurs between different film layers when the transistor is fabricated (the second metal layer is opposite to the first metal layer) or a slight offset due to the tolerance of the precision of the machine, the first pixel 210 The change of the generated first gate-drain parasitic capacitance Cgd1 is more consistent with the change of the second gate-drain parasitic capacitance Cgd2 generated by the second pixel 220. The so-called variation is more consistently means a pixel array. The gate-drain parasitic capacitance Cgd of each pixel on 200 will become larger or smaller at the same time. In this way, the difference in brightness between adjacent two pixels is small, and when the pixel array 200 is applied to the display panel (shown in FIG. 4), the display uniformity of the display is improved, thereby avoiding A problem occurs in which flicker is generated to cause uneven brightness.

In addition, in the pixel array 200 of the present invention, the odd-numbered scan lines SO electrically connected to the first pixel 210 can further serve as the lower capacitor electrode of the second pixel 220, and are electrically connected to the second pixel 220. The even number of scan lines SE may further serve as the lower capacitor electrode of the first pixel 210. The following will be further described with reference to FIG. 3A and FIG. 3B to further illustrate that the first pixel and the second pixel mutually utilize the scan line electrically connected to each other as the storage capacitor type of the capacitor electrode under the self.

3A is a top view of a storage capacitor of a first pixel according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line AA and BB of FIG. 3A. As shown in FIG. 3A and FIG. 3B, in the embodiment, each first pixel 210 further includes a first upper capacitor electrode 218 located in the first pixel region 210R, and at each first pixel 210. The even number of scan lines SE electrically connected to the second pixel 220 are used as the lower capacitor electrode 219 of the first pixel 210, and in the embodiment, the first pixel electrode 214 and the first upper capacitor electrode 218 are electrically The first pixel element 214, the first upper capacitor electrode 218, and the even column scan line SE as the lower capacitor electrode 219 of the first pixel 210 constitute a first storage capacitor Cst1, wherein the first pixel electrode 214 is, for example, It is connected to the first upper capacitor electrode 218 via the opening H1 of the protective layer 217. On the other hand, each second pixel 220 may further include a second upper capacitor electrode 228 located in the second pixel region 220R, and in each second pixel 220, electrically connected to the first pixel 210 The odd-numbered scan lines SO are connected as the lower capacitor electrodes 229 of the second pixel 220, and in the present embodiment, the second pixel electrodes 224 and the second upper capacitor electrodes 228 are electrically connected such that the second pixel electrodes 224 The second upper capacitor electrode 228 and the odd-numbered column scan line SO as the lower capacitor electrode 229 of the second pixel 220 constitute a second storage capacitor Cst2, wherein the second pixel electrode 224 is, for example, via the opening H2 of the protective layer 217. The second upper capacitor electrode 228 is connected.

4 is a schematic diagram of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 4 , the display panel 300 of the present embodiment includes a pixel array substrate 310 , a pair of substrates 320 , and a display medium layer 330 disposed between the pixel array substrate 310 and the opposite substrate 320 . The pixel array substrate 310 herein may be a substrate having the pixel array 200 of the foregoing various embodiments of the present invention or other unillustrated pixels. The opposite substrate 320 is, for example, a color filter substrate. Of course, if possible, the opposite substrate 320 may be a glass substrate or a quartz substrate having only a common electrode, and a color filter layer may be formed on the corresponding pixel array substrate 310. In the embodiment, the display medium layer 330 is, for example, a liquid crystal layer, and the display panel 300 is a liquid crystal display panel 300. Of course, in other embodiments, the display medium layer 330 may also be an electroluminescent material, and the display panel 300 is an electroluminescent display panel 300, wherein the electroluminescent material is, for example, an organic material, an inorganic material, or a combination thereof. .

In summary, the pixel array and the display panel of the present invention use the same data line to write corresponding signals into the pixels of two adjacent rows, thereby achieving a data driven wafer half source driver and reducing the cost. . In addition, the gate and the drain of the transistor electrically connected to the same data line and located on both sides of the data line are arranged such that the drain and gate overlap regions are synchronously reduced or enlarged, so that The gate-drain parasitic capacitance of each pixel on the pixel array tends to be uniform due to the variation of the drain and gate overlap regions, thereby avoiding the occurrence of flicker and display unevenness during display, and improving display quality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of protection of the present invention is attached The scope of the patent application is subject to change.

210, 210B‧‧‧ first pixels

212‧‧‧First transistor

212D‧‧‧First bungee

212G‧‧‧first gate

212S‧‧‧first source

214‧‧‧ first pixel electrode

216‧‧‧First overlapping area

220, 220B‧‧‧ second picture

222‧‧‧second transistor

222D‧‧‧Second bungee

222G‧‧‧second gate

222S‧‧‧second source

224‧‧‧second pixel electrode

226‧‧‧Second overlapping area

Cgd1‧‧‧first gate-bungee parasitic capacitance

Cgd2‧‧‧Second gate-bungee parasitic capacitance

D, D4, D5‧‧‧ data lines

S, S4-S7‧‧‧ scan line

SE2, SE3‧‧‧ even scan lines

SO3, SO4‧‧‧ odd scan lines

Y1‧‧‧ first direction

Claims (22)

A pixel array includes: a plurality of scan lines and a plurality of data lines, wherein the data lines intersect the scan lines, wherein each of the data lines defines a first one on one side and two adjacent odd scan lines a pixel region, and on the other side thereof, a second pixel region defined by the adjacent two even scan lines, the first pixel regions being adjacent to the second pixel regions and respectively located on the data line a plurality of first pixels, respectively located in the first pixel regions, each of the first pixels comprising a first transistor and a first pixel electrode connected to the first transistor; The second pixels are respectively located in the second pixel regions, and each of the second pixels includes a second transistor and a second pixel electrode connected to the second transistor, and the same data line The first pixels on the two sides and the second pixels are electrically connected to the data line; wherein a first drain of each first transistor is from a first gate of each first transistor a direction in which the poles are convex and a direction in which a second drain of each of the second transistors protrudes from a second gate of each of the second transistors . The pixel array of claim 1, wherein in each of the first transistors, the first gate is connected to one of the odd scan lines, the first drain and the first gate The pole has a first overlap region in a projection direction to generate a first gate-drain parasitic capacitance, and in each second transistor, the second gate is connected to one of the even-numbered scan lines, The second drain and the second gate have a second overlap region in the projection direction to generate a second gate-drain parasitic capacitance, and the second drain, the second gate, and the first gate And the first gate is configured to: when the first overlap region decreases to cause the first gate-drain parasitic capacitance to decrease, the second overlap region is correspondingly reduced to cause the second gate - Bungee parasitic capacitance decreases when the first overlap When the region becomes large and the first gate-drain parasitic capacitance increases, the second overlap region becomes correspondingly larger to increase the second gate-drain parasitic capacitance. The pixel array of claim 1, wherein the first gates of the first transistors and the second gates of the second transistors respectively protrude from corresponding scan lines. The protruding directions of the first gates in the row direction coincide with the protruding directions of the second gates. The pixel array of claim 1, wherein a first source of each of the first transistors has a recess toward the corresponding first drain along the row direction, and each of the second transistors a second source has a recess toward the corresponding second drain along the row direction, and the recesses of the first source are oriented toward the notches of the second source . The pixel array of claim 1, wherein the first pixels and the second pixels connected to the same data line, the first transistors and the second electrodes The structure of the crystal exhibits a line symmetry to the shape of the data line. The pixel array of claim 2, wherein the first drains protrude from the first overlapping regions along the row direction and the second drains from the second overlap regions The direction of the bulge is the same. The pixel array of claim 1, wherein the first pixels located in the odd rows are aligned with each other, the second pixels in the even rows are aligned with each other, and the first pixels and the first pixels are These second pixels are not aligned with each other. The pixel array of claim 1, wherein the odd-numbered scan lines electrically connected to the first pixels serve as lower capacitance electrodes of the second pixels, and the second The even number of scan lines electrically connected to the pixels are used as the lower capacitor electrodes of the first pixels. The pixel array of claim 1, wherein each of the first pixels further includes a first upper capacitor electrode located in the first pixel region, and in each of the first pixels, the first The upper capacitor electrode overlaps with the even-numbered column scan lines located under the first pixel electrode to form a first storage capacitor. The pixel array of claim 9, wherein in each of the first pixels, the first pixel electrode is electrically connected to the first upper capacitor electrode. The pixel array of claim 1, wherein each second pixel further comprises a second upper capacitor electrode located in the second pixel region, and in each second pixel, the first pixel The upper upper capacitor electrode overlaps with the odd column scan lines located under the second pixel electrode to form a second storage capacitor. The pixel array of claim 11, wherein in each second pixel, the second pixel electrode is electrically connected to the second upper capacitor electrode. A display panel includes: a pixel array substrate, comprising: a substrate; a plurality of scan lines and a plurality of data lines disposed on the substrate, wherein the data lines intersect the scan lines, and each data line is One side and two adjacent odd-numbered scan lines define a first pixel area, and on the other side and adjacent two even-numbered scan lines define a second pixel area, the first pixel areas and The second pixel regions are adjacent to each other and are respectively located at two sides of the data line; a plurality of first pixels are respectively located in the first pixel regions, and each of the first pixels includes a first transistor and a first pixel electrode; and a plurality of second pixels respectively located in the second pixel regions, each second pixel comprising a second transistor and a second pixel electrode, and the same data The first pixels on both sides of the line and the second pixels are electrically connected to the data line; wherein a first drain of each first transistor is from a first of each first transistor a direction in which the gate protrudes and a second drain of each of the second transistors protrude from a second gate of each of the second transistors To the agreement. The display panel of claim 13, wherein in each of the first transistors, the first gate is connected to one of the odd scan lines, the first drain and the first gate in a first overlap region is formed in a projection direction to generate a first gate-drain parasitic capacitance. In each second transistor, the second gate is connected to one of the even scan lines. The second drain and the second gate have a second overlap region in the projection direction to generate a second gate-drain parasitic capacitance, and the second drain, the second gate, the first drain, and The first gate is configured to: when the first overlap region is reduced to cause the first gate-drain parasitic capacitance to decrease, the second overlap region is correspondingly reduced to cause the second gate-drain The parasitic capacitance decreases. When the first overlap region becomes large and the first gate-drain parasitic capacitance increases, the second overlap region becomes correspondingly larger to increase the second gate-drain parasitic capacitance. The display panel of claim 13, wherein the first pixels and the second pixels connected to the same data line, the first transistors and the second transistors The structure exhibits a line symmetry to the type of the data line. The display panel of claim 13, wherein the first dipoles protrude from the first overlapping regions in a row direction and the second dipoles protrude from the second overlapping regions. The directions are the same. The display panel of claim 13, wherein the first pixels located in the odd rows are aligned with each other, the second pixels located in the even rows are aligned with each other, and the first pixels and the first pixels are The second pixels are not aligned with each other. The display panel of claim 13, wherein the odd-numbered scan lines electrically connected to the first pixels are used as the lower capacitive electrodes of the second pixels, and the second paintings The even number of scan lines electrically connected to the element are used as the lower capacitor electrodes of the first pixels. The display panel of claim 13, wherein each of the first pixels further comprises a first upper capacitor electrode located in the first pixel region, in each of the first pixels, the first layer The capacitor electrode overlaps with the even-numbered column scan lines located below the first pixel electrode to form a first storage capacitor. The display panel of claim 19, wherein in each of the first pixels, the first pixel electrode is electrically connected to the first upper capacitor electrode. The display panel of claim 13, wherein each second pixel further comprises a second upper capacitor electrode located in the second pixel region, and in each second pixel, the second The upper capacitor electrode overlaps with the odd-numbered column scan lines located under the second pixel electrode to form a second storage capacitor. The display panel of claim 20, wherein in each second pixel, the second pixel electrode is electrically connected to the second upper capacitor electrode.