TWI481014B - Semiconductor memory element and method of manufacturing same - Google Patents

Description

Semiconductor memory element and method of manufacturing same

The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device and a method of fabricating the same, wherein the semiconductor memory device has an improved gate coupling coefficient (GCC).

The gate coupling coefficient (GCC) is one of the important characteristics of flash memory components. Flash memory components with large gate coupling coefficients typically achieve higher component performance. In the fabrication of flash memory components, shallow trench isolation (STI) techniques can be used to form isolation structures for bit isolation and word isolation. In particular, in a cell array of flash memory elements, the shallow trench isolation structure electrically insulates two adjacent memory cells. Additionally, as discussed below, shallow trench isolation structures may affect the gate coupling coefficient of flash memory components.

1A-1H are schematic cross-sectional views showing a method of fabricating a conventional flash memory device. Referring to FIG. 1A, a yttrium oxide (SiO ₂ ) layer 12 as a pad oxide layer may be formed on the substrate 11 by a thermal oxidation process. Next, a tantalum nitride (Si ₃ N ₄ ) layer 13 may be formed on the pad oxide layer 12 by a deposition process, and the thickness “T ₀ ” of the tantalum nitride layer 13 is about 1800 angstroms ( ).

Referring to FIG. 1B, a portion of the hafnium oxide layer 12 and a portion of the tantalum nitride layer 13 may be removed by an etching process to expose portions 111 of the substrate 11. After the etching process is performed, the patterned tantalum nitride layer 13-1 and the patterned hafnium oxide layer 12-1 may together form a plurality of stacked structures 10 which are separated from each other in the row direction by the exposed portions 111. And extending in the column direction. Each of the stacked structures 10 has a width "W ₀ " in the row direction.

Referring to FIG. 1C, the spacer oxide 14 may be formed on both sides of each stacked structure 10 by a thin film deposition process and an etching process.

Referring to FIG. 1D, a trench 15 may be formed between adjacent stacked structures 10 by an etching process, and a spacer oxide 14 may be used as a protective layer to protect the sidewalls of the stacked structure 10 from being etched.

Referring to FIG. 1E, in the deposition process, the trench 15 may be filled with yttrium oxide to form the shallow trench isolation structure 16. Next, a chemical mechanical polishing process may be performed to planarize the surface of the patterned tantalum nitride layer 13-1 and the surface of the shallow trench isolation structure 16. Then, the patterned tantalum nitride layer 13-1 is removed.

Referring to FIG. 1F, the polysilicon layer 17 may be formed on the patterned yttrium oxide layer 12-1 by a deposition process, and then the polysilicon layer 17 may be coplanar with the shallow trench isolation structure 16 by a chemical mechanical polishing process.

Referring to FIG. 1G, the shallow trench isolation structure 16 may be partially etched to form a shallow trench isolation structure 16-1 having a smaller height.

Referring to FIG. 1H, an oxide-nitride-oxide (ONO) layer 18 may be formed on the polysilicon layer 17 and the shallow trench isolation structure 16-1 by a deposition process. NAND flash memory is coupled coefficient element is a function of the width W ₀ shown in FIG. 1H width W ₀ of each of the cells in the row direction of the polysilicon layer of each unit or patterned layer 17 of silicon oxide on 12-1 The width is the same. That is, the gate coupling coefficient may increase as the width W ₀ increases, and decrease as the width W ₀ decreases.

It is therefore preferred to have the semiconductor memory device have a larger width W ₀ and thus have an improved gate coupling coefficient. Furthermore, the current trend in the semiconductor industry is to fabricate semiconductor components having miniaturized dimensions. As all dimensions of the integrated circuit are reduced, the size of the memory and the width W _{0 of} each memory cell are also reduced, which adversely affects the gate coupling coefficient of the memory device. Therefore a need for a method of manufacturing a semiconductor memory device to be by increasing the width W ₀ of the semiconductor memory element of improved gate coupling coefficient.

The present invention provides a semiconductor memory device and a method of fabricating the same to achieve a higher gate coupling coefficient.

The present invention provides a semiconductor memory device comprising a substrate, a patterned dielectric layer on the substrate, a patterned conductor layer on the patterned dielectric layer, and a plurality of isolation structures, wherein the isolation structure pairs the patterned conductor The layers provide electrical isolation. Each isolation structure includes a base in the substrate, a first block extending from the base to the patterned conductor layer, and a second block extending from the base to the patterned conductor layer, wherein the first block and the second block Separated from each other above the substrate.

The present invention provides another semiconductor memory device comprising a substrate, a patterned dielectric layer on the substrate, an array of conductor cells arranged in rows and columns on the patterned dielectric layer, and a plurality of isolation structures, wherein the isolation structure is The conductor unit provides electrical isolation. Each conductor unit includes a first portion on the patterned dielectric layer and a second portion over the patterned dielectric layer. The first portion has a width "W ₁ " in the row direction and the second portion has a width "W" in the row direction, where W _{1 is} less than W. Further, each of the isolation structures includes a base at a base, a first block extending from the base to one of the conductor units, and a second block extending from the base to the other of the conductor units, wherein the conductor unit The other is in close proximity to the one of the conductor elements in the row direction. The first block and the second block are separated from each other above the substrate.

The invention further provides a semiconductor memory device comprising a substrate and an array of memory cells arranged in rows and columns on the substrate. Each of the memory cells may include a dielectric unit, a conductor unit, a first isolation structure, and a second isolation structure on the substrate. The conductor unit can include a first portion on the dielectric unit and a second portion above the dielectric unit. The first portion has a first width in the row direction and the second portion has a second width in the row direction, wherein the first width is less than the second width. The first isolation structure can include a first block, wherein the first block is coupled to the first portion and the second portion of the conductor unit. Additionally, the second isolation structure can include a second block, wherein the second block is coupled to the first portion and the second portion of the conductor unit. The first block and the second block are separated from each other above the substrate.

The present invention further provides a method of fabricating a semiconductor memory device. First, a substrate is provided. Next, a patterned first dielectric layer is formed on the substrate. A patterned second dielectric layer is then formed over the patterned first dielectric layer, wherein the patterned first and second dielectric layers expose a portion of the substrate. A trench is then formed through the exposed portion of the substrate. The trench is then filled with a dielectric material to form a first isolation trench and planarized by a chemical mechanical polishing process. Following, the height of the patterned second dielectric layer is partially removed to form a patterned dielectric layer. Next, the first isolation trench is etched to form a second isolation trench, wherein each of the second isolation trenches has a top and first and second shoulders on one side of the top, respectively. The patterned dielectric layer is then removed. A patterned conductor layer is then formed on the patterned first dielectric layer, wherein the patterned conductor layer is on the same level as the top of the second isolation trench. Next, the third isolation trench is formed by removing the top of the second isolation trench, such that each of the third isolation trenches includes first and second shoulders and an exposed surface that is lower than the first and second shoulders.

The features and advantages of a part of the present invention will be described hereinafter, and other features and advantages will be apparent from the description of the invention. The features and advantages of the present invention are realized and attained by the <RTIgt;

The above described features and advantages of the present invention will be more apparent from the following description.

The invention will be described in detail with reference to the embodiments of the invention and the drawings. The same reference numbers will be used throughout the drawings to refer to the same or. It must be understood that the schema is a simplified representation rather than a representation of the exact dimensions.

2 is a partial cross-sectional view of a memory cell 20 of a portion of a semiconductor memory device in accordance with an embodiment of the present invention. Memory cell 20 can be used as a storage unit in a semiconductor memory device, wherein the semiconductor memory device includes an array of memory cells 20. In order to simplify the drawing, only a part of a memory cell is shown, and the entire memory cell array of the semiconductor memory element is not shown.

Referring to FIG. 2, the semiconductor memory device may include a substrate 21, a patterned first dielectric layer 22, a patterned conductor layer 23, a patterned second dielectric layer 24, and a plurality of isolation structures (only first isolation) The structure 25-1 and the second isolation structure 25-2 are representative, wherein the patterned first dielectric layer 22 further includes an array of dielectric cells 220, and the patterned conductor layer 23 further includes conductor units 230 arranged in rows and columns. Array. The array of dielectric cells 220 may extend in the column direction, such as in a direction perpendicular to the page plane of FIG. In addition, the representative memory cell 20 can include a dielectric unit 220, a conductor unit 230 on the dielectric unit 220, and a first isolation structure 25-1 and a second isolation structure 25-2.

The dielectric unit 220 may include one of cerium oxide (SiO ₂ ) and cerium oxynitride (SiON), and may serve as a pad oxide layer or a pad dielectric layer of the memory cell 20. The dielectric unit 220 has a width of about "W ₁ " in the row direction, wherein the row direction is, for example, in a direction horizontal to the page plane of FIG. 2.

The conductor unit 230 may include a polysilicon and may serve as a floating gate of the memory cell 20. The conductor unit 230 may further include a first portion (not labeled) on the dielectric unit 220 and a second portion (not labeled) above the dielectric unit 220. The first portion of the conductor unit 230 has a width of about "W ₁ " in the row direction, and the second portion of the conductor unit 230 has a width of about "W" in the row direction, wherein W _{1 is} smaller than W.

The first and second isolation structures 25-1, 25-2 (e.g., shallow trench isolation (STI) structures) can provide electrical isolation to the memory cells 20. The first isolation structure 25-1 may include a first base portion 25a, a first block 251a, and a second block 252a in the substrate 21, wherein the first block 251a extends from the first base portion 25a to the conductor unit of the memory cell 20. 230, and the second block 252a extends from the first base 25a to the conductor unit 230 of the other memory cell 20-1, wherein the memory cell 20-1 is in close proximity to the memory cell 20 in the row direction. The first block 251a and the second block 252a may be separated from each other above the substrate 21. Further, the first block 251a may be coplanar with the first side 230a of the conductor unit 230 in the row direction. Furthermore, the first block 251a is connected to the first and second portions of the conductor unit 230, and the first block 251a has a width of about "T" in the row direction.

Similarly, the second isolation structure 25-2 may include a second base 25b, a first block 251b, and a second block 252b in the substrate 21, wherein the first block 251b extends from the second base 25b to another memory The conductor unit 230 of the cell 20-2, wherein the memory cell 20-2 is adjacent to the memory cell 20 in the row direction, and the second block 252b is extended from the second base 25b to the conductor cell 230 of the memory cell 20. The first block 251b and the second block 252b may be separated from each other above the substrate 21. Further, the second block 252b may be coplanar with the second side 230b of the conductor unit 230 in the row direction. Further, the second block 252b is connected to the first and second portions of the conductor unit 230, and the second block 252b has a width of about "T" in the row direction.

In the present embodiment, the size parameters W, W ₁ , and T satisfy the equation (1) shown below.

W=W ₁ +2T equation (1)

The "T" value can be predetermined to avoid shorting of adjacent conductor units 230 during the process. In one embodiment, the width may be equal to or less than T 1 / 3W _2, e.g. T ≦ W _2/3. Embodiment, the width T of the dielectric between 1 / 4W ₂ to 1 / 3W _2, e.g. _{W 2/4 ≦ T ≦ W} 2/3 in another embodiment.

Compared to the semiconductor memory device shown in FIG. 1H, the "W" of the semiconductor memory device according to the present invention is larger than the width "W ₀ " of the conventional semiconductor memory device in the width of interest (which is substantially equal to that of FIG. 2 Shown W ₁ ). Therefore, the gate coupling coefficient of the semiconductor memory device of the present invention is greater than that of the conventional semiconductor memory device shown in FIG. 1H.

3A to 3K are schematic cross-sectional views showing a method of manufacturing the semiconductor memory device shown in Fig. 2.

Referring to Figure 3A, a substrate 31 is provided which is, for example, doped with a p-type dopant. Next, a first dielectric layer 32 is formed on the substrate 31, for example, by a deposition process. The first dielectric layer 32 may include one of yttrium oxide (SiO ₂ ) and hafnium oxynitride (SiON), the first dielectric layer 32 having a relationship of about 100 angstroms ( ) to a thickness of 300 angstroms. Next, a second dielectric layer 33 is formed on the first dielectric layer 32 by a deposition process. In an embodiment, the second dielectric layer 33 may include tantalum nitride (Si _x N _y ) and has a thickness "T ₁ " of between about 2000 angstroms and 3600 angstroms. The thickness T _{1 is} greater than the thickness T ₀ shown in FIG. 1A to define features of the semiconductor memory device in subsequent processes.

Referring to FIG. 3B, the patterned second dielectric layer 33-1 and the patterned first dielectric layer 32-1 may be sequentially formed by a lithography process and an etching process. Next, the portion 311 of the substrate 31 is exposed. Any of the patterned first dielectric layer 32-1 and the patterned second dielectric layer 33-1 may have a width "W ₁ " in the row direction. Further, each exposed portion 311 may have a width "W ₂ " in the row direction. The widths W ₁ , W ₂ can be varied in different generation processes. For example, in a 90 nm (90-nm) process, the width W ₁ may be about 40 nm and the width W ₂ may be about 50 nm, for example, a channel length of a gold-oxide semiconductor field effect transistor (MOSFET) is 90 nm. The width is approximately half the length of the channel.

Referring to FIG. 3C, the sidewall spacers 34 may be formed along both sidewalls of the patterned first dielectric layer 32-1 and the patterned second dielectric layer 33-1 by sequentially performing a deposition process and an etching process. The sidewall spacers 34 may include hafnium oxide and have a thickness of about 200 angstroms.

Referring to FIG. 3D, a trench 35 may be formed in the substrate 31, wherein each trench 35 exposes the substrate 31. The method of forming the trench 35 may be a shallow trench isolation (STI) technique, and in the process of forming the trench, the sidewall spacers 34 may be used to protect the patterned first dielectric layer 32-1 and the patterned second dielectric layer. 33-1. Each trench 35 may have a depth of between about 2000 angstroms and 3500 angstroms from the surface of the substrate 31.

Referring to FIG. 3E, the trench 35 can then be filled with a dielectric material, such as a high density plasma (HDP) deposition process. Then, using the patterned second dielectric layer 33-1 as a polishing stop layer, a chemical mechanical polishing process is performed to planarize or planarize the deposited high density plasma (HDP) deposition layer to form a first isolation trench. 36-1.

Referring to FIG. 3F, the patterned second dielectric layer 33-1 is partially removed or etched back by an etching process to form a patterned dielectric layer 33-2. In the present embodiment, the patterned dielectric layer 33-2 has a thickness "T ₂ " of about 1800 angstroms and a thickness substantially equal to the thickness T ₀ of the tantalum nitride layer 13 shown in FIG. 1A. The patterned dielectric layer 33-2 exposes a portion of each of the first isolation trenches 36-1.

Referring to FIG. 3G, for example, the exposed portion of each of the first isolation trenches 36-1 is partially removed by an isotropic etching to form a second isolation trench 36-2 such that the height of the second isolation trench 36-2 is T _{1 is} reduced to T ₃ . By controlling the processing time of the isotropic etching process, each of the second isolation trenches 36-2 may include a top portion 363, a first shoulder portion 361 on one side of the top portion 363, and a first side on the other side of the top portion in the row direction. Two shoulders 362. The first shoulder 361 and the second shoulder 362 have a width "T" in the row direction. As previously described with reference to FIG. 2, it may be previously determined "T" values to ensure that the width of the top 363 in the row direction "W _3" is sufficient to prevent a short circuit between adjacent memory cells, wherein W ₃ = W ₂ -2T. In one embodiment, the width may be equal to or less than T 1 / 3W _2, e.g. T ≦ W _2/3. In another embodiment, the width of the T may be between 1 / 4W ₂ to 1 / 3W _2, such as the _{W 2/4 ≦ T ≦ W} 2/3.

Referring to FIG. 3H, the patterned dielectric layer 33-2 can be removed comprehensively, for example, by an isotropic etching process, such as using an H ₃ PO ₄ solution as an etchant.

Referring to FIG. 3I, a conductor layer may be formed over the second isolation trench 36-2 and the patterned first dielectric layer 32-1, for example, a conductor layer having a polysilicon layer formed by a deposition process. Next, for example, the second isolation trench 36-2 is used as a polishing stop layer, and the conductor layer is planarized by a chemical mechanical polishing process to form a patterned conductor layer 37. The patterned conductor layer 37 can include an array of conductor segments 370 that extend in the column direction. Each conductor segment 370 can include a first segment having a width "W ₁ " and a second segment having a width "W", wherein the first segment is on the patterned first dielectric layer 32-1, and the second section of the patterned first dielectric layer 32-1 over the row direction is substantially equal to W wherein _{W. 1} plus 2T.

Referring to FIG. 3J, the patterned conductor layer 37 is used as a mask, for example, a portion of each of the second isolation trenches 36-2 is removed by an etching process to form a third isolation trench 36-3. Among them, the etching process is, for example, an oxide dip process. After the etching process, the top 363 of the second isolation trench 36-2 can be completely removed such that the exposed surface 364 of each of the third isolation trenches 36-3 is lower than the first and second shoulders 361, 362. Thus, the first and second shoulders 361, 362 are "blocks" with respect to each exposed surface 364. Moreover, each of the third isolation trenches 36-3 can include a base 360 located in the substrate 31 and a first block 361 and a second block 362 extending from the base 360.

Referring to FIG. 3K, a third dielectric layer 38 including an oxide-nitride-oxide (ONO) stacked layer is formed on the patterned conductor layer 37 by, for example, a deposition process. In addition, another conductor layer (not shown) may be formed over the third dielectric layer 38 as a control gate layer, and the conductor layer, the third dielectric layer 38, and the patterned conductor layer 37 may be Patterning to form a matrix of memory cells in sequence.

It will be understood by those of ordinary skill in the art that certain changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, it is to be understood that the invention is not limited to the specific embodiment disclosed, that is, within the spirit and scope of the present invention, some modifications and refinements may be made thereto, so that the scope of protection of the present invention is attached. The scope of the patent application is subject to change.

Moreover, in the embodiments of the invention, the methods and/or processes of the invention are described in a particular sequence of steps. However, the methods or processes of the present invention are not limited to the sequence of steps described herein. Anyone having ordinary skill in the art should understand that other sequences are also possible. Therefore, the specific order of the steps recited in the specification should not be construed as a limitation. Furthermore, the description of the method and/or process of the present invention in the scope of the claims should not be construed as being in the order of the written description. Any one of ordinary skill in the art should understand that the spirit and scope of the present invention The order can be changed within.

10. . . Stack structure

11, 21, 31. . . Base

12. . . Cerium oxide layer

12-1. . . Patterned ruthenium oxide layer

13. . . Tantalum nitride layer

13-1‧‧‧ patterned layer of tantalum nitride

14‧‧‧ spacer oxide

15‧‧‧ Ditch

16, 16-1‧‧‧ shallow trench isolation structure

17‧‧‧Polysilicon layer

18‧‧‧Oxide-nitride-oxide layer

20, 20-1, 20-2‧‧‧ memory cells

22, 24, 32, 32-1, 33, 33-1, 38‧‧‧ dielectric layers

23, 37‧‧‧ patterned conductor layer

25-1, 25-2‧‧‧ isolation structure

25a, 25b, 360‧‧‧ base

34‧‧‧ sidewall spacer

35‧‧‧ Ditch

36-1, 36-2, 36-3‧‧‧Isolation Ditch

111, 311‧‧‧ Section

220‧‧‧ dielectric unit

230‧‧‧Conductor unit

230a, 230b‧‧‧ side

251a, 251b, 252a, 252b, 361, 362‧‧‧ blocks

361, 362‧‧‧ shoulder

363‧‧‧ top

364‧‧‧ surface

370‧‧‧ conductor section

W, W ₀ , W ₁ , W ₂ , W ₃ , T‧‧‧ width

T ₀ , T ₁ , T ₃ ‧‧‧ thickness

1A-1H are schematic cross-sectional views showing a method of fabricating a conventional flash memory device.

2 is a partial cross-sectional view of a memory cell of a portion of a semiconductor memory device in accordance with an embodiment of the present invention.

3A to 3K are schematic cross-sectional views showing a method of manufacturing the semiconductor memory device shown in Fig. 2.

twenty one. . . Base

20, 20-1, 20-2. . . Memory cell

twenty two. . . Patterned first dielectric layer

twenty three. . . Patterned conductor layer

twenty four. . . Patterned second dielectric layer

25-1, 25-2. . . Isolation structure

25a, 25b. . . Base

220. . . Dielectric unit

230. . . Conductor unit

230a, 230b. . . side

251a, 251b, 252a, 252b. . . Block

W, W ₁ , W ₂ , T. . . width

Claims (24)

A semiconductor memory device comprising: a substrate; a patterned dielectric layer on the substrate; a patterned conductor layer on the patterned dielectric layer, the surface of the patterned conductor layer being a plane And a plurality of isolation structures providing electrical isolation to the patterned conductor layer, each of the isolation structures including a base in the substrate, a first portion extending from the base to the patterned conductor layer a block and a second block extending from the base to the patterned conductor layer, wherein the first block and the second block are separated from each other above the substrate, wherein the first block Each of the isolation structures of a block and the second block has a width W ₂ in the row direction, and any one of the first block and the second block is in the row direction Has a width T, where T is between 1/4 W ₂ and 1/3 W ₂ . The semiconductor memory device of claim 1, wherein the patterned conductor layer comprises an array of conductor elements arranged in rows and columns, each of the conductor units having a width W in a row direction, and wherein the patterning The dielectric layer includes an array of dielectric cells, each of the dielectric cells having a width W ₁ in the row direction, wherein the width W _{1 is} less than the width W. The semiconductor memory device of claim 2, wherein the isolation structure comprises a first isolation structure and a second isolation structure, the first block of the first isolation structure extending into the conductor unit a first conductor unit having a width T in the row direction, and the second block of the second isolation structure extending to the first conductor unit and having a width T in the row direction, wherein W= W ₁ +2T. The semiconductor memory device of claim 2, wherein the isolation structure comprises a first isolation structure, the first block of the first isolation structure extending to a first conductor unit in the conductor unit And the first block of the first isolation structure is coplanar with the first side of the first conductor unit in the row direction. The semiconductor memory device of claim 4, wherein the isolation structure comprises a second isolation structure, the second block of the second isolation structure extends to the first conductor unit, and The second block of the second isolation structure is coplanar with the second side of the first conductor unit in the row direction. The semiconductor memory device of claim 2, wherein the isolation structure comprises a first isolation structure, the first block of the first isolation structure extending to a first conductor unit in the conductor unit And the second block of the first isolation structure extends to a second conductor unit in the conductor unit, the first conductor unit being in close proximity to the second conductor unit in the row direction. A semiconductor memory device comprising: a substrate; a patterned dielectric layer on the substrate; an array of conductor cells arranged in rows and columns on the patterned dielectric layer, each of the conductor units having a first portion And a second portion, the first portion is on the patterned dielectric layer and has a width W _{1 in a} row direction, and the second portion is above the patterned dielectric layer and in the row direction Having a width W, wherein W _{1 is} less than W; and a plurality of isolation structures providing electrical isolation to the conductor elements, each of the isolation structures including a base, a first block, and a second block, the base being located In the substrate, the first block extends from the base to one of the conductor units and the second block extends from the base to the other of the conductor units, wherein the conductor The other of the cells is in close proximity to the one of the conductor units in the row direction, wherein the first block and the second block are separated from each other above the substrate, wherein Across the first block and The configuration of each of said spacer block having a second width W ₂ in the row direction, and the first block and second block according to any one of the T has a width in the row direction, wherein T is between 1/4 W ₂ and 1/3 W ₂ . The semiconductor memory device of claim 7, wherein the patterned dielectric layer comprises an array of dielectric cells, each of the dielectric cells having a width W ₁ in the row direction. The semiconductor memory device of claim 7, wherein the isolation structure comprises a first isolation structure and a second isolation structure, the first block of the first isolation structure extending into the conductor unit a first conductor unit having a width T in the row direction, and the second block of the second isolation structure extending to the first conductor unit and having a width T in the row direction, wherein W= W ₁ +2T. The semiconductor memory device of claim 7, wherein the isolation structure comprises a first isolation structure, the first block of the first isolation structure extending to a first conductor unit in the conductor unit And the first block of the first isolation structure is coplanar with the first side of the first conductor unit in the row direction. The semiconductor memory device of claim 10, wherein the isolation structure comprises a second isolation structure, the second block of the second isolation structure extends to the first conductor unit, and The second block of the second isolation structure is coplanar with the second side of the first conductor unit in the row direction. The semiconductor memory device of claim 11, wherein any one of the first block of the first isolation structure and the second block of the second isolation structure is The first portion of the first conductor unit is coupled to the second portion. A semiconductor memory device comprising: a substrate; and a memory cell array arranged in rows and columns on the substrate, each of the memory cells comprising: a dielectric unit on the substrate; and a conductor unit, including the dielectric layer a first portion on the electrical unit and a second portion above the dielectric unit, wherein the first portion has a first width in a row direction and the second portion has a second width in the row direction, the a width smaller than the second width, the surface of the second portion of the conductive unit is a plane; the first isolation structure includes a first block, the first block and the first of the conductor unit One portion is coupled to the second portion; and the second isolation structure includes a second block, the second block being coupled to the first portion of the conductor unit and the second portion, the first region And the second block is separated from each other above the substrate, wherein the first and second isolation structures spanning the first block and the second block are respectively in the row direction With width W ₂ , and any one of the first block and the second block has a width T in the row direction, wherein T is between 1/4 W ₂ and 1/3 W ₂ . The semiconductor memory device of claim 13, wherein the second width is W, conforming to: W = W ₁ + 2T, wherein W ₁ represents a width of the dielectric unit in the row direction, and T represents the width of the first block and the second block in the row direction. A method of fabricating a semiconductor memory device, comprising: providing a substrate; forming a patterned first dielectric layer on the substrate; forming a patterned second dielectric layer on the patterned first dielectric layer, Wherein the patterned first and second dielectric layers expose portions of the substrate; forming a trench via the exposed portion of the substrate; filling the trench with a dielectric material to form a first isolation trench; Partially removing the height of the patterned second dielectric layer to form a patterned dielectric layer; etching the first isolation trench to form a second isolation trench, wherein each of the second isolation trenches has a top and First and second shoulders on one side of the top portion; removing the patterned dielectric layer; forming a patterned conductor layer on the patterned first dielectric layer, wherein The patterned conductor layer is on the same level as the top of the second isolation trench; and the third isolation trench is formed by removing the top of the second isolation trench The third isolation trench includes the first and second shoulders and an exposed surface that is lower than the first and second shoulders. The method of fabricating a semiconductor memory device according to claim 15, wherein the method of forming the patterned first and second dielectric layers comprises: forming a first dielectric layer on the substrate; Forming a second dielectric layer on the first dielectric layer; patterning the second dielectric layer to form the patterned second dielectric layer; and patterning the first dielectric layer to form The patterned first dielectric layer. The method of fabricating a semiconductor memory device according to claim 16, wherein the first dielectric layer comprises one of cerium oxide and cerium oxynitride and the second dielectric layer comprises cerium nitride. The manufacturing method of the semiconductor memory device of claim 15, after the trench is filled with the dielectric material to form the first isolation trench, the method further includes: performing the chemical mechanical polishing process An isolation trench is coplanar with the patterned second dielectric layer. The method of fabricating a semiconductor memory device according to claim 18, wherein the dielectric material filled in the trench comprises ruthenium oxide. The method of fabricating a semiconductor memory device according to claim 15, wherein the patterned conductor layer comprises an array of conductor segments, each conductor segment further comprising a layer on the patterned first dielectric layer. a first segment and a second segment on the patterned first dielectric layer, the first segment having a width "W ₁ " in a reference direction and the second segment being There is a width "W" in the reference direction, where W _{1 is} less than W. The method of fabricating a semiconductor memory device according to claim 20, wherein the first and second shoulder portions of each of the third isolation trenches have a width "T" in the reference direction, wherein W = W ₁ + 2T. The method of fabricating a semiconductor memory device according to claim 21, wherein each of said third isolation trenches across said first and second shoulders has a width "W ₂ " in said reference direction , and T is equal to or less than 1/3W ₂ . The method of fabricating a semiconductor memory device according to claim 20, wherein the first shoulder of one of the third isolation trenches extends to a first conductor segment of the conductor segment, And the second shoulder of the one of the third isolation trenches extends to a second conductor segment in the conductor segment, the first conductor segment and the second conductor segment Adjacent to each other in the reference direction. The method of fabricating a semiconductor memory device according to claim 20, wherein the first shoulder of the first one of the third isolation trenches extends to one of the conductor segments, and The second shoulder of the second one of the third isolation trench extends to the one of the conductor segments, the first one of the third isolation trench and the second one being The reference directions are adjacent to each other.