TWI489600B - 半導體堆疊結構及其製法 - Google Patents

半導體堆疊結構及其製法 Download PDF

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TWI489600B
TWI489600B TW101149480A TW101149480A TWI489600B TW I489600 B TWI489600 B TW I489600B TW 101149480 A TW101149480 A TW 101149480A TW 101149480 A TW101149480 A TW 101149480A TW I489600 B TWI489600 B TW I489600B
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semiconductor stacked
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何彥仕
關欣
尤龍生
劉滄宇
鄭家明
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精材科技股份有限公司
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Description

半導體堆疊結構及其製法
本發明係有關一種半導體堆疊結構及製法，尤係關於一種不同規格之晶圓相堆疊之半導體堆疊結構及其製法。
隨著電子產業的蓬勃發展，當半導體平面封裝相關技術到達極限，可藉由積體化滿足微小化的需求。堆疊晶圓之技術係為新發展之領域，對未來科技有很大的助力，目前，係朝將多個同質或異質之晶圓堆疊作發展，以達多功能之目的。
一般晶圓封裝廠的設備中，一套製程設備僅限於加工一種規格的晶圓，若要加工其他規格的晶圓，則需重新增設另一套製程設備。例如：8吋晶圓廠的設備用於加工8吋晶圓，12吋晶圓廠的設備用於加工12吋晶圓。而隨著科技發展迅速，新發展的電子產品需要新設計之晶片，故晶片加工廠需新蓋廠房或新增設備，以因應新電子產品之需求。
惟，以目前電子產品之競爭現況，晶片加工廠藉由新蓋廠房或新增設備的速度係無法配合電子產品之汰換速度，亦即晶片加工廠難以即時供應所需之晶片封裝件。
因此，如何滿足晶圓加工對電子產品之需求量，實已成目前亟欲解決的課題。
為克服上述習知技術之問題，本發明遂提供一種半導 體堆疊結構之製法，係先將晶圓進行切割以形成複數晶片，再將各該晶片重新排設以配合所需之基板規格；接著，提供表面具有複數壩塊之一基板，以藉由各該壩塊，使各該晶片結合於該基板上；再於晶片上進行線路重佈層(Redistribution Layer,RDL)之製程；最後，進行切割以形成複數該半導體堆疊結構。
前述之製法中，可於承載件上進行重新排設，且該承載件上設有複數定位部，可令該些定位部對應位於各該晶片之間，使各該晶片之間具有間距。
前述之製法中，可於切割該晶圓前，先研磨該晶圓。
本發明復提供一種半導體堆疊結構，係包括：晶片、以及藉由壩塊可對應結合該晶片之基板。該晶片之表面具有線路重佈層，且該晶片之側面上具有隔離層，又該晶片之表面與該線路重佈層上形成有保護層。
前述之結構中，該隔離層復可形成於該晶片與該線路重佈層之間。
前述之結構及其製法中，該基板可為矽基板或玻璃板。
由上可知，本發明之半導體堆疊結構及其製法，主要藉由現有設備將一新規格之晶圓切割為複數晶片，再將各該晶片經重新排設成現有規格之晶圓樣式，以堆疊於現有規格之基板，故可使用現有設備進行後續製程。因此，對於新規格之晶圓，本發明之製法係使用現有設備加工，而無需新蓋廠房或新增設備，故可即時供應所需之晶片封裝 件，以配合電子產品之汰換速度。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“一”、“上”、“側”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
在本發明中，晶圓經堆疊、封裝、切單後所形成之半導體封裝件可應用於，例如各種微機電系統(Micro Electro Mechanical System；MEMS)，尤其是或利用電性或電容變化來測量的影像感測器。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)或壓力感測器(process sensors)等半導體封裝件。
請參閱第1A至1G圖，係為本發明之半導體堆疊結構1之製法之第一實施例。
如第1A圖所示，提供一具有相對之第一表面10a與第二表面10b之晶圓1a，該晶圓1a之第一表面10a具有複數電性接觸墊100。於本實施利中，該晶圓1a係為12吋。
接著，將該晶圓1a之第一表面10a設置於一第一承載件3上。於本實施利中，該第一承載件3係為玻璃板，且該第一承載件3藉由黏著層30結合於該晶圓1a之第一表面10a上。
如第1B圖所示，研磨該晶圓1a之第二表面10b，以減少該晶圓1a之厚度，而達到薄化之需求。
如第1C圖所示，形成複數盲孔101於該晶圓1a之第二表面10b上，以令該些電性接觸墊100對應外露於各該盲孔101。
如第1D圖所示，於該晶圓1a之第二表面10b上進行切割，以形成複數晶片10，且該晶片具有相鄰該第一表面10a與第二表面10b之側面10c。
如第1E圖所示，將各該晶片10由該第一承載件3移至一具有複數定位部40之第二承載件4上，且該晶片10之第二表面10b設置於該第二承載件4上，以外露該晶片10之第一表面10a，並令該些定位部40對應位於各該晶片10之間，使各該晶片10之間具有間距D。
於本實施例中，該第二承載件4係為散熱膠帶、矽板 或玻璃板，且該定位部40係為該第二承載件4上之凸狀；詳細地，該定位部40與該第二承載件4為一體、或接置於該第二承載件4上。
藉由該些定位部40，使12吋晶圓1a所切割出之晶片10重新排設為對應8吋晶圓之樣式，即各該晶片10之間的間距D等同於8吋晶圓切割後各晶片間的間距。
如第1F圖所示，提供表面具有複數壩塊110之一基板11，以將各該電性接觸墊100對應各該壩塊110，使各該晶片10之第一表面10a結合於該基板11上。於本實施利中，該基板11係為矽基板或玻璃板。再者，該壩塊110依製程或結構之需求，可部分結合該電性接觸墊100、完全不接觸該電性接觸墊100、或完全接觸該電性接觸墊100。
接著，移除該第二承載件4及該些定位部40，再形成隔離層12於各該晶片10之第二表面10b、盲孔101之孔壁與各該晶片10之側面10c上，且該電性接觸墊100外露出該盲孔101。
接著，形成線路重佈層13於各該晶片10之第二表面10b上之部分隔離層12上，且形成導電盲孔130於該盲孔101中，以藉該導電盲孔130電性連接該線路重佈層13與該電性接觸墊100。
接著，形成保護層14於各該晶片10之第二表面10b上之隔離層12與該線路重佈層13上。
如第1G圖所示，沿各該晶片10之間的間距D切割該 基板11，以形成複數該半導體堆疊結構1。
於其他實施例中，依設計態樣，於切割該基板11時，可一併切割該壩塊110。
本發明半導體堆疊結構之製法中，可藉由8吋晶圓廠的設備將12吋晶圓1a切割為複數晶片10，再將各該晶片10經該第二承載件4及該些定位部40重新排設成8吋晶圓之樣式，以堆疊於8吋晶圓所對應之基板11上，故對於12吋晶圓1a而言，本發明之製法係可使用現有8吋晶圓廠的設備進行加工，而無需新蓋廠房或新增設備。
請參閱第2A至2G圖，係為本發明之半導體堆疊結構2之製法之第二實施例。本實施例與第一實施例之差異在於形成盲孔之步驟順序，其他相關製程均大致相同，故相同之處不加以詳述。
如第2A圖所示，提供一具有相對之第一表面20a與第二表面20b之晶圓2a，該晶圓2a之第一表面20a具有複數電性接觸墊200。
接著，經研磨該晶圓2a之第二表面20b，再將該晶圓2a切割成複數晶片20，且該晶片具有相鄰該第一表面20a與第二表面20b之側面20c。
如第2B圖所示，將各該晶片20設置於一具有複數定位部40’之第二承載件4上，且該晶片20之第二表面20b設置於該第二承載件4上，以外露該晶片20之第一表面20a，並令該些定位部40’對應位於各該晶片20之間，使各該晶片20之間具有間距D。
於本實施例中，該第二承載件4係為散熱膠帶，該定位部40’係為疊於該散熱膠帶上之網版，以將各該晶片20置於該網版之開口中。
如第2C圖所示，提供表面具有複數壩塊210之一基板21，以將各該電性接觸墊200結合各該壩塊210，使各該晶片20之第一表面20a結合於該基板21上。
如第2D圖所示，移除該第二承載件4及該些定位部40’。接著，形成複數盲孔201於各該晶片20之第二表面20b上，以令該些電性接觸墊200對應外露出各該盲孔201。
如第2E圖所示，形成隔離層22於各該晶片20之第二表面20b、盲孔201之孔壁與各該晶片20之側面20c上，且該電性接觸墊200外露出該盲孔201。
如第2F圖所示，形成線路重佈層23於各該晶片20之第二表面20b上之部分隔離層22上，且形成導電盲孔230於該盲孔201中，以藉該導電盲孔230電性連接該線路重佈層23與該電性接觸墊200。
如第2J圖所示，形成保護層24於各該晶片20之第二表面20b上之隔離層22與該線路重佈層23上。
如第2G圖所示，沿各該晶片20之間的間距D切割該基板21與該壩塊210，以形成複數該半導體堆疊結構2。
本發明復提供一種半導體堆疊結構1,2，係包括：具有相對之第一表面10a,20a、第二表面10b,20b及相鄰該第一表面10a,20a與第二表面10b,20b之側面10c,20c的晶片10,20、形成於該晶片10,20之第二表面10b,20b上 之保護層14,24、以及結合於該晶片10,20之第一表面10a,20a上之基板11,21。
所述之晶片10,20之第一表面10a,20a具有複數電性接觸墊100,200，且其第二表面10b,20b上具有線路重佈層13,23，而其側面10c,20c上具有隔離層12,22以防止該晶片10,20受損，又該晶片10,20中具有導電盲孔130,230以電性連接該線路重佈層13,23與該電性接觸墊100,200。另外，該隔離層12,22復形成於該晶片10,20之第二表面10b,20b與該線路重佈層13,23之間、及該導電盲孔130,230之孔壁上。
所述之保護層14,24復形成於該線路重佈層13,23上。
所述之基板11,21係為矽基板或玻璃板，其表面具有複數壩塊110,210以結合該電性接觸墊100,200，使該晶片10,20之第一表面10a,20a結合於該基板11,21上。
綜上所述，本發明之半導體堆疊結構及其製法，係藉由現有設備加工新規格之晶圓，因而針對新規格之晶圓無需新蓋廠房或新增設備，不僅降低成本，且可即時供應所需之晶片封裝件，以達到提升生產力之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2‧‧‧半導體堆疊結構
1a,2a‧‧‧晶圓
10,20‧‧‧晶片
10a,20a‧‧‧第一表面
10b,20b‧‧‧第二表面
10c,20c‧‧‧側面
100,200‧‧‧電性接觸墊
101,201‧‧‧盲孔
11,21‧‧‧基板
110,210‧‧‧壩塊
12,22‧‧‧隔離層
13,23‧‧‧線路重佈層
130,230‧‧‧導電盲孔
14,24‧‧‧保護層
3‧‧‧第一承載件
30‧‧‧黏著層
4‧‧‧第二承載件
40,40’‧‧‧定位部
D‧‧‧間距
第1A至1G圖係為本發明半導體堆疊結構之製法之剖面示意圖；以及第2A至2G圖係為本發明半導體堆疊結構之製法之剖面示意圖。
1‧‧‧半導體堆疊結構
10‧‧‧晶片
10a‧‧‧第一表面
10b‧‧‧第二表面
10c‧‧‧側面
100‧‧‧電性接觸墊
11‧‧‧基板
110‧‧‧壩塊
12‧‧‧隔離層
13‧‧‧線路重佈層
130‧‧‧導電盲孔
14‧‧‧保護層

Claims (16)

  1. 一種半導體堆疊結構之製法，係包括：提供一具有相對之第一表面與第二表面之晶圓，該晶圓之第一表面具有複數電性接觸墊；將該晶圓藉其第一表面設置於一第一承載件上；形成複數盲孔於該晶圓之第二表面上，以令該些電性接觸墊對應外露出各該盲孔；由該晶圓之第二表面切割該晶圓，以形成複數晶片；將各該晶片由該第一承載件移至一設有複數定位部之第二承載件上，且該晶片之第二表面設置於該第二承載件上，以外露該晶片之第一表面，並令該些定位部對應位於各該晶片之間，使各該晶片之間具有間距；提供表面具有複數壩塊之基板，以將各該晶片第一表面上之電性接觸墊對應各該壩塊，使各該晶片其第一表面結合於該基板上；移除該第二承載件及該些定位部；形成隔離層於各該晶片之第二表面、盲孔之孔壁與各該晶片之側面上，且該電性接觸墊外露出該盲孔；形成線路重佈層於各該晶片之第二表面上之部分隔離層上，且形成導電盲孔於該盲孔中，以藉該導電盲孔電性連接該線路重佈層與該電性接觸墊；形成保護層於各該晶片之第二表面上之隔離層與 該線路重佈層上；以及沿各該晶片之間的間距切割該基板，以形成複數該半導體堆疊結構。
  2. 如申請專利範圍第1項所述之半導體堆疊結構之製法，其中，該第一承載件係為玻璃板。
  3. 如申請專利範圍第1項所述之半導體堆疊結構之製法，其中，該第一承載件藉由黏著層結合於該晶圓之第一表面上。
  4. 如申請專利範圍第1項所述之半導體堆疊結構之製法，其中，該第二承載件係為散熱膠帶、矽板或玻璃板。
  5. 如申請專利範圍第1項所述之半導體堆疊結構之製法，其中，該定位部係為網版或該第二承載件上之凸狀。
  6. 如申請專利範圍第1項所述之半導體堆疊結構之製法，其中，該基板係為矽基板或玻璃板。
  7. 如申請專利範圍第1項所述之半導體堆疊結構之製法，復包括形成該盲孔之前，研磨該晶圓之第二表面。
  8. 如申請專利範圍第1項所述之半導體堆疊結構之製法，復包括切割該基板時，一併切割該壩塊。
  9. 一種半導體堆疊結構之製法，係包括：提供一具有相對之第一表面與第二表面之晶圓，該晶圓之第一表面具有複數電性接觸墊；將該晶圓藉其第一表面設置於一第一承載件上； 由該晶圓之第二表面切割該晶圓，以形成複數晶片；將各該晶片由該第一承載件移至一設有複數定位部之第二承載件上，且該晶片之第二表面設置於該第二承載件上，以外露該晶片之第一表面，並令該些定位部對應位於各該晶片之間，使各該晶片之間具有間距；提供表面具有複數壩塊之基板，以將各該晶片第一表面上之電性接觸墊對應各該壩塊，使各該晶片其第一表面結合於該基板上；移除該第二承載件及該些定位部；形成複數盲孔於各該晶片之第二表面上，以令該些電性接觸墊對應外露出各該盲孔；形成隔離層於各該晶片之第二表面、盲孔之孔壁與各該晶片之側面上，且該電性接觸墊外露出該盲孔；形成線路重佈層於各該晶片之第二表面上之部分隔離層上，且形成導電盲孔於該盲孔中，以藉該導電盲孔電性連接該線路重佈層與該電性接觸墊；形成保護層於各該晶片之第二表面上之隔離層與該線路重佈層上；以及沿各該晶片之間的間距切割該基板，以形成複數該半導體堆疊結構。
  10. 如申請專利範圍第9項所述之半導體堆疊結構之製法，其中，該第一承載件係為玻璃板。
  11. 如申請專利範圍第9項所述之半導體堆疊結構之製法，其中，該第一承載件藉由黏著層結合於該晶圓之第一表面上。
  12. 如申請專利範圍第9項所述之半導體堆疊結構之製法，其中，該第二承載件係為散熱膠帶、矽板或玻璃板。
  13. 如申請專利範圍第9項所述之半導體堆疊結構之製法，其中，該定位部係為網版或該第二承載件上之凸狀。
  14. 如申請專利範圍第9項所述之半導體堆疊結構之製法，其中，該基板係為矽基板或玻璃板。
  15. 如申請專利範圍第9項所述之半導體堆疊結構之製法，復包括於將該晶圓設置於該第一承載件上之前，研磨該晶圓之第二表面。
  16. 如申請專利範圍第9項所述之半導體堆疊結構之製法，復包括切割該基板時，一併切割該壩塊。
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